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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 106

Last change on this file since 106 was 106, checked in by rosiere, 15 years ago
1) RAT : Fix bug when update and event in same cycle 2) Context State : Compute depth 3) Load Store Unit : In check logic, translate all access in little endian. More easy to check 4) UFPT : End Event
Property svn:keywords set to `Id`
File size: 27.2 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 106 2009-02-09 22:55:26Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::transition"
21	void Context_State::transition (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_context; i++)
29	{
30	reg_STATE [i] = CONTEXT_STATE_OK;
31	reg_INTERRUPT_ENABLE [i] = 0;
32	}
33	}
34	else
35	{
36	// -------------------------------------------------------------------
37	// -----[ next state ]------------------------------------------------
38	// -------------------------------------------------------------------
39	for (uint32_t i=0; i<_param->_nb_context; i++)
40	{
41	// uint32_t x = _param->_link_context_to_decod_unit [i];
42
43	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
44	// Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
45
46	context_state_t state = reg_STATE [i];
47
48	switch (state)
49	{
50	case CONTEXT_STATE_OK :
51	{
52	// nothing, wait an event
53	break;
54	}
55	case CONTEXT_STATE_KO_EXCEP :
56	{
57	// Wait end of all instruction
58	if (inst_all == 0)
59	state = CONTEXT_STATE_KO_EXCEP_ADDR;
60	break;
61	}
62	case CONTEXT_STATE_KO_EXCEP_ADDR :
63	{
64	// nothing, wait the update of internal register (pc)
65	break;
66	}
67	case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
68	{
69	// Wait end of all instruction
70	if (inst_all == 0)
71
72	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
73	state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
74	break;
75	}
76	case CONTEXT_STATE_KO_MISS_LOAD_WAITEND :
77	{
78	// Wait end of all instruction
79	if (inst_all == 0)
80	state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
81
82	break;
83	}
84	case CONTEXT_STATE_KO_EXCEP_SPR :
85	{
86	// nothing, wait the update of internal register (epcr, eear, sr, esr)
87	break;
88	}
89	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR :
90	{
91	// nothing, wait the update of internal register (pc)
92	break;
93	}
94	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
95	{
96	// nothing, wait the update of internal register (pc)
97	break;
98	}
99	// case CONTEXT_STATE_KO_PSYNC :
100	// {
101	// // Wait end of all instruction
102	// if (inst_all == 0)
103	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
104	// break;
105	// }
106	case CONTEXT_STATE_KO_PSYNC_FLUSH :
107	{
108	// nothing, wait end of flush (ifetch)
109	if (inst_all == 0)
110	// state = CONTEXT_STATE_KO_PSYNC_ADDR;
111	state = CONTEXT_STATE_OK;
112
113	break;
114	}
115	case CONTEXT_STATE_KO_PSYNC_ADDR :
116	{
117	// nothing, wait the pc write
118	break;
119	}
120	// case CONTEXT_STATE_KO_CSYNC :
121	// {
122	// // Wait end of all instruction
123	// if (inst_all == 0)
124	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
125	// break;
126	// }
127	case CONTEXT_STATE_KO_CSYNC_FLUSH :
128	{
129	// nothing, wait end of flush (all internal structure)
130	if (inst_all == 0)
131	state = CONTEXT_STATE_KO_CSYNC_ADDR;
132	break;
133	}
134	case CONTEXT_STATE_KO_CSYNC_ADDR :
135	{
136	// nothing, wait the pc write
137	break;
138	}
139	// case CONTEXT_STATE_KO_MSYNC :
140	// {
141	// // Wait end of memory instruction
142	// if (inst_mem == 0)
143	// state = CONTEXT_STATE_KO_MSYNC_ISSUE;
144	// break;
145	// }
146	// case CONTEXT_STATE_KO_MSYNC_ISSUE :
147	// {
148	// // Wait the msync issue
149	// if (inst_mem != 0)
150	// state = CONTEXT_STATE_KO_MSYNC_EXEC;
151	// break;
152	// }
153	case CONTEXT_STATE_KO_MSYNC_EXEC :
154	{
155	// Wait the end of msync
156	if (inst_all == 0)
157	state = CONTEXT_STATE_OK;
158	break;
159	}
160	// case CONTEXT_STATE_KO_SPR :
161	// {
162	// // Wait end of all instruction
163	// if (inst_all == 0)
164	// state = CONTEXT_STATE_KO_SPR_ISSUE;
165	// break;
166	// }
167	// case CONTEXT_STATE_KO_SPR_ISSUE :
168	// {
169	// // Wait the spr_access issue
170	// if (inst_all != 0)
171	// state = CONTEXT_STATE_KO_SPR_EXEC;
172	// break;
173	// }
174	case CONTEXT_STATE_KO_SPR_EXEC :
175	{
176	// Wait the spr_access execution
177	if (inst_all == 0)
178	state = CONTEXT_STATE_OK;
179	break;
180	}
181
182	default :
183	{
184	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
185	}
186	}
187	reg_STATE [i] = state;
188	}
189
190	// -------------------------------------------------------------------
191	// -----[ BRANCH_EVENT ]----------------------------------------------
192	// -------------------------------------------------------------------
193	for (uint32_t i=0; i<_param->_nb_context; ++i)
194	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
195	{
196	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);
197
198	context_state_t state = reg_STATE [i];
199
200	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
201	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
202	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
203	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i];
204
205	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
206	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
207	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
208	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
209
210	// priority : miss > excep > spr/sync
211	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
212	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
213	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
214	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
215	uint8_t priority1 = 2; // miss
216
217	// is_valid = can modify local information
218	// if context_state_ok : yes
219	// if context_state_ko : test the depth, and the priority of event
220	bool is_valid = ((state == CONTEXT_STATE_OK) or
221	(depth1< depth0) or
222	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
223
224	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
225	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
226	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
227	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
228	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
229	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
230	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
231	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
232	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
233
234	if (is_valid)
235	{
236	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
237	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
238	reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
239	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
240	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
241	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
242	//reg_EVENT_ADDRESS_EEAR [i] = 0;
243	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
244	reg_EVENT_IS_DELAY_SLOT [i] = 1;
245	reg_EVENT_IS_DS_TAKE [i] = dest_val;
246	reg_EVENT_DEPTH [i] = depth;
247	}
248	}
249
250	// -------------------------------------------------------------------
251	// -----[ DECOD_EVENT ]-----------------------------------------------
252	// -------------------------------------------------------------------
253
254	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
255	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
256	{
257	log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);
258
259	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
260	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
261	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
262	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
263	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];
264
265	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
266	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
267	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
268	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
269
270	context_state_t state = reg_STATE [context];
271	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
272
273	// miss > excep > spr/sync
274	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
275	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
276	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
277	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
278	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
279
280	// is_valid = can modify local information
281	// if context_state_ok : yes
282	// if context_state_ko : test the depth, and the priority of envent
283
284	bool is_valid = ((state == CONTEXT_STATE_OK) or
285	(depth1< depth0) or
286	((depth1==depth0) and (priority1>=priority0)));
287
288	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
289	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
290	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
291	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
292	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
293	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
294	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
295	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
296	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
297
298	if (is_valid)
299	{
300	log_printf(TRACE,Context_State,FUNCTION," * is_valid");
301
302	// decod :
303	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
304	context_state_t state_next = state;
305	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
306	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
307
308	switch (type)
309	{
310	case EVENT_TYPE_EXCEPTION :
311	{
312	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");
313
314	state_next = CONTEXT_STATE_KO_EXCEP;
315
316	break;
317	}
318	case EVENT_TYPE_SPR_ACCESS :
319	{
320	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");
321
322	// state_next = CONTEXT_STATE_KO_SPR ;
323	state_next = CONTEXT_STATE_KO_SPR_EXEC;
324	address++; // take next address
325	// if (is_delay_slot)
326	// throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
327	break;
328	}
329	case EVENT_TYPE_MSYNC :
330	{
331	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");
332
333	// state_next = CONTEXT_STATE_KO_MSYNC;
334	state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
335	address++; // take next address
336	// if (is_delay_slot)
337	// throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
338	break;
339	}
340	case EVENT_TYPE_PSYNC :
341	{
342	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");
343
344	// state_next = CONTEXT_STATE_KO_PSYNC;
345	state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
346	address++; // take next address
347	if (is_delay_slot)
348	throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
349	break;
350	}
351	case EVENT_TYPE_CSYNC :
352	{
353	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");
354
355	// state_next = CONTEXT_STATE_KO_CSYNC;
356	state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
357	address++; // take next address
358	if (is_delay_slot)
359	throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
360	break;
361	}
362	case EVENT_TYPE_NONE :
363	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
364	case EVENT_TYPE_LOAD_MISS_SPECULATION :
365	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
366	default :
367	{
368	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
369	}
370	}
371
372	reg_STATE [context] = state_next;
373	reg_EVENT_ADDRESS [context] = address;
374	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
375	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
376	//reg_EVENT_ADDRESS_EEAR [context]
377	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
378	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
379	//reg_EVENT_IS_DS_TAKE [context] = 0;
380	reg_EVENT_DEPTH [context] = depth;
381	}
382	}
383
384	// -------------------------------------------------------------------
385	// -----[ COMMIT_EVENT ]----------------------------------------------
386	// -------------------------------------------------------------------
387
388	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
389	{
390	log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT");
391
392	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
393	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
394	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
395	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
396	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];
397
398	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
399	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
400	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
401	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
402
403	context_state_t state = reg_STATE [context];
404	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
405
406	// miss > excep > spr/sync
407	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
408	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
409	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
410	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
411	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
412
413	// is_valid = can modify local information
414	// if context_state_ok : yes
415	// if context_state_ko : test the depth, and the priority of envent
416
417	bool is_valid = ((state == CONTEXT_STATE_OK) or
418	(depth1< depth0) or
419	((depth1==depth0) and (priority1>=priority0)));
420
421	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
422	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
423	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
424	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
425	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
426	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
427	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
428	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
429	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
430
431	if (is_valid)
432	{
433	// commit
434	// type : exception
435	context_state_t state_next = state;
436	switch (type)
437	{
438	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
439	case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;}
440	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
441	case EVENT_TYPE_SPR_ACCESS :
442	case EVENT_TYPE_MSYNC :
443	case EVENT_TYPE_PSYNC :
444	case EVENT_TYPE_CSYNC :
445	case EVENT_TYPE_NONE :
446	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
447	default :
448	{
449	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
450	}
451	}
452	reg_STATE [context] = state_next;
453	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
454	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
455	reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
456	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
457	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
458	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
459	reg_EVENT_IS_DS_TAKE [context] = 0;
460	reg_EVENT_DEPTH [context] = depth;
461	}
462	}
463
464	// -------------------------------------------------------------------
465	// -----[ EVENT ]-----------------------------------------------------
466	// -------------------------------------------------------------------
467	for (uint32_t i=0; i<_param->_nb_context; i++)
468	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
469	{
470	log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);
471	// Write pc
472	context_state_t state = reg_STATE [i];
473
474	switch (state)
475	{
476	case CONTEXT_STATE_KO_EXCEP_ADDR :
477	{
478	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
479	break;
480	}
481	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
482	// {
483	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
484	// break;
485	// }
486	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
487	case CONTEXT_STATE_KO_PSYNC_ADDR :
488	case CONTEXT_STATE_KO_CSYNC_ADDR :
489	{
490	reg_STATE [i] = CONTEXT_STATE_OK;
491	break;
492	}
493	default :
494	{
495	#ifdef DEBUG_TEST
496	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
497	#endif
498	break;
499	}
500	}
501	}
502
503	// -------------------------------------------------------------------
504	// -----[ SPR_EVENT ]-------------------------------------------------
505	// -------------------------------------------------------------------
506	for (uint32_t i=0; i<_param->_nb_context; i++)
507	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
508	{
509	log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i);
510
511	// Write spr
512	#ifdef DEBUG_TEST
513	context_state_t state = reg_STATE [i];
514
515	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
516	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
517	#endif
518
519	reg_STATE [i] = CONTEXT_STATE_OK;
520	}
521
522	for (uint32_t i=0; i<_param->_nb_context; ++i)
523	{
524	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
525
526	if (reg_INTERRUPT_ENABLE [i])
527	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
528	}
529	}
530
531	#if DEBUG >= DEBUG_TRACE
532	for (uint32_t i=0; i<_param->_nb_context; i++)
533	{
534	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
535	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
536	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
537	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
538	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
539	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
540	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
541	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
542	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
543	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
544	}
545	#endif
546
547	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
548	end_cycle ();
549	#endif
550
551	log_end(Context_State,FUNCTION);
552	};
553
554	}; // end namespace context_state
555	}; // end namespace front_end
556	}; // end namespace multi_front_end
557	}; // end namespace core
558
559	}; // end namespace behavioural
560	}; // end namespace morpheo
561	#endif

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