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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 108

Last change on this file since 108 was 108, checked in by rosiere, 15 years ago
1) decod_queue : add reg_LAST_SLOT. 2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not) 3) Context State / UPT : Branch miss and Load miss in same cycle. 4) Free List : Bank is on LSB not MSB. 5) Platforms : move data
Property svn:keywords set to `Id`
File size: 29.3 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 108 2009-02-12 11:55:06Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::transition"
21	void Context_State::transition (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_context; i++)
29	{
30	reg_STATE [i] = CONTEXT_STATE_OK;
31	reg_INTERRUPT_ENABLE [i] = 0;
32	}
33	}
34	else
35	{
36	// -------------------------------------------------------------------
37	// -----[ next state ]------------------------------------------------
38	// -------------------------------------------------------------------
39	for (uint32_t i=0; i<_param->_nb_context; i++)
40	{
41	// uint32_t x = _param->_link_context_to_decod_unit [i];
42
43	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
44	// Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
45
46	context_state_t state = reg_STATE [i];
47
48	switch (state)
49	{
50	case CONTEXT_STATE_OK :
51	{
52	// nothing, wait an event
53	break;
54	}
55	case CONTEXT_STATE_KO_EXCEP :
56	{
57	// Wait end of all instruction
58	if (inst_all == 0)
59	state = CONTEXT_STATE_KO_EXCEP_ADDR;
60	break;
61	}
62	case CONTEXT_STATE_KO_EXCEP_ADDR :
63	{
64	// nothing, wait the update of internal register (pc)
65	break;
66	}
67	case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
68	{
69	// Wait end of all instruction
70	if (inst_all == 0)
71
72	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
73	state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
74	break;
75	}
76	case CONTEXT_STATE_KO_MISS_LOAD_WAITEND :
77	{
78	// Wait end of all instruction
79	if (inst_all == 0)
80	state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
81
82	break;
83	}
84	case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND :
85	{
86	// Wait end of all instruction
87	if (inst_all == 0)
88
89	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
90	state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR;
91	break;
92	}
93	case CONTEXT_STATE_KO_EXCEP_SPR :
94	{
95	// nothing, wait the update of internal register (epcr, eear, sr, esr)
96	break;
97	}
98	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR :
99	{
100	// nothing, wait the update of internal register (pc)
101	break;
102	}
103	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
104	{
105	// nothing, wait the update of internal register (pc)
106	break;
107	}
108	case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR :
109	{
110	// nothing, wait the update of internal register (pc)
111	break;
112	}
113	// case CONTEXT_STATE_KO_PSYNC :
114	// {
115	// // Wait end of all instruction
116	// if (inst_all == 0)
117	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
118	// break;
119	// }
120	case CONTEXT_STATE_KO_PSYNC_FLUSH :
121	{
122	// nothing, wait end of flush (ifetch)
123	if (inst_all == 0)
124	// state = CONTEXT_STATE_KO_PSYNC_ADDR;
125	state = CONTEXT_STATE_OK;
126
127	break;
128	}
129	case CONTEXT_STATE_KO_PSYNC_ADDR :
130	{
131	// nothing, wait the pc write
132	break;
133	}
134	// case CONTEXT_STATE_KO_CSYNC :
135	// {
136	// // Wait end of all instruction
137	// if (inst_all == 0)
138	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
139	// break;
140	// }
141	case CONTEXT_STATE_KO_CSYNC_FLUSH :
142	{
143	// nothing, wait end of flush (all internal structure)
144	if (inst_all == 0)
145	state = CONTEXT_STATE_KO_CSYNC_ADDR;
146	break;
147	}
148	case CONTEXT_STATE_KO_CSYNC_ADDR :
149	{
150	// nothing, wait the pc write
151	break;
152	}
153	// case CONTEXT_STATE_KO_MSYNC :
154	// {
155	// // Wait end of memory instruction
156	// if (inst_mem == 0)
157	// state = CONTEXT_STATE_KO_MSYNC_ISSUE;
158	// break;
159	// }
160	// case CONTEXT_STATE_KO_MSYNC_ISSUE :
161	// {
162	// // Wait the msync issue
163	// if (inst_mem != 0)
164	// state = CONTEXT_STATE_KO_MSYNC_EXEC;
165	// break;
166	// }
167	case CONTEXT_STATE_KO_MSYNC_EXEC :
168	{
169	// Wait the end of msync
170	if (inst_all == 0)
171	state = CONTEXT_STATE_OK;
172	break;
173	}
174	// case CONTEXT_STATE_KO_SPR :
175	// {
176	// // Wait end of all instruction
177	// if (inst_all == 0)
178	// state = CONTEXT_STATE_KO_SPR_ISSUE;
179	// break;
180	// }
181	// case CONTEXT_STATE_KO_SPR_ISSUE :
182	// {
183	// // Wait the spr_access issue
184	// if (inst_all != 0)
185	// state = CONTEXT_STATE_KO_SPR_EXEC;
186	// break;
187	// }
188	case CONTEXT_STATE_KO_SPR_EXEC :
189	{
190	// Wait the spr_access execution
191	if (inst_all == 0)
192	state = CONTEXT_STATE_OK;
193	break;
194	}
195
196	default :
197	{
198	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
199	}
200	}
201	reg_STATE [i] = state;
202	}
203
204	// -------------------------------------------------------------------
205	// -----[ BRANCH_EVENT ]----------------------------------------------
206	// -------------------------------------------------------------------
207	for (uint32_t i=0; i<_param->_nb_context; ++i)
208	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
209	{
210	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);
211
212	context_state_t state = reg_STATE [i];
213
214	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
215	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
216	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
217	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i];
218
219	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
220	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
221	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
222	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
223
224	// priority : miss > excep > spr/sync
225	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
226	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
227	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or
228	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or
229	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or
230	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
231	uint8_t priority1 = 2; // miss
232
233	// is_valid = can modify local information
234	// if context_state_ok : yes
235	// if context_state_ko : test the depth, and the priority of event
236	bool is_valid = ((state == CONTEXT_STATE_OK) or
237	(depth1< depth0) or
238	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
239
240	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
241	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
242	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
243	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
244	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
245	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
246	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
247	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
248	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
249
250	if (is_valid)
251	{
252	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
253	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
254	reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
255	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
256	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
257	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
258	//reg_EVENT_ADDRESS_EEAR [i] = 0;
259	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
260	reg_EVENT_IS_DELAY_SLOT [i] = 1;
261	reg_EVENT_IS_DS_TAKE [i] = dest_val;
262	reg_EVENT_DEPTH [i] = depth;
263	}
264	}
265
266	// -------------------------------------------------------------------
267	// -----[ DECOD_EVENT ]-----------------------------------------------
268	// -------------------------------------------------------------------
269
270	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
271	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
272	{
273	log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);
274
275	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
276	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
277	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
278	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
279	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];
280
281	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
282	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
283	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
284	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
285
286	context_state_t state = reg_STATE [context];
287	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
288
289	// miss > excep > spr/sync
290	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
291	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
292	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or
293	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or
294	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or
295	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
296	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
297
298	// is_valid = can modify local information
299	// if context_state_ok : yes
300	// if context_state_ko : test the depth, and the priority of envent
301
302	bool is_valid = ((state == CONTEXT_STATE_OK) or
303	(depth1< depth0) or
304	((depth1==depth0) and (priority1>=priority0)));
305
306	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
307	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
308	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
309	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
310	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
311	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
312	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
313	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
314	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
315
316	if (is_valid)
317	{
318	log_printf(TRACE,Context_State,FUNCTION," * is_valid");
319
320	// decod :
321	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
322	context_state_t state_next = state;
323	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
324	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
325
326	switch (type)
327	{
328	case EVENT_TYPE_EXCEPTION :
329	{
330	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");
331
332	state_next = CONTEXT_STATE_KO_EXCEP;
333
334	break;
335	}
336	case EVENT_TYPE_SPR_ACCESS :
337	{
338	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");
339
340	// state_next = CONTEXT_STATE_KO_SPR ;
341	state_next = CONTEXT_STATE_KO_SPR_EXEC;
342	address++; // take next address
343	// if (is_delay_slot)
344	// throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
345	break;
346	}
347	case EVENT_TYPE_MSYNC :
348	{
349	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");
350
351	// state_next = CONTEXT_STATE_KO_MSYNC;
352	state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
353	address++; // take next address
354	// if (is_delay_slot)
355	// throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
356	break;
357	}
358	case EVENT_TYPE_PSYNC :
359	{
360	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");
361
362	// state_next = CONTEXT_STATE_KO_PSYNC;
363	state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
364	address++; // take next address
365	if (is_delay_slot)
366	throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
367	break;
368	}
369	case EVENT_TYPE_CSYNC :
370	{
371	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");
372
373	// state_next = CONTEXT_STATE_KO_CSYNC;
374	state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
375	address++; // take next address
376	if (is_delay_slot)
377	throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
378	break;
379	}
380	case EVENT_TYPE_NONE :
381	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
382	case EVENT_TYPE_LOAD_MISS_SPECULATION :
383	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
384	default :
385	{
386	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
387	}
388	}
389
390	reg_STATE [context] = state_next;
391	reg_EVENT_ADDRESS [context] = address;
392	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
393	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
394	//reg_EVENT_ADDRESS_EEAR [context]
395	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
396	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
397	//reg_EVENT_IS_DS_TAKE [context] = 0;
398	reg_EVENT_DEPTH [context] = depth;
399	}
400	}
401
402	// -------------------------------------------------------------------
403	// -----[ COMMIT_EVENT ]----------------------------------------------
404	// -------------------------------------------------------------------
405
406	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
407	{
408	log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT");
409
410	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
411	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
412	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
413	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
414	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];
415
416	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
417	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
418	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
419	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
420
421	context_state_t state = reg_STATE [context];
422	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
423
424	// miss > excep > spr/sync
425	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
426	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
427	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or
428	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or
429	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or
430	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
431	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
432
433	// is_valid = can modify local information
434	// if context_state_ok : yes
435	// if context_state_ko : test the depth, and the priority of envent
436
437	bool is_valid = ((state == CONTEXT_STATE_OK) or
438	(depth1< depth0) or
439	((depth1==depth0) and (priority1>=priority0)));
440
441	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
442	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
443	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
444	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
445	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
446	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
447	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
448	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
449	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
450
451	if (is_valid)
452	{
453	// commit
454	// type : exception
455	context_state_t state_next = state;
456	switch (type)
457	{
458	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
459	case EVENT_TYPE_LOAD_MISS_SPECULATION :
460	{
461	// Test if previous branch occure
462	if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
463	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or
464	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or
465	(state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))
466	state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND;
467	else
468	state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
469	break;
470	}
471	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
472	case EVENT_TYPE_SPR_ACCESS :
473	case EVENT_TYPE_MSYNC :
474	case EVENT_TYPE_PSYNC :
475	case EVENT_TYPE_CSYNC :
476	case EVENT_TYPE_NONE :
477	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
478	default :
479	{
480	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
481	}
482	}
483	reg_STATE [context] = state_next;
484	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
485	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
486	reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
487	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
488	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
489	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
490	reg_EVENT_IS_DS_TAKE [context] = 0;
491	reg_EVENT_DEPTH [context] = depth;
492	}
493	}
494
495	// -------------------------------------------------------------------
496	// -----[ EVENT ]-----------------------------------------------------
497	// -------------------------------------------------------------------
498	for (uint32_t i=0; i<_param->_nb_context; i++)
499	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
500	{
501	log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);
502	// Write pc
503	context_state_t state = reg_STATE [i];
504
505	switch (state)
506	{
507	case CONTEXT_STATE_KO_EXCEP_ADDR :
508	{
509	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
510	break;
511	}
512	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
513
514	// {
515	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
516	// break;
517	// }
518	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
519	case CONTEXT_STATE_KO_PSYNC_ADDR :
520	case CONTEXT_STATE_KO_CSYNC_ADDR :
521	{
522	reg_STATE [i] = CONTEXT_STATE_OK;
523	break;
524	}
525	case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR:
526	{
527	reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
528	break;
529	}
530	default :
531	{
532	#ifdef DEBUG_TEST
533	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
534	#endif
535	break;
536	}
537	}
538	}
539
540	// -------------------------------------------------------------------
541	// -----[ SPR_EVENT ]-------------------------------------------------
542	// -------------------------------------------------------------------
543	for (uint32_t i=0; i<_param->_nb_context; i++)
544	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
545	{
546	log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i);
547
548	// Write spr
549	#ifdef DEBUG_TEST
550	context_state_t state = reg_STATE [i];
551
552	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
553	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
554	#endif
555
556	reg_STATE [i] = CONTEXT_STATE_OK;
557	}
558
559	for (uint32_t i=0; i<_param->_nb_context; ++i)
560	{
561	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
562
563	if (reg_INTERRUPT_ENABLE [i])
564	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
565	}
566	}
567
568	#if DEBUG >= DEBUG_TRACE
569	for (uint32_t i=0; i<_param->_nb_context; i++)
570	{
571	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
572	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
573	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
574	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
575	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
576	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
577	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
578	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
579	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
580	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
581	}
582	#endif
583
584	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
585	end_cycle ();
586	#endif
587
588	log_end(Context_State,FUNCTION);
589	};
590
591	}; // end namespace context_state
592	}; // end namespace front_end
593	}; // end namespace multi_front_end
594	}; // end namespace core
595
596	}; // end namespace behavioural
597	}; // end namespace morpheo
598	#endif

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