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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 16 years ago
1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...) 2) Change VHDL Execute_queue -> use Generic/Queue? 3) Complete document on VHDL generation 4) Add soc test
Property svn:keywords set to `Id`
File size: 25.1 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 98 2008-12-31 10:18:08Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::transition"
21	void Context_State::transition (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_context; i++)
29	{
30	reg_STATE [i] = CONTEXT_STATE_OK;
31	reg_INTERRUPT_ENABLE [i] = 0;
32	}
33	}
34	else
35	{
36	// -------------------------------------------------------------------
37	// -----[ BRANCH_EVENT ]----------------------------------------------
38	// -------------------------------------------------------------------
39	for (uint32_t i=0; i<_param->_nb_context; ++i)
40	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
41	{
42	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);
43
44	// throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n"));
45
46	context_state_t state = reg_STATE [i];
47
48	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
49	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
50	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
51	Tdepth_t depth_max = _param->_array_size_depth [i];
52
53	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
54	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
55	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
56	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
57
58	// priority : miss > excep > spr/sync
59	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
60	uint8_t priority1 = 2; // miss
61
62	// is_valid = can modify local information
63	// if context_state_ok : yes
64	// if context_state_ko : test the depth, and the priority of event
65
66	bool is_valid = ((state == CONTEXT_STATE_OK) or
67	(depth1< depth0) or
68	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
69
70	if (is_valid)
71	{
72	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
73	reg_STATE [i] = CONTEXT_STATE_KO_MISS;
74	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
75	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
76	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
77	//reg_EVENT_ADDRESS_EEAR [i] = 0;
78	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
79	reg_EVENT_IS_DELAY_SLOT [i] = 1;
80	reg_EVENT_IS_DS_TAKE [i] = dest_val;
81	reg_EVENT_DEPTH [i] = depth;
82	}
83	}
84
85	// -------------------------------------------------------------------
86	// -----[ DECOD_EVENT ]-----------------------------------------------
87	// -------------------------------------------------------------------
88
89	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
90	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
91	{
92	log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);
93
94	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
95	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
96	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
97	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
98	Tdepth_t depth_max = _param->_array_size_depth [context];
99
100	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
101	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
102	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
103	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
104
105	context_state_t state = reg_STATE [context];
106	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
107
108	// miss > excep > spr/sync
109	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
110	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
111
112	// is_valid = can modify local information
113	// if context_state_ok : yes
114	// if context_state_ko : test the depth, and the priority of envent
115
116	bool is_valid = ((state == CONTEXT_STATE_OK) or
117	(depth1< depth0) or
118	((depth1==depth0) and (priority1>priority0)));
119
120	if (is_valid)
121	{
122	// decod :
123	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
124	context_state_t state_next = state;
125	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
126	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
127
128	switch (type)
129	{
130	case EVENT_TYPE_EXCEPTION :
131	{
132	state_next = CONTEXT_STATE_KO_EXCEP;
133
134	break;
135	}
136	case EVENT_TYPE_SPR_ACCESS :
137	{
138	state_next = CONTEXT_STATE_KO_SPR ;
139	address++; // take next address
140	if (is_delay_slot)
141	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
142	break;
143	}
144	case EVENT_TYPE_MSYNC :
145	{
146	state_next = CONTEXT_STATE_KO_MSYNC;
147	address++; // take next address
148	if (is_delay_slot)
149	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
150	break;
151	}
152	case EVENT_TYPE_PSYNC :
153	{
154	state_next = CONTEXT_STATE_KO_PSYNC;
155	address++; // take next address
156	if (is_delay_slot)
157	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
158	break;
159	}
160	case EVENT_TYPE_CSYNC :
161	{
162	state_next = CONTEXT_STATE_KO_CSYNC;
163	address++; // take next address
164	if (is_delay_slot)
165	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
166	break;
167	}
168	case EVENT_TYPE_NONE :
169	case EVENT_TYPE_MISS_SPECULATION :
170	case EVENT_TYPE_BRANCH_NO_ACCURATE :
171	default :
172	{
173	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
174	}
175	}
176
177	reg_STATE [context] = state_next;
178	reg_EVENT_ADDRESS [context] = address;
179	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
180	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
181	//reg_EVENT_ADDRESS_EEAR [context]
182	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
183	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
184	//reg_EVENT_IS_DS_TAKE [context] = 0;
185	reg_EVENT_DEPTH [context] = depth;
186	}
187	}
188
189	// -------------------------------------------------------------------
190	// -----[ COMMIT_EVENT ]----------------------------------------------
191	// -------------------------------------------------------------------
192
193	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
194	{
195	log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT");
196
197	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
198	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
199	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
200	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
201	Tdepth_t depth_max = _param->_array_size_depth [context];
202
203	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
204	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
205	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
206	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
207
208	context_state_t state = reg_STATE [context];
209	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
210
211	// miss > excep > spr/sync
212	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
213	uint8_t priority1 = 1; // exception
214
215	// is_valid = can modify local information
216	// if context_state_ok : yes
217	// if context_state_ko : test the depth, and the priority of envent
218
219	bool is_valid = ((state == CONTEXT_STATE_OK) or
220	(depth1< depth0) or
221	((depth1==depth0) and (priority1>priority0)));
222
223	if (is_valid)
224	{
225	// commit
226	// type : exception
227	context_state_t state_next = state;
228	switch (type)
229	{
230	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
231	case EVENT_TYPE_SPR_ACCESS :
232	case EVENT_TYPE_MSYNC :
233	case EVENT_TYPE_PSYNC :
234	case EVENT_TYPE_CSYNC :
235	case EVENT_TYPE_NONE :
236	case EVENT_TYPE_MISS_SPECULATION :
237	case EVENT_TYPE_BRANCH_NO_ACCURATE :
238	default :
239	{
240	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
241	}
242	}
243	reg_STATE [context] = state_next;
244	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
245	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
246	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
247	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
248	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
249	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
250	//reg_EVENT_IS_DS_TAKE [context] = 0;
251	reg_EVENT_DEPTH [context] = depth;
252	}
253	}
254
255	// -------------------------------------------------------------------
256	// -----[ BRANCH_COMPLETE ]-------------------------------------------
257	// -------------------------------------------------------------------
258
259	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
260	// if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i])
261	// {
262	// log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i);
263	// if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))
264	// {
265	// Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
266	// Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
267	// Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
268	// Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
269	// Tdepth_t depth_max = _param->_array_size_depth [context];
270
271	// // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
272	// // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
273	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
274	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
275
276	// context_state_t state = reg_STATE [context];
277
278	// // miss > excep > spr/sync
279	// uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
280	// uint8_t priority1 = 2; // miss
281
282	// // is_valid = can modify local information
283	// // if context_state_ok : yes
284	// // if context_state_ko : test the depth, and the priority of envent
285
286	// bool is_valid = ((state == CONTEXT_STATE_OK) or
287	// (depth1< depth0) or
288	// ((depth1==depth0) and (priority1>priority0)));
289
290	// if (is_valid)
291	// {
292	// // commit
293	// Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);
294	// reg_STATE [context] = CONTEXT_STATE_KO_MISS;
295	// reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT
296	// reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);
297	// reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence
298	// //reg_EVENT_ADDRESS_EEAR [context];
299	// reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
300	// reg_EVENT_IS_DELAY_SLOT [context] = take;
301	// reg_EVENT_IS_DS_TAKE [context] = take;
302	// reg_EVENT_DEPTH [context] = depth;
303	// }
304	// }
305	// }
306
307	// -------------------------------------------------------------------
308	// -----[ EVENT ]-----------------------------------------------------
309	// -------------------------------------------------------------------
310	for (uint32_t i=0; i<_param->_nb_context; i++)
311	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
312	{
313	log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);
314	// Write pc
315	context_state_t state = reg_STATE [i];
316
317	switch (state)
318	{
319	case CONTEXT_STATE_KO_EXCEP_ADDR :
320	{
321	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
322	break;
323	}
324	case CONTEXT_STATE_KO_MISS_ADDR :
325	case CONTEXT_STATE_KO_PSYNC_ADDR :
326	case CONTEXT_STATE_KO_CSYNC_ADDR :
327	{
328	reg_STATE [i] = CONTEXT_STATE_OK;
329	break;
330	}
331	default :
332	{
333	#ifdef DEBUG_TEST
334	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
335	#endif
336	break;
337	}
338	}
339	}
340
341	// -------------------------------------------------------------------
342	// -----[ SPR_EVENT ]-------------------------------------------------
343	// -------------------------------------------------------------------
344	for (uint32_t i=0; i<_param->_nb_context; i++)
345	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
346	{
347	log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i);
348
349	// Write spr
350	#ifdef DEBUG_TEST
351	context_state_t state = reg_STATE [i];
352
353	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
354	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
355	#endif
356
357	reg_STATE [i] = CONTEXT_STATE_OK;
358	}
359
360	// -------------------------------------------------------------------
361	// -----[ next state ]------------------------------------------------
362	// -------------------------------------------------------------------
363	for (uint32_t i=0; i<_param->_nb_context; i++)
364	{
365	// uint32_t x = _param->_link_context_to_decod_unit [i];
366
367	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
368	Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
369
370	context_state_t state = reg_STATE [i];
371
372	switch (state)
373	{
374	case CONTEXT_STATE_OK :
375	{
376	// nothing, wait an event
377	break;
378	}
379	case CONTEXT_STATE_KO_EXCEP :
380	{
381	// Wait end of all instruction
382	if (inst_all == 0)
383	state = CONTEXT_STATE_KO_EXCEP_ADDR;
384	break;
385	}
386	case CONTEXT_STATE_KO_MISS :
387	{
388	// Wait end of all instruction
389	if (inst_all == 0)
390	state = CONTEXT_STATE_KO_MISS_ADDR;
391	break;
392	}
393	case CONTEXT_STATE_KO_EXCEP_ADDR :
394	{
395	// nothing, wait the update of internal register (pc)
396	break;
397	}
398	case CONTEXT_STATE_KO_EXCEP_SPR :
399	{
400	// nothing, wait the update of internal register (epcr, eear, sr, esr)
401	break;
402	}
403	case CONTEXT_STATE_KO_MISS_ADDR :
404	{
405	// nothing, wait the update of internal register (pc)
406	break;
407	}
408	case CONTEXT_STATE_KO_PSYNC :
409	{
410	// Wait end of all instruction
411	if (inst_all == 0)
412	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
413	state = CONTEXT_STATE_KO_PSYNC_ADDR ;
414	break;
415	}
416	// case CONTEXT_STATE_KO_PSYNC_FLUSH :
417	// {
418	// // nothing, wait end of flush (ifetch)
419	// break;
420	// }
421	case CONTEXT_STATE_KO_PSYNC_ADDR :
422	{
423	// nothing, wait the pc write
424	break;
425	}
426	case CONTEXT_STATE_KO_CSYNC :
427	{
428	// Wait end of all instruction
429	if (inst_all == 0)
430	state = CONTEXT_STATE_KO_CSYNC_ADDR ;
431	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
432	break;
433	}
434	// case CONTEXT_STATE_KO_CSYNC_FLUSH :
435	// {
436	// // nothing, wait end of flush (all internal structure)
437	// break;
438	// }
439	case CONTEXT_STATE_KO_CSYNC_ADDR :
440	{
441	// nothing, wait the pc write
442	break;
443	}
444	case CONTEXT_STATE_KO_MSYNC :
445	{
446	// Wait end of memory instruction
447	if (inst_mem == 0)
448	state = CONTEXT_STATE_KO_MSYNC_ISSUE;
449	break;
450	}
451	case CONTEXT_STATE_KO_MSYNC_ISSUE :
452	{
453	// Wait the msync issue
454	if (inst_mem != 0)
455	state = CONTEXT_STATE_KO_MSYNC_EXEC;
456	break;
457	}
458	case CONTEXT_STATE_KO_MSYNC_EXEC :
459	{
460	// Wait the end of msync
461	if (inst_mem == 0)
462	state = CONTEXT_STATE_OK;
463	break;
464	}
465	case CONTEXT_STATE_KO_SPR :
466	{
467	// Wait end of all instruction
468	if (inst_all == 0)
469	state = CONTEXT_STATE_KO_SPR_ISSUE;
470	break;
471	}
472	case CONTEXT_STATE_KO_SPR_ISSUE :
473	{
474	// Wait the spr_access issue
475	if (inst_all != 0)
476	state = CONTEXT_STATE_KO_SPR_EXEC;
477	break;
478	}
479	case CONTEXT_STATE_KO_SPR_EXEC :
480	{
481	// Wait the spr_access execution
482	if (inst_all == 0)
483	state = CONTEXT_STATE_OK;
484	break;
485	}
486
487	default :
488	{
489	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
490	}
491	}
492	reg_STATE [i] = state;
493	}
494
495	for (uint32_t i=0; i<_param->_nb_context; ++i)
496	{
497	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
498
499	if (reg_INTERRUPT_ENABLE [i])
500	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
501	}
502	}
503
504	#if DEBUG >= DEBUG_TRACE
505	for (uint32_t i=0; i<_param->_nb_context; i++)
506	{
507	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
508	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
509	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
510	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
511	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
512	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
513	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
514	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
515	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
516	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
517	}
518	#endif
519
520	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
521	end_cycle ();
522	#endif
523
524	log_end(Context_State,FUNCTION);
525	};
526
527	}; // end namespace context_state
528	}; // end namespace front_end
529	}; // end namespace multi_front_end
530	}; // end namespace core
531
532	}; // end namespace behavioural
533	}; // end namespace morpheo
534	#endif

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