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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 95

Last change on this file since 95 was 95, checked in by rosiere, 16 years ago
1) Update Prediction Table - New architecture (systemC) done (and tested) -> need change interface in top level 2) Change documentation on VHDL generation 3) Change VHDL constant (case std_logic and std_logic_vector)
Property svn:keywords set to `Id`
File size: 24.4 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 95 2008-12-16 16:24:26Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::transition"
21	void Context_State::transition (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_context; i++)
29	{
30	reg_STATE [i] = CONTEXT_STATE_OK;
31	reg_INTERRUPT_ENABLE [i] = 0;
32	}
33	}
34	else
35	{
36	// -------------------------------------------------------------------
37	// -----[ BRANCH_EVENT ]----------------------------------------------
38	// -------------------------------------------------------------------
39	for (uint32_t i=0; i<_param->_nb_context; ++i)
40	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
41	{
42	// throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n"));
43
44	context_state_t state = reg_STATE [i];
45
46	Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):
47	0;
48	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
49	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
50	Tdepth_t depth_max = _param->_array_size_depth [i];
51
52	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
53	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
54	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
55	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
56
57	// priority : miss > excep > spr/sync
58	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
59	uint8_t priority1 = 2; // miss
60
61	// is_valid = can modify local information
62	// if context_state_ok : yes
63	// if context_state_ko : test the depth, and the priority of envent
64
65	bool is_valid = ((state == CONTEXT_STATE_OK) or
66	(depth1< depth0) or
67	((depth1==depth0) and (priority1>priority0)));
68
69	if (is_valid)
70	{
71	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
72	reg_STATE [i] = CONTEXT_STATE_KO_MISS;
73	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
74	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
75	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
76	//reg_EVENT_ADDRESS_EEAR [i] = 0;
77	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
78	reg_EVENT_IS_DELAY_SLOT [i] = dest_val;
79	reg_EVENT_IS_DS_TAKE [i] = dest_val;
80	reg_EVENT_DEPTH [i] = depth;
81	}
82	}
83
84	// -------------------------------------------------------------------
85	// -----[ DECOD_EVENT ]-----------------------------------------------
86	// -------------------------------------------------------------------
87
88	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
89	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
90	{
91	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
92	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
93	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
94	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
95	Tdepth_t depth_max = _param->_array_size_depth [context];
96
97	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
98	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
99	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
100	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
101
102	context_state_t state = reg_STATE [context];
103	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
104
105	// miss > excep > spr/sync
106	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
107	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
108
109	// is_valid = can modify local information
110	// if context_state_ok : yes
111	// if context_state_ko : test the depth, and the priority of envent
112
113	bool is_valid = ((state == CONTEXT_STATE_OK) or
114	(depth1< depth0) or
115	((depth1==depth0) and (priority1>priority0)));
116
117	if (is_valid)
118	{
119	// decod :
120	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
121	context_state_t state_next = state;
122	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
123	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
124
125	switch (type)
126	{
127	case EVENT_TYPE_EXCEPTION :
128	{
129	state_next = CONTEXT_STATE_KO_EXCEP;
130
131	break;
132	}
133	case EVENT_TYPE_SPR_ACCESS :
134	{
135	state_next = CONTEXT_STATE_KO_SPR ;
136	address++; // take next address
137	if (is_delay_slot)
138	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
139	break;
140	}
141	case EVENT_TYPE_MSYNC :
142	{
143	state_next = CONTEXT_STATE_KO_MSYNC;
144	address++; // take next address
145	if (is_delay_slot)
146	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
147	break;
148	}
149	case EVENT_TYPE_PSYNC :
150	{
151	state_next = CONTEXT_STATE_KO_PSYNC;
152	address++; // take next address
153	if (is_delay_slot)
154	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
155	break;
156	}
157	case EVENT_TYPE_CSYNC :
158	{
159	state_next = CONTEXT_STATE_KO_CSYNC;
160	address++; // take next address
161	if (is_delay_slot)
162	throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
163	break;
164	}
165	case EVENT_TYPE_NONE :
166	case EVENT_TYPE_MISS_SPECULATION :
167	case EVENT_TYPE_BRANCH_NO_ACCURATE :
168	default :
169	{
170	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
171	}
172	}
173
174	reg_STATE [context] = state_next;
175	reg_EVENT_ADDRESS [context] = address;
176	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
177	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
178	//reg_EVENT_ADDRESS_EEAR [context]
179	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
180	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
181	//reg_EVENT_IS_DS_TAKE [context] = 0;
182	reg_EVENT_DEPTH [context] = depth;
183	}
184	}
185
186	// -------------------------------------------------------------------
187	// -----[ COMMIT_EVENT ]----------------------------------------------
188	// -------------------------------------------------------------------
189
190	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
191	{
192	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
193	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
194	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
195	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
196	Tdepth_t depth_max = _param->_array_size_depth [context];
197
198	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
199	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
200	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
201	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
202
203	context_state_t state = reg_STATE [context];
204	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
205
206	// miss > excep > spr/sync
207	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
208	uint8_t priority1 = 1; // exception
209
210	// is_valid = can modify local information
211	// if context_state_ok : yes
212	// if context_state_ko : test the depth, and the priority of envent
213
214	bool is_valid = ((state == CONTEXT_STATE_OK) or
215	(depth1< depth0) or
216	((depth1==depth0) and (priority1>priority0)));
217
218	if (is_valid)
219	{
220	// commit
221	// type : exception
222	context_state_t state_next = state;
223	switch (type)
224	{
225	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
226	case EVENT_TYPE_SPR_ACCESS :
227	case EVENT_TYPE_MSYNC :
228	case EVENT_TYPE_PSYNC :
229	case EVENT_TYPE_CSYNC :
230	case EVENT_TYPE_NONE :
231	case EVENT_TYPE_MISS_SPECULATION :
232	case EVENT_TYPE_BRANCH_NO_ACCURATE :
233	default :
234	{
235	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
236	}
237	}
238	reg_STATE [context] = state_next;
239	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
240	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
241	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
242	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
243	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
244	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
245	//reg_EVENT_IS_DS_TAKE [context] = 0;
246	reg_EVENT_DEPTH [context] = depth;
247	}
248	}
249
250	// -------------------------------------------------------------------
251	// -----[ BRANCH_COMPLETE ]-------------------------------------------
252	// -------------------------------------------------------------------
253
254	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
255	if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i])
256	{
257	if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))
258	{
259	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
260	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
261	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
262	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
263	Tdepth_t depth_max = _param->_array_size_depth [context];
264
265	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
266	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
267	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
268	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
269
270	context_state_t state = reg_STATE [context];
271
272	// miss > excep > spr/sync
273	uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
274	uint8_t priority1 = 2; // miss
275
276	// is_valid = can modify local information
277	// if context_state_ok : yes
278	// if context_state_ko : test the depth, and the priority of envent
279
280	bool is_valid = ((state == CONTEXT_STATE_OK) or
281	(depth1< depth0) or
282	((depth1==depth0) and (priority1>priority0)));
283
284	if (is_valid)
285	{
286	// commit
287	Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);
288	reg_STATE [context] = CONTEXT_STATE_KO_MISS;
289	reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT
290	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);
291	reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence
292	//reg_EVENT_ADDRESS_EEAR [context];
293	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
294	reg_EVENT_IS_DELAY_SLOT [context] = take;
295	reg_EVENT_IS_DS_TAKE [context] = take;
296	reg_EVENT_DEPTH [context] = depth;
297	}
298	}
299	}
300
301	// -------------------------------------------------------------------
302	// -----[ EVENT ]-----------------------------------------------------
303	// -------------------------------------------------------------------
304	for (uint32_t i=0; i<_param->_nb_context; i++)
305	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
306	{
307	// Write pc
308	context_state_t state = reg_STATE [i];
309
310	switch (state)
311	{
312	case CONTEXT_STATE_KO_EXCEP_ADDR :
313	{
314	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
315	break;
316	}
317	case CONTEXT_STATE_KO_MISS_ADDR :
318	case CONTEXT_STATE_KO_PSYNC_ADDR :
319	case CONTEXT_STATE_KO_CSYNC_ADDR :
320	{
321	reg_STATE [i] = CONTEXT_STATE_OK;
322	break;
323	}
324	default :
325	{
326	#ifdef DEBUG_TEST
327	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
328	#endif
329	break;
330	}
331	}
332	}
333
334	// -------------------------------------------------------------------
335	// -----[ SPR_EVENT ]-------------------------------------------------
336	// -------------------------------------------------------------------
337	for (uint32_t i=0; i<_param->_nb_context; i++)
338	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
339	{
340	// Write spr
341	#ifdef DEBUG_TEST
342	context_state_t state = reg_STATE [i];
343
344	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
345	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
346	#endif
347
348	reg_STATE [i] = CONTEXT_STATE_OK;
349	}
350
351	// -------------------------------------------------------------------
352	// -----[ next state ]------------------------------------------------
353	// -------------------------------------------------------------------
354	for (uint32_t i=0; i<_param->_nb_context; i++)
355	{
356	// uint32_t x = _param->_link_context_to_decod_unit [i];
357
358	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
359	Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
360
361	context_state_t state = reg_STATE [i];
362
363	switch (state)
364	{
365	case CONTEXT_STATE_OK :
366	{
367	// nothing, wait an event
368	break;
369	}
370	case CONTEXT_STATE_KO_EXCEP :
371	{
372	// Wait end of all instruction
373	if (inst_all == 0)
374	state = CONTEXT_STATE_KO_EXCEP_ADDR;
375	break;
376	}
377	case CONTEXT_STATE_KO_MISS :
378	{
379	// Wait end of all instruction
380	if (inst_all == 0)
381	state = CONTEXT_STATE_KO_MISS_ADDR;
382	break;
383	}
384	case CONTEXT_STATE_KO_EXCEP_ADDR :
385	{
386	// nothing, wait the update of internal register (pc)
387	break;
388	}
389	case CONTEXT_STATE_KO_EXCEP_SPR :
390	{
391	// nothing, wait the update of internal register (epcr, eear, sr, esr)
392	break;
393	}
394	case CONTEXT_STATE_KO_MISS_ADDR :
395	{
396	// nothing, wait the update of internal register (pc)
397	break;
398	}
399	case CONTEXT_STATE_KO_PSYNC :
400	{
401	// Wait end of all instruction
402	if (inst_all == 0)
403	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
404	state = CONTEXT_STATE_KO_PSYNC_ADDR ;
405	break;
406	}
407	// case CONTEXT_STATE_KO_PSYNC_FLUSH :
408	// {
409	// // nothing, wait end of flush (ifetch)
410	// break;
411	// }
412	case CONTEXT_STATE_KO_PSYNC_ADDR :
413	{
414	// nothing, wait the pc write
415	break;
416	}
417	case CONTEXT_STATE_KO_CSYNC :
418	{
419	// Wait end of all instruction
420	if (inst_all == 0)
421	state = CONTEXT_STATE_KO_CSYNC_ADDR ;
422	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
423	break;
424	}
425	// case CONTEXT_STATE_KO_CSYNC_FLUSH :
426	// {
427	// // nothing, wait end of flush (all internal structure)
428	// break;
429	// }
430	case CONTEXT_STATE_KO_CSYNC_ADDR :
431	{
432	// nothing, wait the pc write
433	break;
434	}
435	case CONTEXT_STATE_KO_MSYNC :
436	{
437	// Wait end of memory instruction
438	if (inst_mem == 0)
439	state = CONTEXT_STATE_KO_MSYNC_ISSUE;
440	break;
441	}
442	case CONTEXT_STATE_KO_MSYNC_ISSUE :
443	{
444	// Wait the msync issue
445	if (inst_mem != 0)
446	state = CONTEXT_STATE_KO_MSYNC_EXEC;
447	break;
448	}
449	case CONTEXT_STATE_KO_MSYNC_EXEC :
450	{
451	// Wait the end of msync
452	if (inst_mem == 0)
453	state = CONTEXT_STATE_OK;
454	break;
455	}
456	case CONTEXT_STATE_KO_SPR :
457	{
458	// Wait end of all instruction
459	if (inst_all == 0)
460	state = CONTEXT_STATE_KO_SPR_ISSUE;
461	break;
462	}
463	case CONTEXT_STATE_KO_SPR_ISSUE :
464	{
465	// Wait the spr_access issue
466	if (inst_all != 0)
467	state = CONTEXT_STATE_KO_SPR_EXEC;
468	break;
469	}
470	case CONTEXT_STATE_KO_SPR_EXEC :
471	{
472	// Wait the spr_access execution
473	if (inst_all == 0)
474	state = CONTEXT_STATE_OK;
475	break;
476	}
477
478	default :
479	{
480	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
481	}
482	}
483	reg_STATE [i] = state;
484	}
485
486	for (uint32_t i=0; i<_param->_nb_context; ++i)
487	{
488	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
489
490	if (reg_INTERRUPT_ENABLE [i])
491	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
492	}
493	}
494
495	#if DEBUG >= DEBUG_TRACE
496	for (uint32_t i=0; i<_param->_nb_context; i++)
497	{
498	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
499	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
500	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
501	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
502	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
503	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
504	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
505	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
506	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
507	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
508	}
509	#endif
510
511	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
512	end_cycle ();
513	#endif
514
515	log_end(Context_State,FUNCTION);
516	};
517
518	}; // end namespace context_state
519	}; // end namespace front_end
520	}; // end namespace multi_front_end
521	}; // end namespace core
522
523	}; // end namespace behavioural
524	}; // end namespace morpheo
525	#endif

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