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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
Property svn:keywords set to `Id`
File size: 137.4 KB

Rev	Line
[78]	1	/*
	2	* $Id: Instruction.cpp 117 2009-05-16 14:42:39Z rosiere $
	3	*
	4	* [ Description ]
	5	*
	6	* instruction MAC_UNIT (l.mac, l.maci, l.macrc, l.msb) throw a context event. Also is sequential.
	7	* If your program need intensive mac_unit, you can change the implementation of this unit :
	8	* 1) "decod" : inst->_event_type = EVENT_TYPE_NONE;
	9	* 2) "rename" : add component as load_store_unit pointer management
	10	* 3) "functionnal_unit" : test type instruction, if type=MAC_UNIT, insert in queue, the localisation is the ptr give by rename stage. Retire in this queue in sequence (as the store queue).
	11	*
	12	*/
	13
	14	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h"
[86]	15	#include "Behavioural/include/Constants.h"
[88]	16	#include "Behavioural/include/Operation.h"
[78]	17
	18	namespace morpheo {
	19	namespace behavioural {
	20	namespace core {
	21	namespace multi_front_end {
	22	namespace front_end {
	23	namespace decod_unit {
	24	namespace decod {
	25
[117]	26	#define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>(param->_size_data, x,true ,nb_bits)
	27	#define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>(param->_size_data, x,false,nb_bits)
[78]	28
	29	void instruction_decod (decod_instruction_t * inst, decod_param_t * param)
	30	{
[101]	31	log_printf(TRACE,Decod,"instruction_decod"," * instruction : decod");
	32
[78]	33	// instruction_decod_type_0 (inst,param);
	34
	35	uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
[101]	36
	37	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	38
[78]	39	(* param->_function_decod[ 0][opcod]) (inst,param);
	40	}
	41
	42	// void instruction_decod_type_0 (decod_instruction_t * inst, decod_param_t * param)
	43	// {
	44	// uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
	45	// (* param->_function_decod[ 0][opcod]) (inst,param);
	46	// }
	47
	48	void instruction_decod_type_1 (decod_instruction_t * inst, decod_param_t * param)
	49	{
[101]	50	log_printf(TRACE,Decod,"instruction_decod_type_1"," * instruction : decod type_1");
	51
[78]	52	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
[101]	53
	54	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	55
[78]	56	(* param->_function_decod[ 1][opcod]) (inst,param);
	57	}
	58
	59	void instruction_decod_type_2 (decod_instruction_t * inst, decod_param_t * param)
	60	{
[101]	61	log_printf(TRACE,Decod,"instruction_decod_type_2"," * instruction : decod type_2");
	62
[78]	63	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
[101]	64
	65	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	66
[78]	67	(* param->_function_decod[ 2][opcod]) (inst,param);
	68	}
	69
	70	void instruction_decod_type_3 (decod_instruction_t * inst, decod_param_t * param)
	71	{
[101]	72	log_printf(TRACE,Decod,"instruction_decod_type_3"," * instruction : decod type_3");
	73
[78]	74	uint32_t opcod = ((range<uint32_t>(inst->_instruction, 9, 8)<<4) \|
	75	(range<uint32_t>(inst->_instruction, 3, 0)));
[101]	76
	77	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	78
[78]	79	(* param->_function_decod[ 3][opcod]) (inst,param);
	80	}
	81
	82	void instruction_decod_type_4 (decod_instruction_t * inst, decod_param_t * param)
	83	{
[101]	84	log_printf(TRACE,Decod,"instruction_decod_type_4"," * instruction : decod type_4");
	85
[78]	86	uint32_t opcod = range<uint32_t>(inst->_instruction,25,21);
[101]	87
	88	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	89
[78]	90	(* param->_function_decod[ 4][opcod]) (inst,param);
	91	}
	92
	93	void instruction_decod_type_5 (decod_instruction_t * inst, decod_param_t * param)
	94	{
[101]	95	log_printf(TRACE,Decod,"instruction_decod_type_5"," * instruction : decod type_5");
	96
[78]	97	uint32_t opcod = range<uint32_t>(inst->_instruction,25,21);
[101]	98
	99	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	100
[78]	101	(* param->_function_decod[ 5][opcod]) (inst,param);
	102	}
	103
	104	void instruction_decod_type_6 (decod_instruction_t * inst, decod_param_t * param)
	105	{
[101]	106	log_printf(TRACE,Decod,"instruction_decod_type_6"," * instruction : decod type_6");
	107
[78]	108	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
[101]	109
	110	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	111
[78]	112	(* param->_function_decod[ 6][opcod]) (inst,param);
	113	}
	114
	115	void instruction_decod_type_7 (decod_instruction_t * inst, decod_param_t * param)
	116	{
[101]	117	log_printf(TRACE,Decod,"instruction_decod_type_7"," * instruction : decod type_7");
	118
[78]	119	uint32_t opcod = range<uint32_t>(inst->_instruction, 3, 0);
[101]	120
	121	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	122
[78]	123	(* param->_function_decod[ 7][opcod]) (inst,param);
	124	}
	125
	126	void instruction_decod_type_8 (decod_instruction_t * inst, decod_param_t * param)
	127	{
[101]	128	log_printf(TRACE,Decod,"instruction_decod_type_8"," * instruction : decod type_8");
	129
[78]	130	uint32_t opcod = range<uint32_t>(inst->_instruction,16,16);
[101]	131
	132	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	133
[78]	134	(* param->_function_decod[ 8][opcod]) (inst,param);
	135	}
	136
	137	void instruction_decod_type_9 (decod_instruction_t * inst, decod_param_t * param)
	138	{
[101]	139	log_printf(TRACE,Decod,"instruction_decod_type_9"," * instruction : decod type_9");
	140
[78]	141	uint32_t opcod = range<uint32_t>(inst->_instruction,25,23);
[101]	142
	143	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	144
[78]	145	(* param->_function_decod[ 9][opcod]) (inst,param);
	146	}
	147
	148	void instruction_decod_type_10 (decod_instruction_t * inst, decod_param_t * param)
	149	{
[101]	150	log_printf(TRACE,Decod,"instruction_decod_type_10"," * instruction : decod type_10");
	151
[78]	152	uint32_t opcod = range<uint32_t>(inst->_instruction,25,24);
[101]	153
	154	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	155
[78]	156	(* param->_function_decod[10][opcod]) (inst,param);
	157	}
	158
	159	void instruction_decod_type_11 (decod_instruction_t * inst, decod_param_t * param)
	160	{
[101]	161	log_printf(TRACE,Decod,"instruction_decod_type_11"," * instruction : decod type_11");
	162
[78]	163	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
[101]	164
	165	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	166
[78]	167	(* param->_function_decod[11][opcod]) (inst,param);
	168	}
	169
	170	void instruction_decod_type_12 (decod_instruction_t * inst, decod_param_t * param)
	171	{
[101]	172	log_printf(TRACE,Decod,"instruction_decod_type_12"," * instruction : decod type_12");
	173
[78]	174	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
[101]	175
	176	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	177
[78]	178	(* param->_function_decod[12][opcod]) (inst,param);
	179	}
	180
	181	void instruction_decod_type_13 (decod_instruction_t * inst, decod_param_t * param)
	182	{
[101]	183	log_printf(TRACE,Decod,"instruction_decod_type_13"," * instruction : decod type_13");
	184
[78]	185	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
[101]	186
	187	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
	188
[78]	189	(* param->_function_decod[13][opcod]) (inst,param);
	190	}
	191
	192	void instruction_illegal (decod_instruction_t * inst, decod_param_t * param)
	193	{
[101]	194	log_printf(TRACE,Decod,"instruction_illegal"," * instruction : illegal");
	195
	196	msgWarning(_("Instruction \"%.8x\" at address \"%.8x\" is illegal.\n"),inst->_instruction,inst->_address);
[78]	197
	198	inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION;
[88]	199	inst->_exception = EXCEPTION_ILLEGAL_INSTRUCTION;
[78]	200
	201	if (inst->_is_delay_slot)
	202	inst->_address_next = inst->_address_previous;
	203	else
	204	inst->_address_next = inst->_address;
	205
	206	inst->_event_type = EVENT_TYPE_EXCEPTION;
	207	}
[86]	208
	209	void instruction_l_custom (decod_instruction_t * inst, decod_param_t * param)
	210	{
	211	log_printf(TRACE,Decod,"instruction_l_custom"," * instruction : custom");
	212
	213	uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
[88]	214
[86]	215	switch (opcod)
	216	{
[88]	217	case OPCOD_L_CUST1 : {inst->_type = instruction_information(INSTRUCTION_L_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST1)._operation; break;}
	218	case OPCOD_L_CUST2 : {inst->_type = instruction_information(INSTRUCTION_L_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST2)._operation; break;}
	219	case OPCOD_L_CUST3 : {inst->_type = instruction_information(INSTRUCTION_L_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST3)._operation; break;}
	220	case OPCOD_L_CUST4 : {inst->_type = instruction_information(INSTRUCTION_L_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST4)._operation; break;}
	221	case OPCOD_L_CUST5 : {inst->_type = instruction_information(INSTRUCTION_L_CUST5)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST5)._operation; break;}
	222	case OPCOD_L_CUST6 : {inst->_type = instruction_information(INSTRUCTION_L_CUST6)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST6)._operation; break;}
	223	case OPCOD_L_CUST7 : {inst->_type = instruction_information(INSTRUCTION_L_CUST7)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST7)._operation; break;}
	224	case OPCOD_L_CUST8 : {inst->_type = instruction_information(INSTRUCTION_L_CUST8)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST8)._operation; break;}
	225
[86]	226	default : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));}
	227	}
	228
	229	(* param->_function_custom[ 0][opcod]) (inst,param);
	230
	231	instruction_custom(inst,param);
	232	}
	233
	234	void instruction_lf_custom (decod_instruction_t * inst, decod_param_t * param)
	235	{
	236	log_printf(TRACE,Decod,"instruction_lf_custom"," * instruction : custom");
	237
	238	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
	239
	240	switch (opcod)
	241	{
[88]	242	// case OPCOD_LF_CUST1_D : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_D)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_D)._operation; break;}
	243	// case OPCOD_LF_CUST1_S : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_S)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_S)._operation; break;}
[86]	244	default : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));}
	245	}
	246
	247	(* param->_function_custom[ 1][opcod]) (inst,param);
	248
	249	instruction_custom(inst,param);
	250	}
	251
	252	void instruction_lv_custom (decod_instruction_t * inst, decod_param_t * param)
	253	{
	254	log_printf(TRACE,Decod,"instruction_lv_custom"," * instruction : custom");
	255
	256	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
	257
	258	switch (opcod)
	259	{
[88]	260	// case OPCOD_LV_CUST1 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST1)._operation; break;}
	261	// case OPCOD_LV_CUST2 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST2)._operation; break;}
	262	// case OPCOD_LV_CUST3 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST3)._operation; break;}
	263	// case OPCOD_LV_CUST4 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST4)._operation; break;}
[86]	264	default : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));}
	265	}
	266
	267	(* param->_function_custom[ 2][opcod]) (inst,param);
	268
	269	instruction_custom(inst,param);
	270	}
	271
	272	void instruction_custom (decod_instruction_t * inst, decod_param_t * param)
	273	{
	274	// Test custom operation
	275
	276	std::string msg = "";
	277
	278	if (inst->_exception_use != EXCEPTION_USE_ILLEGAL_INSTRUCTION)
	279	{
	280	if (inst->_type != TYPE_CUSTOM)
	281	msg += _("Invalid Type.\n");
	282
	283	if ((inst->_operation != OPERATION_CUSTOM_L_1 ) and
	284	(inst->_operation != OPERATION_CUSTOM_L_2 ) and
	285	(inst->_operation != OPERATION_CUSTOM_L_3 ) and
	286	(inst->_operation != OPERATION_CUSTOM_L_4 ) and
	287	(inst->_operation != OPERATION_CUSTOM_L_5 ) and
	288	(inst->_operation != OPERATION_CUSTOM_L_6 ) and
	289	(inst->_operation != OPERATION_CUSTOM_L_7 ) and
	290	(inst->_operation != OPERATION_CUSTOM_L_8 ) and
	291	(inst->_operation != OPERATION_CUSTOM_LF_1_D) and
	292	(inst->_operation != OPERATION_CUSTOM_LF_1_S) and
	293	(inst->_operation != OPERATION_CUSTOM_LV_1 ) and
	294	(inst->_operation != OPERATION_CUSTOM_LV_2 ) and
	295	(inst->_operation != OPERATION_CUSTOM_LV_3 ) and
	296	(inst->_operation != OPERATION_CUSTOM_LV_4 ))
	297	msg += _("Invalid Operation.\n");
	298
	299	if ((inst->_exception_use != EXCEPTION_USE_NONE ) and
	300	(inst->_exception_use != EXCEPTION_USE_RANGE ) and
	301	(inst->_exception_use != EXCEPTION_USE_CUSTOM_0 ) and
	302	(inst->_exception_use != EXCEPTION_USE_CUSTOM_1 ) and
	303	(inst->_exception_use != EXCEPTION_USE_CUSTOM_2 ) and
	304	(inst->_exception_use != EXCEPTION_USE_CUSTOM_3 ) and
	305	(inst->_exception_use != EXCEPTION_USE_CUSTOM_4 ) and
	306	(inst->_exception_use != EXCEPTION_USE_CUSTOM_5 ) and
	307	(inst->_exception_use != EXCEPTION_USE_CUSTOM_6 ))
	308	msg += _("Invalid Exception.\n");
	309
	310	if ((inst->_event_type != EVENT_TYPE_NONE ) and
	311	(inst->_event_type != EVENT_TYPE_SPR_ACCESS))
	312	msg += _("Invalid Event_type.\n");
	313
	314	if (inst->_address_next != (inst->_address+1))
	315	msg += _("Address must be in sequence.\n");
	316
	317	if (msg != "")
	318	throw ERRORMORPHEO("instruction_custom","Invalid decod : "+msg);
	319	}
	320	}
[78]	321
	322	// ORBIS
	323	void instruction_l_add (decod_instruction_t * inst, decod_param_t * param)
	324	{
	325	log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add");
[88]	326	inst->_type = instruction_information(INSTRUCTION_L_ADD)._type ; //TYPE_ALU;
	327	inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD;
[78]	328	inst->_has_immediat = 0;
[97]	329	inst->_immediat = 0; // unnecessary
[78]	330	inst->_read_ra = 1;
	331	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	332	inst->_read_rb = 1;
	333	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	334	inst->_read_rc = 0;
[97]	335	inst->_num_reg_rc = 0; //unnecessary
[78]	336	inst->_write_rd = 1;
	337	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	338	inst->_write_re = 1;
	339	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	340	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	341	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	342	// inst->_branch_condition = ;
	343	// inst->_branch_stack_write = ;
	344	// inst->_branch_direction = ;
[97]	345	// inst->_address_next = ; // already define : PC+4
[88]	346	inst->_no_execute = 0;
[78]	347	inst->_event_type = EVENT_TYPE_NONE;
	348	}
	349
	350	void instruction_l_addc (decod_instruction_t * inst, decod_param_t * param)
	351	{
	352	log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc");
	353
[88]	354	inst->_type = instruction_information(INSTRUCTION_L_ADDC)._type ; //TYPE_ALU;
	355	inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD;
[78]	356	inst->_has_immediat = 0;
[97]	357	inst->_immediat = 0; // unnecessary
[78]	358	inst->_read_ra = 1;
	359	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	360	inst->_read_rb = 1;
	361	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	362	inst->_read_rc = 1;
	363	inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV;
	364	inst->_write_rd = 1;
	365	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	366	inst->_write_re = 1;
	367	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	368	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	369	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	370	// inst->_branch_condition = ;
	371	// inst->_branch_stack_write = ;
	372	// inst->_branch_direction = ;
[97]	373	// inst->_address_next = ; // already define : PC+4
[88]	374	inst->_no_execute = 0;
[78]	375	inst->_event_type = EVENT_TYPE_NONE;
	376	}
	377
	378	void instruction_l_addi (decod_instruction_t * inst, decod_param_t * param)
	379	{
	380	log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi");
	381
[88]	382	inst->_type = instruction_information(INSTRUCTION_L_ADDI)._type ; //TYPE_ALU;
	383	inst->_operation = instruction_information(INSTRUCTION_L_ADDI)._operation; //OPERATION_ALU_L_ADD;
[78]	384	inst->_has_immediat = 1;
	385	inst->_immediat = EXTENDS(inst->_instruction,16);
	386	inst->_read_ra = 1;
	387	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	388	inst->_read_rb = 0;
[97]	389	inst->_num_reg_rb = 0; //unnecessary
[78]	390	inst->_read_rc = 0;
[97]	391	inst->_num_reg_rc = 0; //unnecessary
[78]	392	inst->_write_rd = 1;
	393	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	394	inst->_write_re = 1;
	395	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	396	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	397	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	398	// inst->_branch_condition = ;
	399	// inst->_branch_stack_write = ;
	400	// inst->_branch_direction = ;
[97]	401	// inst->_address_next = ; // already define : PC+4
[88]	402	inst->_no_execute = 0;
[78]	403	inst->_event_type = EVENT_TYPE_NONE;
	404	}
	405
	406	void instruction_l_addic (decod_instruction_t * inst, decod_param_t * param)
	407	{
	408	log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic");
	409
[88]	410	inst->_type = instruction_information(INSTRUCTION_L_ADDIC)._type ; //TYPE_ALU;
	411	inst->_operation = instruction_information(INSTRUCTION_L_ADDIC)._operation; //OPERATION_ALU_L_ADD;
[78]	412	inst->_has_immediat = 1;
	413	inst->_immediat = EXTENDS(inst->_instruction,16);
	414	inst->_read_ra = 1;
	415	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	416	inst->_read_rb = 0;
[97]	417	inst->_num_reg_rb = 0; //unnecessary
[78]	418	inst->_read_rc = 1;
	419	inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV;
	420	inst->_write_rd = 1;
	421	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	422	inst->_write_re = 1;
	423	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	424	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	425	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	426	// inst->_branch_condition = ;
	427	// inst->_branch_stack_write = ;
	428	// inst->_branch_direction = ;
[97]	429	// inst->_address_next = ; // already define : PC+4
[88]	430	inst->_no_execute = 0;
[78]	431	inst->_event_type = EVENT_TYPE_NONE;
	432	}
	433
	434	void instruction_l_and (decod_instruction_t * inst, decod_param_t * param)
	435	{
	436	log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and");
	437
[88]	438	inst->_type = instruction_information(INSTRUCTION_L_AND)._type ; //TYPE_ALU;
	439	inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND;
[78]	440	inst->_has_immediat = 0;
[97]	441	inst->_immediat = 0; // unnecessary
[78]	442	inst->_read_ra = 1;
	443	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	444	inst->_read_rb = 1;
	445	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	446	inst->_read_rc = 0;
[97]	447	inst->_num_reg_rc = 0; //unnecessary
[78]	448	inst->_write_rd = 1;
	449	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	450	inst->_write_re = 0;
[97]	451	inst->_num_reg_re = 0; //unnecessary
[78]	452	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	453	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	454	// inst->_branch_condition = ;
	455	// inst->_branch_stack_write = ;
	456	// inst->_branch_direction = ;
[97]	457	// inst->_address_next = ; // already define : PC+4
[88]	458	inst->_no_execute = 0;
[78]	459	inst->_event_type = EVENT_TYPE_NONE;
	460	}
	461
	462	void instruction_l_andi (decod_instruction_t * inst, decod_param_t * param)
	463	{
	464	log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi");
	465
[88]	466	inst->_type = instruction_information(INSTRUCTION_L_ANDI)._type ; //TYPE_ALU;
	467	inst->_operation = instruction_information(INSTRUCTION_L_ANDI)._operation; //OPERATION_ALU_L_AND;
[78]	468	inst->_has_immediat = 1;
	469	inst->_immediat = EXTENDZ(inst->_instruction,16);
	470	inst->_read_ra = 1;
	471	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	472	inst->_read_rb = 0;
[97]	473	inst->_num_reg_rb = 0; //unnecessary
[78]	474	inst->_read_rc = 0;
[97]	475	inst->_num_reg_rc = 0; //unnecessary
[78]	476	inst->_write_rd = 1;
	477	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	478	inst->_write_re = 0;
[97]	479	inst->_num_reg_re = 0; //unnecessary
[78]	480	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	481	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	482	// inst->_branch_condition = ;
	483	// inst->_branch_stack_write = ;
	484	// inst->_branch_direction = ;
[97]	485	// inst->_address_next = ; // already define : PC+4
[88]	486	inst->_no_execute = 0;
[78]	487	inst->_event_type = EVENT_TYPE_NONE;
	488	}
	489
	490	void instruction_l_bf (decod_instruction_t * inst, decod_param_t * param)
	491	{
	492	log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf");
	493
[88]	494	Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
	495	);
[78]	496
[88]	497	inst->_type = instruction_information(INSTRUCTION_L_BF)._type ; //TYPE_BRANCH;
	498	inst->_operation = instruction_information(INSTRUCTION_L_BF)._operation; //OPERATION_BRANCH_L_TEST_F;
[78]	499	inst->_has_immediat = 1;
	500	inst->_immediat = address_next;
	501	inst->_read_ra = 0;
[97]	502	inst->_num_reg_ra = 0; //unnecessary
[78]	503	inst->_read_rb = 0;
[97]	504	inst->_num_reg_rb = 0; //unnecessary
[78]	505	inst->_read_rc = 1;
	506	inst->_num_reg_rc = SPR_LOGIC_SR_F;
	507	inst->_write_rd = 0;
[97]	508	inst->_num_reg_rd = 0; //unnecessary
[78]	509	inst->_write_re = 0;
[97]	510	inst->_num_reg_re = 0; //unnecessary
[78]	511	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	512	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	513	inst->_branch_condition = BRANCH_CONDITION_FLAG_SET;
	514	// inst->_branch_stack_write = 0;
	515
	516	inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25);
	517	inst->_address_next = address_next;
[88]	518	inst->_no_execute = 0;
[78]	519	inst->_event_type = EVENT_TYPE_NONE;
	520	}
	521
	522	void instruction_l_bnf (decod_instruction_t * inst, decod_param_t * param)
	523	{
	524	log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf");
	525
[88]	526	Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
	527	);
[78]	528
[88]	529	inst->_type = instruction_information(INSTRUCTION_L_BNF)._type ; //TYPE_BRANCH;
	530	inst->_operation = instruction_information(INSTRUCTION_L_BNF)._operation; //OPERATION_BRANCH_L_TEST_NF;
[78]	531	inst->_has_immediat = 1;
	532	inst->_immediat = address_next;
	533	inst->_read_ra = 0;
[97]	534	inst->_num_reg_ra = 0; //unnecessary
[78]	535	inst->_read_rb = 0;
[97]	536	inst->_num_reg_rb = 0; //unnecessary
[78]	537	inst->_read_rc = 1;
	538	inst->_num_reg_rc = SPR_LOGIC_SR_F;
	539	inst->_write_rd = 0;
	540	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	541	inst->_write_re = 0;
[97]	542	inst->_num_reg_re = 0; //unnecessary
[78]	543	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	544	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	545	inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET;
	546	// inst->_branch_stack_write = 0;
	547	inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25);
	548	inst->_address_next = address_next;
[88]	549	inst->_no_execute = 0;
[78]	550	inst->_event_type = EVENT_TYPE_NONE;
	551	}
	552
	553	void instruction_l_cmov (decod_instruction_t * inst, decod_param_t * param)
	554	{
	555	log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov");
	556
[88]	557	inst->_type = instruction_information(INSTRUCTION_L_CMOV)._type ; //TYPE_MOVE;
	558	inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV;
[78]	559	inst->_has_immediat = 0;
[97]	560	inst->_immediat = 0; // unnecessary
[78]	561	inst->_read_ra = 1;
	562	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	563	inst->_read_rb = 1;
	564	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	565	inst->_read_rc = 1;
	566	inst->_num_reg_rc = SPR_LOGIC_SR_F;
	567	inst->_write_rd = 1;
	568	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	569	inst->_write_re = 0;
[97]	570	inst->_num_reg_re = 0; //unnecessary
[78]	571	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	572	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	573	// inst->_branch_condition = ;
	574	// inst->_branch_stack_write = ;
	575	// inst->_branch_direction = ;
[97]	576	// inst->_address_next = ; // already define : PC+4
[88]	577	inst->_no_execute = 0;
[78]	578	inst->_event_type = EVENT_TYPE_NONE;
	579	}
	580
	581	void instruction_l_csync (decod_instruction_t * inst, decod_param_t * param)
	582	{
	583	log_printf(TRACE,Decod,"instruction_l_csync"," * instruction : l.csync");
	584
	585	if (range<Tinstruction_t>(inst->_instruction,23) != 0)
	586	{
	587	instruction_illegal (inst, param);
	588	}
	589	else
	590	{
[88]	591	inst->_type = instruction_information(INSTRUCTION_L_CSYNC)._type ; //TYPE_SPECIAL;
	592	inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC;
[78]	593	inst->_has_immediat = 0;
[97]	594	inst->_immediat = 0; // unnecessary
[78]	595	inst->_read_ra = 0;
[97]	596	inst->_num_reg_ra = 0; //unnecessary
[78]	597	inst->_read_rb = 0;
[97]	598	inst->_num_reg_rb = 0; //unnecessary
[78]	599	inst->_read_rc = 0;
[97]	600	inst->_num_reg_rc = 0; //unnecessary
[78]	601	inst->_write_rd = 0;
[97]	602	inst->_num_reg_rd = 0; //unnecessary
[78]	603	inst->_write_re = 0;
[97]	604	inst->_num_reg_re = 0; //unnecessary
[78]	605	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	606	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	607	// inst->_branch_condition = ;
	608	// inst->_branch_stack_write = ;
	609	// inst->_branch_direction = ;
[97]	610	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	611	inst->_no_execute = 0;
[78]	612	inst->_event_type = EVENT_TYPE_CSYNC;
	613	}
	614	}
	615
	616	// void instruction_l_cust1 (decod_instruction_t * inst, decod_param_t * param)
	617	// void instruction_l_cust2 (decod_instruction_t * inst, decod_param_t * param)
	618	// void instruction_l_cust3 (decod_instruction_t * inst, decod_param_t * param)
	619	// void instruction_l_cust4 (decod_instruction_t * inst, decod_param_t * param)
	620	// void instruction_l_cust5 (decod_instruction_t * inst, decod_param_t * param)
	621	// void instruction_l_cust6 (decod_instruction_t * inst, decod_param_t * param)
	622	// void instruction_l_cust7 (decod_instruction_t * inst, decod_param_t * param)
	623	// void instruction_l_cust8 (decod_instruction_t * inst, decod_param_t * param)
	624
	625	void instruction_l_div (decod_instruction_t * inst, decod_param_t * param)
	626	{
	627	log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div");
	628
[88]	629	inst->_type = instruction_information(INSTRUCTION_L_DIV)._type ; //TYPE_DIV;
	630	inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV;
[78]	631	inst->_has_immediat = 0;
[97]	632	inst->_immediat = 0; // unnecessary
[78]	633	inst->_read_ra = 1;
	634	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	635	inst->_read_rb = 1;
	636	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	637	inst->_read_rc = 0;
[97]	638	inst->_num_reg_rc = 0; //unnecessary
[78]	639	inst->_write_rd = 1;
	640	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	641	inst->_write_re = 1;
	642	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	643	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	644	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	645	// inst->_branch_condition = ;
	646	// inst->_branch_stack_write = ;
	647	// inst->_branch_direction = ;
[97]	648	// inst->_address_next = ; // already define : PC+4
[88]	649	inst->_no_execute = 0;
[78]	650	inst->_event_type = EVENT_TYPE_NONE;
	651	}
	652
	653	void instruction_l_divu (decod_instruction_t * inst, decod_param_t * param)
	654	{
	655	log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu");
	656
[88]	657	inst->_type = instruction_information(INSTRUCTION_L_DIVU)._type ; //TYPE_DIV;
	658	inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU;
[78]	659	inst->_has_immediat = 0;
[97]	660	inst->_immediat = 0; // unnecessary
[78]	661	inst->_read_ra = 1;
	662	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	663	inst->_read_rb = 1;
	664	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	665	inst->_read_rc = 0;
[97]	666	inst->_num_reg_rc = 0; //unnecessary
[78]	667	inst->_write_rd = 1;
	668	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	669	inst->_write_re = 1;
	670	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	671	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	672	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	673	// inst->_branch_condition = ;
	674	// inst->_branch_stack_write = ;
	675	// inst->_branch_direction = ;
[97]	676	// inst->_address_next = ; // already define : PC+4
[88]	677	inst->_no_execute = 0;
[78]	678	inst->_event_type = EVENT_TYPE_NONE;
	679	}
	680
	681	void instruction_l_extbs (decod_instruction_t * inst, decod_param_t * param)
	682	{
	683	log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs");
	684
[88]	685	inst->_type = instruction_information(INSTRUCTION_L_EXTBS)._type ; //TYPE_EXTEND;
	686	inst->_operation = instruction_information(INSTRUCTION_L_EXTBS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
[78]	687	inst->_has_immediat = 1;
	688	inst->_immediat = 8;
	689	inst->_read_ra = 1;
	690	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	691	inst->_read_rb = 0;
[97]	692	inst->_num_reg_rb = 0; //unnecessary
[78]	693	inst->_read_rc = 0;
[97]	694	inst->_num_reg_rc = 0; //unnecessary
[78]	695	inst->_write_rd = 1;
	696	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	697	inst->_write_re = 0;
[97]	698	inst->_num_reg_re = 0; //unnecessary
[78]	699	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	700	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	701	// inst->_branch_condition = ;
	702	// inst->_branch_stack_write = ;
	703	// inst->_branch_direction = ;
[97]	704	// inst->_address_next = ; // already define : PC+4
[88]	705	inst->_no_execute = 0;
[78]	706	inst->_event_type = EVENT_TYPE_NONE;
	707	}
	708
	709	void instruction_l_extbz (decod_instruction_t * inst, decod_param_t * param)
	710	{
	711	log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz");
	712
[88]	713	inst->_type = instruction_information(INSTRUCTION_L_EXTBZ)._type ; //TYPE_EXTEND;
	714	inst->_operation = instruction_information(INSTRUCTION_L_EXTBZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
[78]	715	inst->_has_immediat = 1;
	716	inst->_immediat = 8;
	717	inst->_read_ra = 1;
	718	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	719	inst->_read_rb = 0;
[97]	720	inst->_num_reg_rb = 0; //unnecessary
[78]	721	inst->_read_rc = 0;
[97]	722	inst->_num_reg_rc = 0; //unnecessary
[78]	723	inst->_write_rd = 1;
	724	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	725	inst->_write_re = 0;
[97]	726	inst->_num_reg_re = 0; //unnecessary
[78]	727	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	728	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	729	// inst->_branch_condition = ;
	730	// inst->_branch_stack_write = ;
	731	// inst->_branch_direction = ;
[97]	732	// inst->_address_next = ; // already define : PC+4
[88]	733	inst->_no_execute = 0;
[78]	734	inst->_event_type = EVENT_TYPE_NONE;
	735	}
	736
	737	void instruction_l_exths (decod_instruction_t * inst, decod_param_t * param)
	738	{
	739	log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths");
	740
[88]	741	inst->_type = instruction_information(INSTRUCTION_L_EXTHS)._type ; //TYPE_EXTEND;
	742	inst->_operation = instruction_information(INSTRUCTION_L_EXTHS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
[78]	743	inst->_has_immediat = 1;
	744	inst->_immediat = 16;
	745	inst->_read_ra = 1;
	746	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	747	inst->_read_rb = 0;
[97]	748	inst->_num_reg_rb = 0; //unnecessary
[78]	749	inst->_read_rc = 0;
[97]	750	inst->_num_reg_rc = 0; //unnecessary
[78]	751	inst->_write_rd = 1;
	752	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	753	inst->_write_re = 0;
[97]	754	inst->_num_reg_re = 0; //unnecessary
[78]	755	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	756	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	757	// inst->_branch_condition = ;
	758	// inst->_branch_stack_write = ;
	759	// inst->_branch_direction = ;
[97]	760	// inst->_address_next = ; // already define : PC+4
[88]	761	inst->_no_execute = 0;
[78]	762	inst->_event_type = EVENT_TYPE_NONE;
	763	}
	764
	765	void instruction_l_exthz (decod_instruction_t * inst, decod_param_t * param)
	766	{
	767	log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz");
	768
[88]	769	inst->_type = instruction_information(INSTRUCTION_L_EXTHZ)._type ; //TYPE_EXTEND;
	770	inst->_operation = instruction_information(INSTRUCTION_L_EXTHZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
[78]	771	inst->_has_immediat = 1;
	772	inst->_immediat = 16;
	773	inst->_read_ra = 1;
	774	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	775	inst->_read_rb = 0;
[97]	776	inst->_num_reg_rb = 0; //unnecessary
[78]	777	inst->_read_rc = 0;
[97]	778	inst->_num_reg_rc = 0; //unnecessary
[78]	779	inst->_write_rd = 1;
	780	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	781	inst->_write_re = 0;
[97]	782	inst->_num_reg_re = 0; //unnecessary
[78]	783	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	784	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	785	// inst->_branch_condition = ;
	786	// inst->_branch_stack_write = ;
	787	// inst->_branch_direction = ;
[97]	788	// inst->_address_next = ; // already define : PC+4
[88]	789	inst->_no_execute = 0;
[78]	790	inst->_event_type = EVENT_TYPE_NONE;
	791	}
	792
	793	void instruction_l_extws (decod_instruction_t * inst, decod_param_t * param)
	794	{
	795	log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws");
	796
[88]	797	inst->_type = instruction_information(INSTRUCTION_L_EXTWS)._type ; //TYPE_EXTEND;
	798	inst->_operation = instruction_information(INSTRUCTION_L_EXTWS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
[78]	799	inst->_has_immediat = 1;
	800	inst->_immediat = 32;
	801	inst->_read_ra = 1;
	802	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	803	inst->_read_rb = 0;
[97]	804	inst->_num_reg_rb = 0; //unnecessary
[78]	805	inst->_read_rc = 0;
[97]	806	inst->_num_reg_rc = 0; //unnecessary
[78]	807	inst->_write_rd = 1;
	808	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	809	inst->_write_re = 0;
[97]	810	inst->_num_reg_re = 0; //unnecessary
[78]	811	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	812	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	813	// inst->_branch_condition = ;
	814	// inst->_branch_stack_write = ;
	815	// inst->_branch_direction = ;
[97]	816	// inst->_address_next = ; // already define : PC+4
[88]	817	inst->_no_execute = 0;
[78]	818	inst->_event_type = EVENT_TYPE_NONE;
	819	}
	820
	821	void instruction_l_extwz (decod_instruction_t * inst, decod_param_t * param)
	822	{
	823	log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz");
	824
[88]	825	inst->_type = instruction_information(INSTRUCTION_L_EXTWZ)._type ; //TYPE_EXTEND;
	826	inst->_operation = instruction_information(INSTRUCTION_L_EXTWZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
[78]	827	inst->_has_immediat = 1;
	828	inst->_immediat = 32;
	829	inst->_read_ra = 1;
	830	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	831	inst->_read_rb = 0;
[97]	832	inst->_num_reg_rb = 0; //unnecessary
[78]	833	inst->_read_rc = 0;
[97]	834	inst->_num_reg_rc = 0; //unnecessary
[78]	835	inst->_write_rd = 1;
	836	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	837	inst->_write_re = 0;
[97]	838	inst->_num_reg_re = 0; //unnecessary
[78]	839	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	840	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	841	// inst->_branch_condition = ;
	842	// inst->_branch_stack_write = ;
	843	// inst->_branch_direction = ;
[97]	844	// inst->_address_next = ; // already define : PC+4
[88]	845	inst->_no_execute = 0;
[78]	846	inst->_event_type = EVENT_TYPE_NONE;
	847	}
	848
	849	void instruction_l_ff1 (decod_instruction_t * inst, decod_param_t * param)
	850	{
	851	log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1");
	852
[88]	853	inst->_type = instruction_information(INSTRUCTION_L_FF1)._type ; //TYPE_FIND;
	854	inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1;
[78]	855	inst->_has_immediat = 0;
[97]	856	inst->_immediat = 0; // unnecessary
[78]	857	inst->_read_ra = 1;
	858	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	859	inst->_read_rb = 0;
[97]	860	inst->_num_reg_rb = 0; //unnecessary
[78]	861	inst->_read_rc = 0;
[97]	862	inst->_num_reg_rc = 0; //unnecessary
[78]	863	inst->_write_rd = 1;
	864	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	865	inst->_write_re = 0;
[97]	866	inst->_num_reg_re = 0; //unnecessary
[78]	867	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	868	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	869	// inst->_branch_condition = ;
	870	// inst->_branch_stack_write = ;
	871	// inst->_branch_direction = ;
[97]	872	// inst->_address_next = ; // already define : PC+4
[88]	873	inst->_no_execute = 0;
[78]	874	inst->_event_type = EVENT_TYPE_NONE;
	875	}
	876
	877	void instruction_l_fl1 (decod_instruction_t * inst, decod_param_t * param)
	878	{
	879	log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1");
	880
[88]	881	inst->_type = instruction_information(INSTRUCTION_L_FL1)._type ; //TYPE_FIND;
	882	inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1;
[78]	883	inst->_has_immediat = 0;
[97]	884	inst->_immediat = 0; // unnecessary
[78]	885	inst->_read_ra = 1;
	886	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	887	inst->_read_rb = 0;
[97]	888	inst->_num_reg_rb = 0; //unnecessary
[78]	889	inst->_read_rc = 0;
[97]	890	inst->_num_reg_rc = 0; //unnecessary
[78]	891	inst->_write_rd = 1;
	892	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	893	inst->_write_re = 0;
[97]	894	inst->_num_reg_re = 0; //unnecessary
[78]	895	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	896	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	897	// inst->_branch_condition = ;
	898	// inst->_branch_stack_write = ;
	899	// inst->_branch_direction = ;
[97]	900	// inst->_address_next = ; // already define : PC+4
[88]	901	inst->_no_execute = 0;
[78]	902	inst->_event_type = EVENT_TYPE_NONE;
	903	}
	904
	905	void instruction_l_j (decod_instruction_t * inst, decod_param_t * param)
	906	{
	907	log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j");
	908
[88]	909	inst->_type = instruction_information(INSTRUCTION_L_J)._type ; //TYPE_BRANCH;
	910	inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE;
[78]	911	inst->_has_immediat = 0;
[97]	912	inst->_immediat = 0; // unnecessary
[78]	913	inst->_read_ra = 0;
[97]	914	inst->_num_reg_ra = 0; //unnecessary
[78]	915	inst->_read_rb = 0;
[97]	916	inst->_num_reg_rb = 0; //unnecessary
[78]	917	inst->_read_rc = 0;
[97]	918	inst->_num_reg_rc = 0; //unnecessary
[78]	919	inst->_write_rd = 0;
[97]	920	inst->_num_reg_rd = 0; //unnecessary
[78]	921	inst->_write_re = 0;
[97]	922	inst->_num_reg_re = 0; //unnecessary
[78]	923	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	924	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	925	inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK;
	926	// inst->_branch_stack_write = 0;
	927	inst->_branch_direction = 1;
[88]	928	inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
	929	);
	930	inst->_no_execute = 1;
[78]	931	inst->_event_type = EVENT_TYPE_NONE;
	932	}
	933
	934	void instruction_l_jal (decod_instruction_t * inst, decod_param_t * param)
	935	{
	936	log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal");
	937
[88]	938	inst->_type = instruction_information(INSTRUCTION_L_JAL)._type ; //TYPE_BRANCH;
	939	inst->_operation = instruction_information(INSTRUCTION_L_JAL)._operation; //OPERATION_BRANCH_L_JALR;
[78]	940	inst->_has_immediat = 1;
[86]	941	inst->_immediat = inst->_address_next+1;
[78]	942	inst->_read_ra = 0;
[97]	943	inst->_num_reg_ra = 0; //unnecessary
[78]	944	inst->_read_rb = 0;
[97]	945	inst->_num_reg_rb = 0; //unnecessary
[78]	946	inst->_read_rc = 0;
[97]	947	inst->_num_reg_rc = 0; //unnecessary
[78]	948	inst->_write_rd = 1;
	949	inst->_num_reg_rd = 9; // Link register
	950	inst->_write_re = 0;
[97]	951	inst->_num_reg_re = 0; //unnecessary
[78]	952	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	953	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	954	inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump
	955	// inst->_branch_stack_write = 1;
	956	inst->_branch_direction = 1;
[88]	957	inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
	958	);
	959	inst->_no_execute = 0;
[78]	960	inst->_event_type = EVENT_TYPE_NONE;
	961	}
	962
	963	void instruction_l_jalr (decod_instruction_t * inst, decod_param_t * param)
	964	{
	965	log_printf(TRACE,Decod,"instruction_l_jalr"," * instruction : l.jalr");
	966
	967	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	968
	969	if (inst->_num_reg_rb == 9)
	970	{
	971	instruction_illegal (inst, param);
	972	}
	973	else
	974	{
[88]	975	inst->_type = instruction_information(INSTRUCTION_L_JALR)._type ; //TYPE_BRANCH;
	976	inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR;
[100]	977	inst->_has_immediat = 1;
	978	inst->_immediat = inst->_address_next+1;
[78]	979	inst->_read_ra = 0;
[97]	980	inst->_num_reg_ra = 0; //unnecessary
[78]	981	inst->_read_rb = 1;
	982	// inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	983	inst->_read_rc = 0;
[97]	984	inst->_num_reg_rc = 0; //unnecessary
[78]	985	inst->_write_rd = 1;
	986	inst->_num_reg_rd = 9; // Link register
	987	inst->_write_re = 0;
[97]	988	inst->_num_reg_re = 0; //unnecessary
[78]	989	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	990	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	991	// inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER;
	992	inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK;
	993	// inst->_branch_stack_write = 1;
	994	inst->_branch_direction = 1;
[97]	995	// inst->_address_next = ; // already define : PC+4
[88]	996	inst->_no_execute = 0;
[78]	997	inst->_event_type = EVENT_TYPE_NONE;
	998	}
	999	}
	1000
	1001	void instruction_l_jr (decod_instruction_t * inst, decod_param_t * param)
	1002	{
	1003	log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr");
	1004
[88]	1005	inst->_type = instruction_information(INSTRUCTION_L_JR)._type ; //TYPE_BRANCH;
	1006	inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR;
[78]	1007	inst->_has_immediat = 0;
[97]	1008	inst->_immediat = 0; // unnecessary
[78]	1009	inst->_read_ra = 0;
[97]	1010	inst->_num_reg_ra = 0; //unnecessary
[78]	1011	inst->_read_rb = 1;
	1012	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1013	inst->_read_rc = 0;
[97]	1014	inst->_num_reg_rc = 0; //unnecessary
[78]	1015	inst->_write_rd = 0;
[97]	1016	inst->_num_reg_rd = 0; //unnecessary
[78]	1017	inst->_write_re = 0;
[97]	1018	inst->_num_reg_re = 0; //unnecessary
[78]	1019	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1020	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1021	inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK;
	1022	// inst->_branch_stack_write = 0;
	1023	inst->_branch_direction = 1;
[97]	1024	// inst->_address_next = ; // already define : PC+4
[88]	1025	inst->_no_execute = 0;
[78]	1026	inst->_event_type = EVENT_TYPE_NONE;
	1027	}
	1028
	1029	void instruction_l_lbs (decod_instruction_t * inst, decod_param_t * param)
	1030	{
	1031	log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs");
	1032
[88]	1033	inst->_type = instruction_information(INSTRUCTION_L_LBS)._type ; //TYPE_MEMORY;
	1034	inst->_operation = instruction_information(INSTRUCTION_L_LBS)._operation; //OPERATION_MEMORY_LOAD_8_S;
[78]	1035	inst->_has_immediat = 1;
	1036	inst->_immediat = EXTENDS(inst->_instruction,16);
	1037	inst->_read_ra = 1;
	1038	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1039	inst->_read_rb = 0;
[97]	1040	inst->_num_reg_rb = 0; //unnecessary
[78]	1041	inst->_read_rc = 0;
[97]	1042	inst->_num_reg_rc = 0; //unnecessary
[78]	1043	inst->_write_rd = 1;
	1044	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1045	inst->_write_re = 0;
[97]	1046	inst->_num_reg_re = 0; //unnecessary
[78]	1047	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
[88]	1048	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1049	// inst->_branch_condition = ;
	1050	// inst->_branch_stack_write = ;
	1051	// inst->_branch_direction = ;
[97]	1052	// inst->_address_next = ; // already define : PC+4
[88]	1053	inst->_no_execute = 0;
[78]	1054	inst->_event_type = EVENT_TYPE_NONE;
	1055	}
	1056
	1057	void instruction_l_lbz (decod_instruction_t * inst, decod_param_t * param)
	1058	{
	1059	log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz");
	1060
[88]	1061	inst->_type = instruction_information(INSTRUCTION_L_LBZ)._type ; //TYPE_MEMORY;
	1062	inst->_operation = instruction_information(INSTRUCTION_L_LBZ)._operation; //OPERATION_MEMORY_LOAD_8_Z;
[78]	1063	inst->_has_immediat = 1;
	1064	inst->_immediat = EXTENDS(inst->_instruction,16);
	1065	inst->_read_ra = 1;
	1066	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1067	inst->_read_rb = 0;
[97]	1068	inst->_num_reg_rb = 0; //unnecessary
[78]	1069	inst->_read_rc = 0;
[97]	1070	inst->_num_reg_rc = 0; //unnecessary
[78]	1071	inst->_write_rd = 1;
	1072	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1073	inst->_write_re = 0;
[97]	1074	inst->_num_reg_re = 0; //unnecessary
[78]	1075	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
[88]	1076	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1077	// inst->_branch_condition = ;
	1078	// inst->_branch_stack_write = ;
	1079	// inst->_branch_direction = ;
[97]	1080	// inst->_address_next = ; // already define : PC+4
[88]	1081	inst->_no_execute = 0;
[78]	1082	inst->_event_type = EVENT_TYPE_NONE;
	1083	}
	1084
	1085	void instruction_l_ld (decod_instruction_t * inst, decod_param_t * param)
	1086	{
	1087	log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld");
	1088
[88]	1089	inst->_type = instruction_information(INSTRUCTION_L_LD)._type ; //TYPE_MEMORY;
	1090	inst->_operation = instruction_information(INSTRUCTION_L_LD)._operation; //OPERATION_MEMORY_LOAD_64_S;
[78]	1091	inst->_has_immediat = 1;
	1092	inst->_immediat = EXTENDS(inst->_instruction,16);
	1093	inst->_read_ra = 1;
	1094	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1095	inst->_read_rb = 0;
[97]	1096	inst->_num_reg_rb = 0; //unnecessary
[78]	1097	inst->_read_rc = 0;
[97]	1098	inst->_num_reg_rc = 0; //unnecessary
[78]	1099	inst->_write_rd = 1;
	1100	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1101	inst->_write_re = 0;
[97]	1102	inst->_num_reg_re = 0; //unnecessary
[78]	1103	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	1104	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1105	// inst->_branch_condition = ;
	1106	// inst->_branch_stack_write = ;
	1107	// inst->_branch_direction = ;
[97]	1108	// inst->_address_next = ; // already define : PC+4
[88]	1109	inst->_no_execute = 0;
[78]	1110	inst->_event_type = EVENT_TYPE_NONE;
	1111	}
	1112
	1113	void instruction_l_lhs (decod_instruction_t * inst, decod_param_t * param)
	1114	{
	1115	log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs");
	1116
[88]	1117	inst->_type = instruction_information(INSTRUCTION_L_LHS)._type ; //TYPE_MEMORY;
	1118	inst->_operation = instruction_information(INSTRUCTION_L_LHS)._operation; //OPERATION_MEMORY_LOAD_16_S;
[78]	1119	inst->_has_immediat = 1;
	1120	inst->_immediat = EXTENDS(inst->_instruction,16);
	1121	inst->_read_ra = 1;
	1122	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1123	inst->_read_rb = 0;
[97]	1124	inst->_num_reg_rb = 0; //unnecessary
[78]	1125	inst->_read_rc = 0;
[97]	1126	inst->_num_reg_rc = 0; //unnecessary
[78]	1127	inst->_write_rd = 1;
	1128	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1129	inst->_write_re = 0;
[97]	1130	inst->_num_reg_re = 0; //unnecessary
[78]	1131	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	1132	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1133	// inst->_branch_condition = ;
	1134	// inst->_branch_stack_write = ;
	1135	// inst->_branch_direction = ;
[97]	1136	// inst->_address_next = ; // already define : PC+4
[88]	1137	inst->_no_execute = 0;
[78]	1138	inst->_event_type = EVENT_TYPE_NONE;
	1139	}
	1140
	1141	void instruction_l_lhz (decod_instruction_t * inst, decod_param_t * param)
	1142	{
	1143	log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz");
	1144
[88]	1145	inst->_type = instruction_information(INSTRUCTION_L_LHZ)._type ; //TYPE_MEMORY;
	1146	inst->_operation = instruction_information(INSTRUCTION_L_LHZ)._operation; //OPERATION_MEMORY_LOAD_16_Z;
[78]	1147	inst->_has_immediat = 1;
	1148	inst->_immediat = EXTENDS(inst->_instruction,16);
	1149	inst->_read_ra = 1;
	1150	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1151	inst->_read_rb = 0;
[97]	1152	inst->_num_reg_rb = 0; //unnecessary
[78]	1153	inst->_read_rc = 0;
[97]	1154	inst->_num_reg_rc = 0; //unnecessary
[78]	1155	inst->_write_rd = 1;
	1156	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1157	inst->_write_re = 0;
[97]	1158	inst->_num_reg_re = 0; //unnecessary
[78]	1159	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	1160	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1161	// inst->_branch_condition = ;
	1162	// inst->_branch_stack_write = ;
	1163	// inst->_branch_direction = ;
[97]	1164	// inst->_address_next = ; // already define : PC+4
[88]	1165	inst->_no_execute = 0;
[78]	1166	inst->_event_type = EVENT_TYPE_NONE;
	1167	}
	1168
	1169	void instruction_l_lws (decod_instruction_t * inst, decod_param_t * param)
	1170	{
	1171	log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws");
	1172
[88]	1173	inst->_type = instruction_information(INSTRUCTION_L_LWS)._type ; //TYPE_MEMORY;
	1174	inst->_operation = instruction_information(INSTRUCTION_L_LWS)._operation; //OPERATION_MEMORY_LOAD_32_S;
[78]	1175	inst->_has_immediat = 1;
	1176	inst->_immediat = EXTENDS(inst->_instruction,16);
	1177	inst->_read_ra = 1;
	1178	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1179	inst->_read_rb = 0;
[97]	1180	inst->_num_reg_rb = 0; //unnecessary
[78]	1181	inst->_read_rc = 0;
[97]	1182	inst->_num_reg_rc = 0; //unnecessary
[78]	1183	inst->_write_rd = 1;
	1184	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1185	inst->_write_re = 0;
[97]	1186	inst->_num_reg_re = 0; //unnecessary
[78]	1187	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	1188	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1189	// inst->_branch_condition = ;
	1190	// inst->_branch_stack_write = ;
	1191	// inst->_branch_direction = ;
[97]	1192	// inst->_address_next = ; // already define : PC+4
[88]	1193	inst->_no_execute = 0;
[78]	1194	inst->_event_type = EVENT_TYPE_NONE;
	1195	}
	1196
	1197	void instruction_l_lwz (decod_instruction_t * inst, decod_param_t * param)
	1198	{
	1199	log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz");
	1200
[88]	1201	inst->_type = instruction_information(INSTRUCTION_L_LWZ)._type ; //TYPE_MEMORY;
	1202	inst->_operation = instruction_information(INSTRUCTION_L_LWZ)._operation; //OPERATION_MEMORY_LOAD_32_Z;
[78]	1203	inst->_has_immediat = 1;
	1204	inst->_immediat = EXTENDS(inst->_instruction,16);
	1205	inst->_read_ra = 1;
	1206	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1207	inst->_read_rb = 0;
[97]	1208	inst->_num_reg_rb = 0; //unnecessary
[78]	1209	inst->_read_rc = 0;
[97]	1210	inst->_num_reg_rc = 0; //unnecessary
[78]	1211	inst->_write_rd = 1;
	1212	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1213	inst->_write_re = 0;
[97]	1214	inst->_num_reg_re = 0; //unnecessary
[78]	1215	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	1216	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1217	// inst->_branch_condition = ;
	1218	// inst->_branch_stack_write = ;
	1219	// inst->_branch_direction = ;
[97]	1220	// inst->_address_next = ; // already define : PC+4
[88]	1221	inst->_no_execute = 0;
[78]	1222	inst->_event_type = EVENT_TYPE_NONE;
	1223	}
	1224
	1225	void instruction_l_mac (decod_instruction_t * inst, decod_param_t * param)
	1226	{
	1227	log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac");
	1228
[88]	1229	inst->_type = instruction_information(INSTRUCTION_L_MAC)._type ; //TYPE_SPECIAL;
	1230	inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC;
[78]	1231	inst->_has_immediat = 0;
[97]	1232	inst->_immediat = 0; // unnecessary
[78]	1233	inst->_read_ra = 1;
	1234	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1235	inst->_read_rb = 1;
	1236	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1237	inst->_read_rc = 0;
[97]	1238	inst->_num_reg_rc = 0; //unnecessary
[78]	1239	inst->_write_rd = 0;
[97]	1240	inst->_num_reg_rd = 0; //unnecessary
[78]	1241	inst->_write_re = 0;
[97]	1242	inst->_num_reg_re = 0; //unnecessary
[78]	1243	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1244	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1245	// inst->_branch_condition = ;
	1246	// inst->_branch_stack_write = ;
	1247	// inst->_branch_direction = ;
[97]	1248	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1249	inst->_no_execute = 0;
[78]	1250	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
	1251	}
	1252
	1253	void instruction_l_maci (decod_instruction_t * inst, decod_param_t * param)
	1254	{
	1255	log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci");
	1256
[88]	1257	inst->_type = instruction_information(INSTRUCTION_L_MACI)._type ; //TYPE_SPECIAL;
	1258	inst->_operation = instruction_information(INSTRUCTION_L_MACI)._operation; //OPERATION_SPECIAL_L_MAC;
[78]	1259	inst->_has_immediat = 1;
	1260	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
	1261	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
	1262	inst->_read_ra = 1;
	1263	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1264	inst->_read_rb = 0;
[97]	1265	inst->_num_reg_rb = 0; //unnecessary
[78]	1266	inst->_read_rc = 0;
[97]	1267	inst->_num_reg_rc = 0; //unnecessary
[78]	1268	inst->_write_rd = 0;
[97]	1269	inst->_num_reg_rd = 0; //unnecessary
[78]	1270	inst->_write_re = 0;
[97]	1271	inst->_num_reg_re = 0; //unnecessary
[78]	1272	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1273	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1274	// inst->_branch_condition = ;
	1275	// inst->_branch_stack_write = ;
	1276	// inst->_branch_direction = ;
[97]	1277	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1278	inst->_no_execute = 0;
[78]	1279	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
	1280	}
	1281
	1282	void instruction_l_macrc (decod_instruction_t * inst, decod_param_t * param)
	1283	{
	1284	log_printf(TRACE,Decod,"instruction_l_macrc"," * instruction : l.macrc");
	1285
	1286	if (range<uint32_t>(inst->_instruction,15, 0) != 0)
	1287	{
	1288	instruction_illegal (inst, param);
	1289	}
	1290	else
	1291	{
[88]	1292	inst->_type = instruction_information(INSTRUCTION_L_MACRC)._type ; //TYPE_SPECIAL;
	1293	inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC;
[78]	1294	inst->_has_immediat = 0;
[97]	1295	inst->_immediat = 0; // unnecessary
[78]	1296	inst->_read_ra = 0;
[97]	1297	inst->_num_reg_ra = 0; //unnecessary
[78]	1298	inst->_read_rb = 0;
[97]	1299	inst->_num_reg_rb = 0; //unnecessary
[78]	1300	inst->_read_rc = 0;
[97]	1301	inst->_num_reg_rc = 0; //unnecessary
[78]	1302	inst->_write_rd = 1;
	1303	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1304	inst->_write_re = 0;
[97]	1305	inst->_num_reg_re = 0; //unnecessary
[78]	1306	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1307	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1308	// inst->_branch_condition = ;
	1309	// inst->_branch_stack_write = ;
	1310	// inst->_branch_direction = ;
[97]	1311	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1312	inst->_no_execute = 0;
[78]	1313	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
	1314	}
	1315	}
	1316
	1317	void instruction_l_mfspr (decod_instruction_t * inst, decod_param_t * param)
	1318	{
	1319	log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr");
	1320
[88]	1321	inst->_type = instruction_information(INSTRUCTION_L_MFSPR)._type ; //TYPE_SPECIAL;
	1322	inst->_operation = instruction_information(INSTRUCTION_L_MFSPR)._operation; //OPERATION_SPECIAL_L_MFSPR;
[78]	1323	inst->_has_immediat = 1;
	1324	inst->_immediat = EXTENDZ(inst->_instruction,16);
	1325	inst->_read_ra = 1;
	1326	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1327	inst->_read_rb = 0;
[97]	1328	inst->_num_reg_rb = 0; //unnecessary
[78]	1329	inst->_read_rc = 0;
[97]	1330	inst->_num_reg_rc = 0; //unnecessary
[78]	1331	inst->_write_rd = 1;
	1332	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1333	inst->_write_re = 0;
[97]	1334	inst->_num_reg_re = 0; //unnecessary
[78]	1335	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1336	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1337	// inst->_branch_condition = ;
	1338	// inst->_branch_stack_write = ;
	1339	// inst->_branch_direction = ;
[97]	1340	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1341	inst->_no_execute = 0;
[78]	1342	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
	1343	}
	1344
	1345	void instruction_l_movhi (decod_instruction_t * inst, decod_param_t * param)
	1346	{
	1347	log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi");
	1348
[88]	1349	inst->_type = instruction_information(INSTRUCTION_L_MOVHI)._type ; //TYPE_MOVE;
	1350	inst->_operation = instruction_information(INSTRUCTION_L_MOVHI)._operation; //OPERATION_MOVE_L_MOVHI;
[78]	1351	inst->_has_immediat = 1;
	1352	inst->_immediat = EXTENDZ(inst->_instruction,16);
	1353	inst->_read_ra = 0;
[97]	1354	inst->_num_reg_ra = 0; //unnecessary
[78]	1355	inst->_read_rb = 0;
[97]	1356	inst->_num_reg_rb = 0; //unnecessary
[78]	1357	inst->_read_rc = 0;
[97]	1358	inst->_num_reg_rc = 0; //unnecessary
[78]	1359	inst->_write_rd = 1;
	1360	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1361	inst->_write_re = 0;
[97]	1362	inst->_num_reg_re = 0; //unnecessary
[78]	1363	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1364	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1365	// inst->_branch_condition = ;
	1366	// inst->_branch_stack_write = ;
	1367	// inst->_branch_direction = ;
[97]	1368	// inst->_address_next = ; // already define : PC+4
[88]	1369	inst->_no_execute = 0;
[78]	1370	inst->_event_type = EVENT_TYPE_NONE;
	1371	}
	1372
	1373	void instruction_l_msb (decod_instruction_t * inst, decod_param_t * param)
	1374	{
	1375	log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb");
	1376
[88]	1377	inst->_type = instruction_information(INSTRUCTION_L_MSB)._type ; //TYPE_SPECIAL;
	1378	inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB;
[78]	1379	inst->_has_immediat = 0;
[97]	1380	inst->_immediat = 0; // unnecessary
[78]	1381	inst->_read_ra = 1;
	1382	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1383	inst->_read_rb = 1;
	1384	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1385	inst->_read_rc = 0;
[97]	1386	inst->_num_reg_rc = 0; //unnecessary
[78]	1387	inst->_write_rd = 0;
[97]	1388	inst->_num_reg_rd = 0; //unnecessary
[78]	1389	inst->_write_re = 0;
[97]	1390	inst->_num_reg_re = 0; //unnecessary
[78]	1391	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1392	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1393	// inst->_branch_condition = ;
	1394	// inst->_branch_stack_write = ;
	1395	// inst->_branch_direction = ;
[97]	1396	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1397	inst->_no_execute = 0;
[78]	1398	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
	1399	}
	1400
	1401	void instruction_l_msync (decod_instruction_t * inst, decod_param_t * param)
	1402	{
	1403	log_printf(TRACE,Decod,"instruction_l_msync"," * instruction : l.msync");
	1404
	1405	if (range<uint32_t>(inst->_instruction,22, 0) != 0)
	1406	{
	1407	instruction_illegal (inst, param);
	1408	}
	1409	else
	1410	{
[88]	1411	inst->_type = instruction_information(INSTRUCTION_L_MSYNC)._type ; //TYPE_SPECIAL;
	1412	inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC;
[78]	1413	inst->_has_immediat = 0;
[97]	1414	inst->_immediat = 0; // unnecessary
[78]	1415	inst->_read_ra = 0;
[97]	1416	inst->_num_reg_ra = 0; //unnecessary
[78]	1417	inst->_read_rb = 0;
[97]	1418	inst->_num_reg_rb = 0; //unnecessary
[78]	1419	inst->_read_rc = 0;
[97]	1420	inst->_num_reg_rc = 0; //unnecessary
[78]	1421	inst->_write_rd = 0;
[97]	1422	inst->_num_reg_rd = 0; //unnecessary
[78]	1423	inst->_write_re = 0;
[97]	1424	inst->_num_reg_re = 0; //unnecessary
[78]	1425	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1426	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1427	// inst->_branch_condition = ;
	1428	// inst->_branch_stack_write = ;
	1429	// inst->_branch_direction = ;
[97]	1430	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1431	inst->_no_execute = 0;
[78]	1432	inst->_event_type = EVENT_TYPE_MSYNC;
	1433	}
	1434	}
	1435
	1436	void instruction_l_mtspr (decod_instruction_t * inst, decod_param_t * param)
	1437	{
	1438	log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr");
	1439
[88]	1440	inst->_type = instruction_information(INSTRUCTION_L_MTSPR)._type ; //TYPE_SPECIAL;
	1441	inst->_operation = instruction_information(INSTRUCTION_L_MTSPR)._operation; //OPERATION_SPECIAL_L_MTSPR;
[78]	1442	inst->_has_immediat = 1;
	1443	inst->_immediat = EXTENDZ(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
	1444	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
	1445	inst->_read_ra = 1;
	1446	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1447	inst->_read_rb = 1;
	1448	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1449	inst->_read_rc = 0;
[97]	1450	inst->_num_reg_rc = 0; //unnecessary
[78]	1451	inst->_write_rd = 0;
[97]	1452	inst->_num_reg_rd = 0; //unnecessary
[78]	1453	inst->_write_re = 0;
[97]	1454	inst->_num_reg_re = 0; //unnecessary
[78]	1455	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1456	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1457	// inst->_branch_condition = ;
	1458	// inst->_branch_stack_write = ;
	1459	// inst->_branch_direction = ;
[97]	1460	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1461	inst->_no_execute = 0;
[78]	1462	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
	1463	}
	1464
	1465	void instruction_l_mul (decod_instruction_t * inst, decod_param_t * param)
	1466	{
	1467	log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul");
	1468
[88]	1469	inst->_type = instruction_information(INSTRUCTION_L_MUL)._type ; //TYPE_MUL;
	1470	inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL;
[78]	1471	inst->_has_immediat = 0;
[97]	1472	inst->_immediat = 0; // unnecessary
[78]	1473	inst->_read_ra = 1;
	1474	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1475	inst->_read_rb = 1;
	1476	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1477	inst->_read_rc = 0;
[97]	1478	inst->_num_reg_rc = 0; //unnecessary
[78]	1479	inst->_write_rd = 1;
	1480	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1481	inst->_write_re = 1;
	1482	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	1483	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	1484	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1485	// inst->_branch_condition = ;
	1486	// inst->_branch_stack_write = ;
	1487	// inst->_branch_direction = ;
[97]	1488	// inst->_address_next = ; // already define : PC+4
[88]	1489	inst->_no_execute = 0;
[78]	1490	inst->_event_type = EVENT_TYPE_NONE;
	1491	}
	1492
	1493	void instruction_l_muli (decod_instruction_t * inst, decod_param_t * param)
	1494	{
	1495	log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli");
	1496
[88]	1497	inst->_type = instruction_information(INSTRUCTION_L_MULI)._type ; //TYPE_MUL;
	1498	inst->_operation = instruction_information(INSTRUCTION_L_MULI)._operation; //OPERATION_MUL_L_MUL;
[78]	1499	inst->_has_immediat = 1;
	1500	inst->_immediat = EXTENDS(inst->_instruction,16);
	1501	inst->_read_ra = 1;
	1502	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1503	inst->_read_rb = 0;
[97]	1504	inst->_num_reg_rb = 0; //unnecessary
[78]	1505	inst->_read_rc = 0;
[97]	1506	inst->_num_reg_rc = 0; //unnecessary
[78]	1507	inst->_write_rd = 1;
	1508	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1509	inst->_write_re = 1;
	1510	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	1511	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	1512	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1513	// inst->_branch_condition = ;
	1514	// inst->_branch_stack_write = ;
	1515	// inst->_branch_direction = ;
[97]	1516	// inst->_address_next = ; // already define : PC+4
[88]	1517	inst->_no_execute = 0;
[78]	1518	inst->_event_type = EVENT_TYPE_NONE;
	1519	}
	1520
	1521	void instruction_l_mulu (decod_instruction_t * inst, decod_param_t * param)
	1522	{
	1523	log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu");
	1524
[88]	1525	inst->_type = instruction_information(INSTRUCTION_L_MULU)._type ; //TYPE_MUL;
	1526	inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU;
[78]	1527	inst->_has_immediat = 0;
[97]	1528	inst->_immediat = 0; // unnecessary
[78]	1529	inst->_read_ra = 1;
	1530	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1531	inst->_read_rb = 1;
	1532	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1533	inst->_read_rc = 0;
[97]	1534	inst->_num_reg_rc = 0; //unnecessary
[78]	1535	inst->_write_rd = 1;
	1536	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1537	inst->_write_re = 1;
	1538	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	1539	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	1540	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1541	// inst->_branch_condition = ;
	1542	// inst->_branch_stack_write = ;
	1543	// inst->_branch_direction = ;
[97]	1544	// inst->_address_next = ; // already define : PC+4
[88]	1545	inst->_no_execute = 0;
[78]	1546	inst->_event_type = EVENT_TYPE_NONE;
	1547	}
	1548
	1549	void instruction_l_nop (decod_instruction_t * inst, decod_param_t * param)
	1550	{
	1551	log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop");
	1552
[88]	1553	inst->_type = instruction_information(INSTRUCTION_L_NOP)._type ; //TYPE_SPECIAL;
	1554	inst->_operation = instruction_information(INSTRUCTION_L_NOP)._operation; //OPERATION_SPECIAL_L_NOP;
[78]	1555	// inst->_has_immediat = 1;
	1556	// inst->_immediat = EXTENDZ(inst->_instruction,16);
	1557	inst->_has_immediat = 0;
[97]	1558	inst->_immediat = 0; // unnecessary
[78]	1559	inst->_read_ra = 0;
[97]	1560	inst->_num_reg_ra = 0; //unnecessary
[78]	1561	inst->_read_rb = 0;
[97]	1562	inst->_num_reg_rb = 0; //unnecessary
[78]	1563	inst->_read_rc = 0;
[97]	1564	inst->_num_reg_rc = 0; //unnecessary
[78]	1565	inst->_write_rd = 0;
[97]	1566	inst->_num_reg_rd = 0; //unnecessary
[78]	1567	inst->_write_re = 0;
[97]	1568	inst->_num_reg_re = 0; //unnecessary
[78]	1569	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1570	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1571	// inst->_branch_condition = ;
	1572	// inst->_branch_stack_write = ;
	1573	// inst->_branch_direction = ;
[97]	1574	// inst->_address_next = ; // already define : PC+4
[88]	1575	inst->_no_execute = 1;
[78]	1576	inst->_event_type = EVENT_TYPE_NONE;
	1577	}
	1578
	1579	void instruction_l_or (decod_instruction_t * inst, decod_param_t * param)
	1580	{
	1581	log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or");
	1582
[88]	1583	inst->_type = instruction_information(INSTRUCTION_L_OR)._type ; //TYPE_ALU;
	1584	inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR;
[78]	1585	inst->_has_immediat = 0;
[97]	1586	inst->_immediat = 0; // unnecessary
[78]	1587	inst->_read_ra = 1;
	1588	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1589	inst->_read_rb = 1;
	1590	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1591	inst->_read_rc = 0;
[97]	1592	inst->_num_reg_rc = 0; //unnecessary
[78]	1593	inst->_write_rd = 1;
	1594	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1595	inst->_write_re = 0;
[97]	1596	inst->_num_reg_re = 0; //unnecessary
[78]	1597	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1598	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1599	// inst->_branch_condition = ;
	1600	// inst->_branch_stack_write = ;
	1601	// inst->_branch_direction = ;
[97]	1602	// inst->_address_next = ; // already define : PC+4
[88]	1603	inst->_no_execute = 0;
[78]	1604	inst->_event_type = EVENT_TYPE_NONE;
	1605	}
	1606
	1607	void instruction_l_ori (decod_instruction_t * inst, decod_param_t * param)
	1608	{
	1609	log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori");
	1610
[88]	1611	inst->_type = instruction_information(INSTRUCTION_L_ORI)._type ; //TYPE_ALU;
	1612	inst->_operation = instruction_information(INSTRUCTION_L_ORI)._operation; //OPERATION_ALU_L_OR;
[78]	1613	inst->_has_immediat = 1;
	1614	inst->_immediat = EXTENDZ(inst->_instruction,16);
	1615	inst->_read_ra = 1;
	1616	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1617	inst->_read_rb = 0;
[97]	1618	inst->_num_reg_rb = 0; //unnecessary
[78]	1619	inst->_read_rc = 0;
[97]	1620	inst->_num_reg_rc = 0; //unnecessary
[78]	1621	inst->_write_rd = 1;
	1622	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1623	inst->_write_re = 0;
[97]	1624	inst->_num_reg_re = 0; //unnecessary
[78]	1625	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1626	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1627	// inst->_branch_condition = ;
	1628	// inst->_branch_stack_write = ;
	1629	// inst->_branch_direction = ;
[97]	1630	// inst->_address_next = ; // already define : PC+4
[88]	1631	inst->_no_execute = 0;
[78]	1632	inst->_event_type = EVENT_TYPE_NONE;
	1633	}
	1634
	1635	void instruction_l_psync (decod_instruction_t * inst, decod_param_t * param)
	1636	{
	1637	log_printf(TRACE,Decod,"instruction_l_psync"," * instruction : l.psync");
	1638
	1639	if (range<uint32_t>(inst->_instruction,22, 0) != 0)
	1640	{
	1641	instruction_illegal (inst, param);
	1642	}
	1643	else
	1644	{
[88]	1645	inst->_type = instruction_information(INSTRUCTION_L_PSYNC)._type ; //TYPE_SPECIAL;
	1646	inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC;
[78]	1647	inst->_has_immediat = 0;
[97]	1648	inst->_immediat = 0; // unnecessary
[78]	1649	inst->_read_ra = 0;
[97]	1650	inst->_num_reg_ra = 0; //unnecessary
[78]	1651	inst->_read_rb = 0;
[97]	1652	inst->_num_reg_rb = 0; //unnecessary
[78]	1653	inst->_read_rc = 0;
[97]	1654	inst->_num_reg_rc = 0; //unnecessary
[78]	1655	inst->_write_rd = 0;
[97]	1656	inst->_num_reg_rd = 0; //unnecessary
[78]	1657	inst->_write_re = 0;
[97]	1658	inst->_num_reg_re = 0; //unnecessary
[78]	1659	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1660	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1661	// inst->_branch_condition = ;
	1662	// inst->_branch_stack_write = ;
	1663	// inst->_branch_direction = ;
[97]	1664	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1665	inst->_no_execute = 0;
[78]	1666	inst->_event_type = EVENT_TYPE_PSYNC;
	1667	}
	1668	}
	1669
	1670	void instruction_l_rfe (decod_instruction_t * inst, decod_param_t * param)
	1671	{
	1672	log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe");
	1673
[88]	1674	inst->_type = instruction_information(INSTRUCTION_L_RFE)._type ; //TYPE_SPECIAL;
	1675	inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE;
[78]	1676	inst->_has_immediat = 0;
[97]	1677	inst->_immediat = 0; // unnecessary
[78]	1678	inst->_read_ra = 0;
[97]	1679	inst->_num_reg_ra = 0; //unnecessary
[78]	1680	inst->_read_rb = 0;
[97]	1681	inst->_num_reg_rb = 0; //unnecessary
[78]	1682	inst->_read_rc = 0;
[97]	1683	inst->_num_reg_rc = 0; //unnecessary
[78]	1684	inst->_write_rd = 0;
[97]	1685	inst->_num_reg_rd = 0; //unnecessary
[78]	1686	inst->_write_re = 0;
[97]	1687	inst->_num_reg_re = 0; //unnecessary
[78]	1688	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1689	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1690	// inst->_branch_condition = ;
	1691	// inst->_branch_stack_write = ;
	1692	// inst->_branch_direction = ;
[97]	1693	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	1694	inst->_no_execute = 1;
[78]	1695	inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage
	1696	}
	1697
	1698	void instruction_l_ror (decod_instruction_t * inst, decod_param_t * param)
	1699	{
	1700	log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror");
	1701
[88]	1702	inst->_type = instruction_information(INSTRUCTION_L_ROR)._type ; //TYPE_SHIFT;
	1703	inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR;
[78]	1704	inst->_has_immediat = 0;
[97]	1705	inst->_immediat = 0; // unnecessary
[78]	1706	inst->_read_ra = 1;
	1707	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1708	inst->_read_rb = 1;
	1709	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1710	inst->_read_rc = 0;
[97]	1711	inst->_num_reg_rc = 0; //unnecessary
[78]	1712	inst->_write_rd = 1;
	1713	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1714	inst->_write_re = 0;
[97]	1715	inst->_num_reg_re = 0; //unnecessary
[78]	1716	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1717	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1718	// inst->_branch_condition = ;
	1719	// inst->_branch_stack_write = ;
	1720	// inst->_branch_direction = ;
[97]	1721	// inst->_address_next = ; // already define : PC+4
[88]	1722	inst->_no_execute = 0;
[78]	1723	inst->_event_type = EVENT_TYPE_NONE;
	1724	}
	1725
	1726	void instruction_l_rori (decod_instruction_t * inst, decod_param_t * param)
	1727	{
	1728	log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori");
	1729
[88]	1730	inst->_type = instruction_information(INSTRUCTION_L_RORI)._type ; //TYPE_SHIFT;
	1731	inst->_operation = instruction_information(INSTRUCTION_L_RORI)._operation; //OPERATION_SHIFT_L_ROR;
[78]	1732	inst->_has_immediat = 1;
	1733	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
	1734	inst->_read_ra = 1;
	1735	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1736	inst->_read_rb = 0;
[97]	1737	inst->_num_reg_rb = 0; //unnecessary
[78]	1738	inst->_read_rc = 0;
[97]	1739	inst->_num_reg_rc = 0; //unnecessary
[78]	1740	inst->_write_rd = 1;
	1741	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	1742	inst->_write_re = 0;
[97]	1743	inst->_num_reg_re = 0; //unnecessary
[78]	1744	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1745	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1746	// inst->_branch_condition = ;
	1747	// inst->_branch_stack_write = ;
	1748	// inst->_branch_direction = ;
[97]	1749	// inst->_address_next = ; // already define : PC+4
[88]	1750	inst->_no_execute = 0;
[78]	1751	inst->_event_type = EVENT_TYPE_NONE;
	1752	}
	1753
	1754	void instruction_l_sb (decod_instruction_t * inst, decod_param_t * param)
	1755	{
	1756	log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb");
	1757
[88]	1758	inst->_type = instruction_information(INSTRUCTION_L_SB)._type ; //TYPE_MEMORY;
	1759	inst->_operation = instruction_information(INSTRUCTION_L_SB)._operation; //OPERATION_MEMORY_STORE_8;
[78]	1760	inst->_has_immediat = 1;
	1761	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
	1762	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
	1763	inst->_read_ra = 1;
	1764	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1765	inst->_read_rb = 1;
	1766	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1767	inst->_read_rc = 0;
[97]	1768	inst->_num_reg_rc = 0; //unnecessary
[78]	1769	inst->_write_rd = 0;
[97]	1770	inst->_num_reg_rd = 0; //unnecessary
[78]	1771	inst->_write_re = 0;
[97]	1772	inst->_num_reg_re = 0; //unnecessary
[78]	1773	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
[88]	1774	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1775	// inst->_branch_condition = ;
	1776	// inst->_branch_stack_write = ;
	1777	// inst->_branch_direction = ;
[97]	1778	// inst->_address_next = ; // already define : PC+4
[88]	1779	inst->_no_execute = 0;
[78]	1780	inst->_event_type = EVENT_TYPE_NONE;
	1781	}
	1782
	1783	void instruction_l_sd (decod_instruction_t * inst, decod_param_t * param)
	1784	{
	1785	log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb");
	1786
[88]	1787	inst->_type = instruction_information(INSTRUCTION_L_SD)._type ; //TYPE_MEMORY;
	1788	inst->_operation = instruction_information(INSTRUCTION_L_SD)._operation; //OPERATION_MEMORY_STORE_64;
[78]	1789	inst->_has_immediat = 1;
	1790	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
	1791	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
	1792	inst->_read_ra = 1;
	1793	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1794	inst->_read_rb = 1;
	1795	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1796	inst->_read_rc = 0;
[97]	1797	inst->_num_reg_rc = 0; //unnecessary
[78]	1798	inst->_write_rd = 0;
[97]	1799	inst->_num_reg_rd = 0; //unnecessary
[78]	1800	inst->_write_re = 0;
[97]	1801	inst->_num_reg_re = 0; //unnecessary
[78]	1802	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	1803	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1804	// inst->_branch_condition = ;
	1805	// inst->_branch_stack_write = ;
	1806	// inst->_branch_direction = ;
[97]	1807	// inst->_address_next = ; // already define : PC+4
[88]	1808	inst->_no_execute = 0;
[78]	1809	inst->_event_type = EVENT_TYPE_NONE;
	1810	}
	1811
	1812	void instruction_l_sfeq (decod_instruction_t * inst, decod_param_t * param)
	1813	{
	1814	log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq");
	1815
[88]	1816	inst->_type = instruction_information(INSTRUCTION_L_SFEQ)._type ; //TYPE_TEST;
	1817	inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ;
[78]	1818	inst->_has_immediat = 0;
[97]	1819	inst->_immediat = 0; // unnecessary
[78]	1820	inst->_read_ra = 1;
	1821	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1822	inst->_read_rb = 1;
	1823	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1824	inst->_read_rc = 0;
[97]	1825	inst->_num_reg_rc = 0; //unnecessary
[78]	1826	inst->_write_rd = 0;
[97]	1827	inst->_num_reg_rd = 0; //unnecessary
[78]	1828	inst->_write_re = 1;
	1829	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1830	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1831	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1832	// inst->_branch_condition = ;
	1833	// inst->_branch_stack_write = ;
	1834	// inst->_branch_direction = ;
[97]	1835	// inst->_address_next = ; // already define : PC+4
[88]	1836	inst->_no_execute = 0;
[78]	1837	inst->_event_type = EVENT_TYPE_NONE;
	1838	}
	1839
	1840	void instruction_l_sfeqi (decod_instruction_t * inst, decod_param_t * param)
	1841	{
	1842	log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi");
	1843
[88]	1844	inst->_type = instruction_information(INSTRUCTION_L_SFEQI)._type ; //TYPE_TEST;
	1845	inst->_operation = instruction_information(INSTRUCTION_L_SFEQI)._operation; //OPERATION_TEST_L_SFEQ;
[78]	1846	inst->_has_immediat = 1;
	1847	inst->_immediat = EXTENDS(inst->_instruction,16);
	1848	inst->_read_ra = 1;
	1849	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1850	inst->_read_rb = 0;
[97]	1851	inst->_num_reg_rb = 0; //unnecessary
[78]	1852	inst->_read_rc = 0;
[97]	1853	inst->_num_reg_rc = 0; //unnecessary
[78]	1854	inst->_write_rd = 0;
[97]	1855	inst->_num_reg_rd = 0; //unnecessary
[78]	1856	inst->_write_re = 1;
	1857	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1858	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1859	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1860	// inst->_branch_condition = ;
	1861	// inst->_branch_stack_write = ;
	1862	// inst->_branch_direction = ;
[97]	1863	// inst->_address_next = ; // already define : PC+4
[88]	1864	inst->_no_execute = 0;
[78]	1865	inst->_event_type = EVENT_TYPE_NONE;
	1866	}
	1867
	1868	void instruction_l_sfges (decod_instruction_t * inst, decod_param_t * param)
	1869	{
	1870	log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges");
	1871
[88]	1872	inst->_type = instruction_information(INSTRUCTION_L_SFGES)._type ; //TYPE_TEST;
	1873	inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES;
[78]	1874	inst->_has_immediat = 0;
[97]	1875	inst->_immediat = 0; // unnecessary
[78]	1876	inst->_read_ra = 1;
	1877	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1878	inst->_read_rb = 1;
	1879	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1880	inst->_read_rc = 0;
[97]	1881	inst->_num_reg_rc = 0; //unnecessary
[78]	1882	inst->_write_rd = 0;
[97]	1883	inst->_num_reg_rd = 0; //unnecessary
[78]	1884	inst->_write_re = 1;
	1885	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1886	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1887	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1888	// inst->_branch_condition = ;
	1889	// inst->_branch_stack_write = ;
	1890	// inst->_branch_direction = ;
[97]	1891	// inst->_address_next = ; // already define : PC+4
[88]	1892	inst->_no_execute = 0;
[78]	1893	inst->_event_type = EVENT_TYPE_NONE;
	1894	}
	1895
	1896	void instruction_l_sfgesi (decod_instruction_t * inst, decod_param_t * param)
	1897	{
	1898	log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi");
	1899
[88]	1900	inst->_type = instruction_information(INSTRUCTION_L_SFGESI)._type ; //TYPE_TEST;
	1901	inst->_operation = instruction_information(INSTRUCTION_L_SFGESI)._operation; //OPERATION_TEST_L_SFGES;
[78]	1902	inst->_has_immediat = 1;
	1903	inst->_immediat = EXTENDS(inst->_instruction,16);
	1904	inst->_read_ra = 1;
	1905	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1906	inst->_read_rb = 0;
[97]	1907	inst->_num_reg_rb = 0; //unnecessary
[78]	1908	inst->_read_rc = 0;
[97]	1909	inst->_num_reg_rc = 0; //unnecessary
[78]	1910	inst->_write_rd = 0;
[97]	1911	inst->_num_reg_rd = 0; //unnecessary
[78]	1912	inst->_write_re = 1;
	1913	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1914	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1915	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1916	// inst->_branch_condition = ;
	1917	// inst->_branch_stack_write = ;
	1918	// inst->_branch_direction = ;
[97]	1919	// inst->_address_next = ; // already define : PC+4
[88]	1920	inst->_no_execute = 0;
[78]	1921	inst->_event_type = EVENT_TYPE_NONE;
	1922	}
	1923
	1924	void instruction_l_sfgeu (decod_instruction_t * inst, decod_param_t * param)
	1925	{
	1926	log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu");
	1927
[88]	1928	inst->_type = instruction_information(INSTRUCTION_L_SFGEU)._type ; //TYPE_TEST;
	1929	inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU;
[78]	1930	inst->_has_immediat = 0;
[97]	1931	inst->_immediat = 0; // unnecessary
[78]	1932	inst->_read_ra = 1;
	1933	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1934	inst->_read_rb = 1;
	1935	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1936	inst->_read_rc = 0;
[97]	1937	inst->_num_reg_rc = 0; //unnecessary
[78]	1938	inst->_write_rd = 0;
[97]	1939	inst->_num_reg_rd = 0; //unnecessary
[78]	1940	inst->_write_re = 1;
	1941	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1942	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1943	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1944	// inst->_branch_condition = ;
	1945	// inst->_branch_stack_write = ;
	1946	// inst->_branch_direction = ;
[97]	1947	// inst->_address_next = ; // already define : PC+4
[88]	1948	inst->_no_execute = 0;
[78]	1949	inst->_event_type = EVENT_TYPE_NONE;
	1950	}
	1951
	1952	void instruction_l_sfgeui (decod_instruction_t * inst, decod_param_t * param)
	1953	{
	1954	log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui");
	1955
[88]	1956	inst->_type = instruction_information(INSTRUCTION_L_SFGEUI)._type ; //TYPE_TEST;
	1957	inst->_operation = instruction_information(INSTRUCTION_L_SFGEUI)._operation; //OPERATION_TEST_L_SFGEU;
[78]	1958	inst->_has_immediat = 1;
	1959	inst->_immediat = EXTENDS(inst->_instruction,16);
	1960	inst->_read_ra = 1;
	1961	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1962	inst->_read_rb = 0;
[97]	1963	inst->_num_reg_rb = 0; //unnecessary
[78]	1964	inst->_read_rc = 0;
[97]	1965	inst->_num_reg_rc = 0; //unnecessary
[78]	1966	inst->_write_rd = 0;
[97]	1967	inst->_num_reg_rd = 0; //unnecessary
[78]	1968	inst->_write_re = 1;
	1969	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1970	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1971	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	1972	// inst->_branch_condition = ;
	1973	// inst->_branch_stack_write = ;
	1974	// inst->_branch_direction = ;
[97]	1975	// inst->_address_next = ; // already define : PC+4
[88]	1976	inst->_no_execute = 0;
[78]	1977	inst->_event_type = EVENT_TYPE_NONE;
	1978	}
	1979
	1980	void instruction_l_sfgts (decod_instruction_t * inst, decod_param_t * param)
	1981	{
	1982	log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts");
	1983
[88]	1984	inst->_type = instruction_information(INSTRUCTION_L_SFGTS)._type ; //TYPE_TEST;
	1985	inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS;
[78]	1986	inst->_has_immediat = 0;
[97]	1987	inst->_immediat = 0; // unnecessary
[78]	1988	inst->_read_ra = 1;
	1989	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	1990	inst->_read_rb = 1;
	1991	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	1992	inst->_read_rc = 0;
[97]	1993	inst->_num_reg_rc = 0; //unnecessary
[78]	1994	inst->_write_rd = 0;
[97]	1995	inst->_num_reg_rd = 0; //unnecessary
[78]	1996	inst->_write_re = 1;
	1997	inst->_num_reg_re = SPR_LOGIC_SR_F;
	1998	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	1999	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2000	// inst->_branch_condition = ;
	2001	// inst->_branch_stack_write = ;
	2002	// inst->_branch_direction = ;
[97]	2003	// inst->_address_next = ; // already define : PC+4
[88]	2004	inst->_no_execute = 0;
[78]	2005	inst->_event_type = EVENT_TYPE_NONE;
	2006	}
	2007
	2008	void instruction_l_sfgtsi (decod_instruction_t * inst, decod_param_t * param)
	2009	{
	2010	log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi");
	2011
[88]	2012	inst->_type = instruction_information(INSTRUCTION_L_SFGTSI)._type ; //TYPE_TEST;
	2013	inst->_operation = instruction_information(INSTRUCTION_L_SFGTSI)._operation; //OPERATION_TEST_L_SFGTS;
[78]	2014	inst->_has_immediat = 1;
	2015	inst->_immediat = EXTENDS(inst->_instruction,16);
	2016	inst->_read_ra = 1;
	2017	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2018	inst->_read_rb = 0;
[97]	2019	inst->_num_reg_rb = 0; //unnecessary
[78]	2020	inst->_read_rc = 0;
[97]	2021	inst->_num_reg_rc = 0; //unnecessary
[78]	2022	inst->_write_rd = 0;
[97]	2023	inst->_num_reg_rd = 0; //unnecessary
[78]	2024	inst->_write_re = 1;
	2025	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2026	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2027	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2028	// inst->_branch_condition = ;
	2029	// inst->_branch_stack_write = ;
	2030	// inst->_branch_direction = ;
[97]	2031	// inst->_address_next = ; // already define : PC+4
[88]	2032	inst->_no_execute = 0;
[78]	2033	inst->_event_type = EVENT_TYPE_NONE;
	2034	}
	2035
	2036	void instruction_l_sfgtu (decod_instruction_t * inst, decod_param_t * param)
	2037	{
	2038	log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu");
	2039
[88]	2040	inst->_type = instruction_information(INSTRUCTION_L_SFGTU)._type ; //TYPE_TEST;
	2041	inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU;
[78]	2042	inst->_has_immediat = 0;
[97]	2043	inst->_immediat = 0; // unnecessary
[78]	2044	inst->_read_ra = 1;
	2045	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2046	inst->_read_rb = 1;
	2047	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2048	inst->_read_rc = 0;
[97]	2049	inst->_num_reg_rc = 0; //unnecessary
[78]	2050	inst->_write_rd = 0;
[97]	2051	inst->_num_reg_rd = 0; //unnecessary
[78]	2052	inst->_write_re = 1;
	2053	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2054	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2055	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2056	// inst->_branch_condition = ;
	2057	// inst->_branch_stack_write = ;
	2058	// inst->_branch_direction = ;
[97]	2059	// inst->_address_next = ; // already define : PC+4
[88]	2060	inst->_no_execute = 0;
[78]	2061	inst->_event_type = EVENT_TYPE_NONE;
	2062	}
	2063
	2064	void instruction_l_sfgtui (decod_instruction_t * inst, decod_param_t * param)
	2065	{
	2066	log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui");
	2067
[88]	2068	inst->_type = instruction_information(INSTRUCTION_L_SFGTUI)._type ; //TYPE_TEST;
	2069	inst->_operation = instruction_information(INSTRUCTION_L_SFGTUI)._operation; //OPERATION_TEST_L_SFGTU;
[78]	2070	inst->_has_immediat = 1;
	2071	inst->_immediat = EXTENDS(inst->_instruction,16);
	2072	inst->_read_ra = 1;
	2073	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2074	inst->_read_rb = 0;
[97]	2075	inst->_num_reg_rb = 0; //unnecessary
[78]	2076	inst->_read_rc = 0;
[97]	2077	inst->_num_reg_rc = 0; //unnecessary
[78]	2078	inst->_write_rd = 0;
[97]	2079	inst->_num_reg_rd = 0; //unnecessary
[78]	2080	inst->_write_re = 1;
	2081	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2082	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2083	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2084	// inst->_branch_condition = ;
	2085	// inst->_branch_stack_write = ;
	2086	// inst->_branch_direction = ;
[97]	2087	// inst->_address_next = ; // already define : PC+4
[88]	2088	inst->_no_execute = 0;
[78]	2089	inst->_event_type = EVENT_TYPE_NONE;
	2090	}
	2091
	2092	void instruction_l_sfles (decod_instruction_t * inst, decod_param_t * param)
	2093	{
	2094	log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles");
	2095
[88]	2096	inst->_type = instruction_information(INSTRUCTION_L_SFLES)._type ; //TYPE_TEST;
	2097	inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES;
[78]	2098	inst->_has_immediat = 0;
[97]	2099	inst->_immediat = 0; // unnecessary
[78]	2100	inst->_read_ra = 1;
	2101	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2102	inst->_read_rb = 1;
	2103	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2104	inst->_read_rc = 0;
[97]	2105	inst->_num_reg_rc = 0; //unnecessary
[78]	2106	inst->_write_rd = 0;
[97]	2107	inst->_num_reg_rd = 0; //unnecessary
[78]	2108	inst->_write_re = 1;
	2109	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2110	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2111	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2112	// inst->_branch_condition = ;
	2113	// inst->_branch_stack_write = ;
	2114	// inst->_branch_direction = ;
[97]	2115	// inst->_address_next = ; // already define : PC+4
[88]	2116	inst->_no_execute = 0;
[78]	2117	inst->_event_type = EVENT_TYPE_NONE;
	2118	}
	2119
	2120	void instruction_l_sflesi (decod_instruction_t * inst, decod_param_t * param)
	2121	{
	2122	log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi");
	2123
[88]	2124	inst->_type = instruction_information(INSTRUCTION_L_SFLESI)._type ; //TYPE_TEST;
	2125	inst->_operation = instruction_information(INSTRUCTION_L_SFLESI)._operation; //OPERATION_TEST_L_SFLES;
[78]	2126	inst->_has_immediat = 1;
	2127	inst->_immediat = EXTENDS(inst->_instruction,16);
	2128	inst->_read_ra = 1;
	2129	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2130	inst->_read_rb = 0;
[97]	2131	inst->_num_reg_rb = 0; //unnecessary
[78]	2132	inst->_read_rc = 0;
[97]	2133	inst->_num_reg_rc = 0; //unnecessary
[78]	2134	inst->_write_rd = 0;
[97]	2135	inst->_num_reg_rd = 0; //unnecessary
[78]	2136	inst->_write_re = 1;
	2137	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2138	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2139	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2140	// inst->_branch_condition = ;
	2141	// inst->_branch_stack_write = ;
	2142	// inst->_branch_direction = ;
[97]	2143	// inst->_address_next = ; // already define : PC+4
[88]	2144	inst->_no_execute = 0;
[78]	2145	inst->_event_type = EVENT_TYPE_NONE;
	2146	}
	2147
	2148	void instruction_l_sfleu (decod_instruction_t * inst, decod_param_t * param)
	2149	{
	2150	log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu");
	2151
[88]	2152	inst->_type = instruction_information(INSTRUCTION_L_SFLEU)._type ; //TYPE_TEST;
	2153	inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU;
[78]	2154	inst->_has_immediat = 0;
[97]	2155	inst->_immediat = 0; // unnecessary
[78]	2156	inst->_read_ra = 1;
	2157	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2158	inst->_read_rb = 1;
	2159	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2160	inst->_read_rc = 0;
[97]	2161	inst->_num_reg_rc = 0; //unnecessary
[78]	2162	inst->_write_rd = 0;
[97]	2163	inst->_num_reg_rd = 0; //unnecessary
[78]	2164	inst->_write_re = 1;
	2165	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2166	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2167	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2168	// inst->_branch_condition = ;
	2169	// inst->_branch_stack_write = ;
	2170	// inst->_branch_direction = ;
[97]	2171	// inst->_address_next = ; // already define : PC+4
[88]	2172	inst->_no_execute = 0;
[78]	2173	inst->_event_type = EVENT_TYPE_NONE;
	2174	}
	2175
	2176	void instruction_l_sfleui (decod_instruction_t * inst, decod_param_t * param)
	2177	{
	2178	log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui");
	2179
[88]	2180	inst->_type = instruction_information(INSTRUCTION_L_SFLEUI)._type ; //TYPE_TEST;
	2181	inst->_operation = instruction_information(INSTRUCTION_L_SFLEUI)._operation; //OPERATION_TEST_L_SFLEU;
[78]	2182	inst->_has_immediat = 1;
	2183	inst->_immediat = EXTENDS(inst->_instruction,16);
	2184	inst->_read_ra = 1;
	2185	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2186	inst->_read_rb = 0;
[97]	2187	inst->_num_reg_rb = 0; //unnecessary
[78]	2188	inst->_read_rc = 0;
[97]	2189	inst->_num_reg_rc = 0; //unnecessary
[78]	2190	inst->_write_rd = 0;
[97]	2191	inst->_num_reg_rd = 0; //unnecessary
[78]	2192	inst->_write_re = 1;
	2193	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2194	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2195	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2196	// inst->_branch_condition = ;
	2197	// inst->_branch_stack_write = ;
	2198	// inst->_branch_direction = ;
[97]	2199	// inst->_address_next = ; // already define : PC+4
[88]	2200	inst->_no_execute = 0;
[78]	2201	inst->_event_type = EVENT_TYPE_NONE;
	2202	}
	2203
	2204	void instruction_l_sflts (decod_instruction_t * inst, decod_param_t * param)
	2205	{
	2206	log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts");
	2207
[88]	2208	inst->_type = instruction_information(INSTRUCTION_L_SFLTS)._type ; //TYPE_TEST;
	2209	inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS;
[78]	2210	inst->_has_immediat = 0;
[97]	2211	inst->_immediat = 0; // unnecessary
[78]	2212	inst->_read_ra = 1;
	2213	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2214	inst->_read_rb = 1;
	2215	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2216	inst->_read_rc = 0;
[97]	2217	inst->_num_reg_rc = 0; //unnecessary
[78]	2218	inst->_write_rd = 0;
[97]	2219	inst->_num_reg_rd = 0; //unnecessary
[78]	2220	inst->_write_re = 1;
	2221	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2222	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2223	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2224	// inst->_branch_condition = ;
	2225	// inst->_branch_stack_write = ;
	2226	// inst->_branch_direction = ;
[97]	2227	// inst->_address_next = ; // already define : PC+4
[88]	2228	inst->_no_execute = 0;
[78]	2229	inst->_event_type = EVENT_TYPE_NONE;
	2230	}
	2231
	2232	void instruction_l_sfltsi (decod_instruction_t * inst, decod_param_t * param)
	2233	{
	2234	log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi");
	2235
[88]	2236	inst->_type = instruction_information(INSTRUCTION_L_SFLTSI)._type ; //TYPE_TEST;
	2237	inst->_operation = instruction_information(INSTRUCTION_L_SFLTSI)._operation; //OPERATION_TEST_L_SFLTS;
[78]	2238	inst->_has_immediat = 1;
	2239	inst->_immediat = EXTENDS(inst->_instruction,16);
	2240	inst->_read_ra = 1;
	2241	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2242	inst->_read_rb = 0;
[97]	2243	inst->_num_reg_rb = 0; //unnecessary
[78]	2244	inst->_read_rc = 0;
[97]	2245	inst->_num_reg_rc = 0; //unnecessary
[78]	2246	inst->_write_rd = 0;
[97]	2247	inst->_num_reg_rd = 0; //unnecessary
[78]	2248	inst->_write_re = 1;
	2249	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2250	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2251	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2252	// inst->_branch_condition = ;
	2253	// inst->_branch_stack_write = ;
	2254	// inst->_branch_direction = ;
[97]	2255	// inst->_address_next = ; // already define : PC+4
[88]	2256	inst->_no_execute = 0;
[78]	2257	inst->_event_type = EVENT_TYPE_NONE;
	2258	}
	2259
	2260	void instruction_l_sfltu (decod_instruction_t * inst, decod_param_t * param)
	2261	{
	2262	log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu");
	2263
[88]	2264	inst->_type = instruction_information(INSTRUCTION_L_SFLTU)._type ; //TYPE_TEST;
	2265	inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU;
[78]	2266	inst->_has_immediat = 0;
[97]	2267	inst->_immediat = 0; // unnecessary
[78]	2268	inst->_read_ra = 1;
	2269	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2270	inst->_read_rb = 1;
	2271	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2272	inst->_read_rc = 0;
[97]	2273	inst->_num_reg_rc = 0; //unnecessary
[78]	2274	inst->_write_rd = 0;
[97]	2275	inst->_num_reg_rd = 0; //unnecessary
[78]	2276	inst->_write_re = 1;
	2277	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2278	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2279	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2280	// inst->_branch_condition = ;
	2281	// inst->_branch_stack_write = ;
	2282	// inst->_branch_direction = ;
[97]	2283	// inst->_address_next = ; // already define : PC+4
[88]	2284	inst->_no_execute = 0;
[78]	2285	inst->_event_type = EVENT_TYPE_NONE;
	2286	}
	2287
	2288	void instruction_l_sfltui (decod_instruction_t * inst, decod_param_t * param)
	2289	{
	2290	log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui");
	2291
[88]	2292	inst->_type = instruction_information(INSTRUCTION_L_SFLTUI)._type ; //TYPE_TEST;
	2293	inst->_operation = instruction_information(INSTRUCTION_L_SFLTUI)._operation; //OPERATION_TEST_L_SFLTU;
[78]	2294	inst->_has_immediat = 1;
	2295	inst->_immediat = EXTENDS(inst->_instruction,16);
	2296	inst->_read_ra = 1;
	2297	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2298	inst->_read_rb = 0;
[97]	2299	inst->_num_reg_rb = 0; //unnecessary
[78]	2300	inst->_read_rc = 0;
[97]	2301	inst->_num_reg_rc = 0; //unnecessary
[78]	2302	inst->_write_rd = 0;
[97]	2303	inst->_num_reg_rd = 0; //unnecessary
[78]	2304	inst->_write_re = 1;
	2305	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2306	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2307	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2308	// inst->_branch_condition = ;
	2309	// inst->_branch_stack_write = ;
	2310	// inst->_branch_direction = ;
[97]	2311	// inst->_address_next = ; // already define : PC+4
[88]	2312	inst->_no_execute = 0;
[78]	2313	inst->_event_type = EVENT_TYPE_NONE;
	2314	}
	2315
	2316	void instruction_l_sfne (decod_instruction_t * inst, decod_param_t * param)
	2317	{
	2318	log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne");
	2319
[88]	2320	inst->_type = instruction_information(INSTRUCTION_L_SFNE)._type ; //TYPE_TEST;
	2321	inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE;
[78]	2322	inst->_has_immediat = 0;
[97]	2323	inst->_immediat = 0; // unnecessary
[78]	2324	inst->_read_ra = 1;
	2325	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2326	inst->_read_rb = 1;
	2327	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2328	inst->_read_rc = 0;
[97]	2329	inst->_num_reg_rc = 0; //unnecessary
[78]	2330	inst->_write_rd = 0;
[97]	2331	inst->_num_reg_rd = 0; //unnecessary
[78]	2332	inst->_write_re = 1;
	2333	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2334	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2335	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2336	// inst->_branch_condition = ;
	2337	// inst->_branch_stack_write = ;
	2338	// inst->_branch_direction = ;
[97]	2339	// inst->_address_next = ; // already define : PC+4
[88]	2340	inst->_no_execute = 0;
[78]	2341	inst->_event_type = EVENT_TYPE_NONE;
	2342	}
	2343
	2344	void instruction_l_sfnei (decod_instruction_t * inst, decod_param_t * param)
	2345	{
	2346	log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei");
	2347
[88]	2348	inst->_type = instruction_information(INSTRUCTION_L_SFNEI)._type ; //TYPE_TEST;
	2349	inst->_operation = instruction_information(INSTRUCTION_L_SFNEI)._operation; //OPERATION_TEST_L_SFNE;
[78]	2350	inst->_has_immediat = 1;
	2351	inst->_immediat = EXTENDS(inst->_instruction,16);
	2352	inst->_read_ra = 1;
	2353	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2354	inst->_read_rb = 0;
[97]	2355	inst->_num_reg_rb = 0; //unnecessary
[78]	2356	inst->_read_rc = 0;
[97]	2357	inst->_num_reg_rc = 0; //unnecessary
[78]	2358	inst->_write_rd = 0;
[97]	2359	inst->_num_reg_rd = 0; //unnecessary
[78]	2360	inst->_write_re = 1;
	2361	inst->_num_reg_re = SPR_LOGIC_SR_F;
	2362	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2363	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2364	// inst->_branch_condition = ;
	2365	// inst->_branch_stack_write = ;
	2366	// inst->_branch_direction = ;
[97]	2367	// inst->_address_next = ; // already define : PC+4
[88]	2368	inst->_no_execute = 0;
[78]	2369	inst->_event_type = EVENT_TYPE_NONE;
	2370	}
	2371
	2372	void instruction_l_sh (decod_instruction_t * inst, decod_param_t * param)
	2373	{
	2374	log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh");
	2375
[88]	2376	inst->_type = instruction_information(INSTRUCTION_L_SH)._type ; //TYPE_MEMORY;
	2377	inst->_operation = instruction_information(INSTRUCTION_L_SH)._operation; //OPERATION_MEMORY_STORE_16;
[78]	2378	inst->_has_immediat = 1;
	2379	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
	2380	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
	2381	inst->_read_ra = 1;
	2382	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2383	inst->_read_rb = 1;
	2384	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2385	inst->_read_rc = 0;
[97]	2386	inst->_num_reg_rc = 0; //unnecessary
[78]	2387	inst->_write_rd = 0;
[97]	2388	inst->_num_reg_rd = 0; //unnecessary
[78]	2389	inst->_write_re = 0;
[97]	2390	inst->_num_reg_re = 0; //unnecessary
[78]	2391	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	2392	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2393	// inst->_branch_condition = ;
	2394	// inst->_branch_stack_write = ;
	2395	// inst->_branch_direction = ;
[97]	2396	// inst->_address_next = ; // already define : PC+4
[88]	2397	inst->_no_execute = 0;
[78]	2398	inst->_event_type = EVENT_TYPE_NONE;
	2399	}
	2400
	2401	void instruction_l_sll (decod_instruction_t * inst, decod_param_t * param)
	2402	{
	2403	log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll");
	2404
[88]	2405	inst->_type = instruction_information(INSTRUCTION_L_SLL)._type ; //TYPE_SHIFT;
	2406	inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL;
[78]	2407	inst->_has_immediat = 0;
[97]	2408	inst->_immediat = 0; // unnecessary
[78]	2409	inst->_read_ra = 1;
	2410	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2411	inst->_read_rb = 1;
	2412	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2413	inst->_read_rc = 0;
[97]	2414	inst->_num_reg_rc = 0; //unnecessary
[78]	2415	inst->_write_rd = 1;
	2416	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2417	inst->_write_re = 0;
[97]	2418	inst->_num_reg_re = 0; //unnecessary
[78]	2419	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2420	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2421	// inst->_branch_condition = ;
	2422	// inst->_branch_stack_write = ;
	2423	// inst->_branch_direction = ;
[97]	2424	// inst->_address_next = ; // already define : PC+4
[88]	2425	inst->_no_execute = 0;
[78]	2426	inst->_event_type = EVENT_TYPE_NONE;
	2427	}
	2428
	2429	void instruction_l_slli (decod_instruction_t * inst, decod_param_t * param)
	2430	{
	2431	log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli");
	2432
[88]	2433	inst->_type = instruction_information(INSTRUCTION_L_SLLI)._type ; //TYPE_SHIFT;
	2434	inst->_operation = instruction_information(INSTRUCTION_L_SLLI)._operation; //OPERATION_SHIFT_L_SLL;
[78]	2435	inst->_has_immediat = 1;
	2436	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
	2437	inst->_read_ra = 1;
	2438	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2439	inst->_read_rb = 0;
[97]	2440	inst->_num_reg_rb = 0; //unnecessary
[78]	2441	inst->_read_rc = 0;
[97]	2442	inst->_num_reg_rc = 0; //unnecessary
[78]	2443	inst->_write_rd = 1;
	2444	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2445	inst->_write_re = 0;
[97]	2446	inst->_num_reg_re = 0; //unnecessary
[78]	2447	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2448	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2449	// inst->_branch_condition = ;
	2450	// inst->_branch_stack_write = ;
	2451	// inst->_branch_direction = ;
[97]	2452	// inst->_address_next = ; // already define : PC+4
[88]	2453	inst->_no_execute = 0;
[78]	2454	inst->_event_type = EVENT_TYPE_NONE;
	2455	}
	2456
	2457	void instruction_l_sra (decod_instruction_t * inst, decod_param_t * param)
	2458	{
	2459	log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra");
	2460
[88]	2461	inst->_type = instruction_information(INSTRUCTION_L_SRA)._type ; //TYPE_SHIFT;
	2462	inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA;
[78]	2463	inst->_has_immediat = 0;
[97]	2464	inst->_immediat = 0; // unnecessary
[78]	2465	inst->_read_ra = 1;
	2466	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2467	inst->_read_rb = 1;
	2468	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2469	inst->_read_rc = 0;
[97]	2470	inst->_num_reg_rc = 0; //unnecessary
[78]	2471	inst->_write_rd = 1;
	2472	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2473	inst->_write_re = 0;
[97]	2474	inst->_num_reg_re = 0; //unnecessary
[78]	2475	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2476	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2477	// inst->_branch_condition = ;
	2478	// inst->_branch_stack_write = ;
	2479	// inst->_branch_direction = ;
[97]	2480	// inst->_address_next = ; // already define : PC+4
[88]	2481	inst->_no_execute = 0;
[78]	2482	inst->_event_type = EVENT_TYPE_NONE;
	2483	}
	2484
	2485	void instruction_l_srai (decod_instruction_t * inst, decod_param_t * param)
	2486	{
	2487	log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai");
	2488
[88]	2489	inst->_type = instruction_information(INSTRUCTION_L_SRAI)._type ; //TYPE_SHIFT;
	2490	inst->_operation = instruction_information(INSTRUCTION_L_SRAI)._operation; //OPERATION_SHIFT_L_SRA;
[78]	2491	inst->_has_immediat = 1;
	2492	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
	2493	inst->_read_ra = 1;
	2494	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2495	inst->_read_rb = 0;
[97]	2496	inst->_num_reg_rb = 0; //unnecessary
[78]	2497	inst->_read_rc = 0;
[97]	2498	inst->_num_reg_rc = 0; //unnecessary
[78]	2499	inst->_write_rd = 1;
	2500	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2501	inst->_write_re = 0;
[97]	2502	inst->_num_reg_re = 0; //unnecessary
[78]	2503	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2504	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2505	// inst->_branch_condition = ;
	2506	// inst->_branch_stack_write = ;
	2507	// inst->_branch_direction = ;
[97]	2508	// inst->_address_next = ; // already define : PC+4
[88]	2509	inst->_no_execute = 0;
[78]	2510	inst->_event_type = EVENT_TYPE_NONE;
	2511	}
	2512
	2513	void instruction_l_srl (decod_instruction_t * inst, decod_param_t * param)
	2514	{
	2515	log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl");
	2516
[88]	2517	inst->_type = instruction_information(INSTRUCTION_L_SRL)._type ; //TYPE_SHIFT;
	2518	inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL;
[78]	2519	inst->_has_immediat = 0;
[97]	2520	inst->_immediat = 0; // unnecessary
[78]	2521	inst->_read_ra = 1;
	2522	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2523	inst->_read_rb = 1;
	2524	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2525	inst->_read_rc = 0;
[97]	2526	inst->_num_reg_rc = 0; //unnecessary
[78]	2527	inst->_write_rd = 1;
	2528	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2529	inst->_write_re = 0;
[97]	2530	inst->_num_reg_re = 0; //unnecessary
[78]	2531	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2532	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2533	// inst->_branch_condition = ;
	2534	// inst->_branch_stack_write = ;
	2535	// inst->_branch_direction = ;
[97]	2536	// inst->_address_next = ; // already define : PC+4
[88]	2537	inst->_no_execute = 0;
[78]	2538	inst->_event_type = EVENT_TYPE_NONE;
	2539	}
	2540
	2541	void instruction_l_srli (decod_instruction_t * inst, decod_param_t * param)
	2542	{
	2543	log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli");
	2544
[88]	2545	inst->_type = instruction_information(INSTRUCTION_L_SRLI)._type ; //TYPE_SHIFT;
	2546	inst->_operation = instruction_information(INSTRUCTION_L_SRLI)._operation; //OPERATION_SHIFT_L_SRL;
[78]	2547	inst->_has_immediat = 1;
	2548	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
	2549	inst->_read_ra = 1;
	2550	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2551	inst->_read_rb = 0;
[97]	2552	inst->_num_reg_rb = 0; //unnecessary
[78]	2553	inst->_read_rc = 0;
[97]	2554	inst->_num_reg_rc = 0; //unnecessary
[78]	2555	inst->_write_rd = 1;
	2556	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2557	inst->_write_re = 0;
[97]	2558	inst->_num_reg_re = 0; //unnecessary
[78]	2559	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2560	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2561	// inst->_branch_condition = ;
	2562	// inst->_branch_stack_write = ;
	2563	// inst->_branch_direction = ;
[97]	2564	// inst->_address_next = ; // already define : PC+4
[88]	2565	inst->_no_execute = 0;
[78]	2566	inst->_event_type = EVENT_TYPE_NONE;
	2567	}
	2568
	2569	void instruction_l_sub (decod_instruction_t * inst, decod_param_t * param)
	2570	{
	2571	log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub");
	2572
[88]	2573	inst->_type = instruction_information(INSTRUCTION_L_SUB)._type ; //TYPE_ALU;
	2574	inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB;
[78]	2575	inst->_has_immediat = 0;
[97]	2576	inst->_immediat = 0; // unnecessary
[78]	2577	inst->_read_ra = 1;
	2578	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2579	inst->_read_rb = 1;
	2580	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2581	inst->_read_rc = 0;
[97]	2582	inst->_num_reg_rc = 0; //unnecessary
[78]	2583	inst->_write_rd = 1;
	2584	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2585	inst->_write_re = 1;
	2586	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
	2587	inst->_exception_use = EXCEPTION_USE_RANGE;
[88]	2588	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2589	// inst->_branch_condition = ;
	2590	// inst->_branch_stack_write = ;
	2591	// inst->_branch_direction = ;
[97]	2592	// inst->_address_next = ; // already define : PC+4
[88]	2593	inst->_no_execute = 0;
[78]	2594	inst->_event_type = EVENT_TYPE_NONE;
	2595	}
	2596
	2597	void instruction_l_sw (decod_instruction_t * inst, decod_param_t * param)
	2598	{
	2599	log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw");
	2600
[88]	2601	inst->_type = instruction_information(INSTRUCTION_L_SW)._type ; //TYPE_MEMORY;
	2602	inst->_operation = instruction_information(INSTRUCTION_L_SW)._operation; //OPERATION_MEMORY_STORE_32;
[78]	2603	inst->_has_immediat = 1;
	2604	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
	2605	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
	2606	inst->_read_ra = 1;
	2607	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2608	inst->_read_rb = 1;
	2609	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2610	inst->_read_rc = 0;
[97]	2611	inst->_num_reg_rc = 0; //unnecessary
[78]	2612	inst->_write_rd = 0;
[97]	2613	inst->_num_reg_rd = 0; //unnecessary
[78]	2614	inst->_write_re = 0;
[97]	2615	inst->_num_reg_re = 0; //unnecessary
[78]	2616	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
[88]	2617	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2618	// inst->_branch_condition = ;
	2619	// inst->_branch_stack_write = ;
	2620	// inst->_branch_direction = ;
[97]	2621	// inst->_address_next = ; // already define : PC+4
[88]	2622	inst->_no_execute = 0;
[78]	2623	inst->_event_type = EVENT_TYPE_NONE;
	2624	}
	2625
	2626	void instruction_l_sys (decod_instruction_t * inst, decod_param_t * param)
	2627	{
	2628	log_printf(TRACE,Decod,"instruction_l_sys"," * instruction : l.sys");
	2629
	2630	if (range<uint32_t>(inst->_instruction,22,16) != 0)
	2631	{
	2632	instruction_illegal (inst, param);
	2633	}
	2634	else
	2635	{
[88]	2636	inst->_type = instruction_information(INSTRUCTION_L_SYS)._type ; //TYPE_SPECIAL;
	2637	inst->_operation = instruction_information(INSTRUCTION_L_SYS)._operation; //OPERATION_SPECIAL_L_SYS;
[78]	2638	// inst->_has_immediat = 1;
	2639	// inst->_immediat = EXTENDZ(inst->_instruction,16);
	2640	inst->_has_immediat = 0;
[97]	2641	inst->_immediat = 0; // unnecessary
[78]	2642	inst->_read_ra = 0;
[97]	2643	inst->_num_reg_ra = 0; //unnecessary
[78]	2644	inst->_read_rb = 0;
[97]	2645	inst->_num_reg_rb = 0; //unnecessary
[78]	2646	inst->_read_rc = 0;
[97]	2647	inst->_num_reg_rc = 0; //unnecessary
[78]	2648	inst->_write_rd = 0;
[97]	2649	inst->_num_reg_rd = 0; //unnecessary
[78]	2650	inst->_write_re = 0;
[97]	2651	inst->_num_reg_re = 0; //unnecessary
[78]	2652	inst->_exception_use = EXCEPTION_USE_SYSCALL;
[88]	2653	inst->_exception = EXCEPTION_SYSCALL;
[78]	2654	// inst->_branch_condition = ;
	2655	// inst->_branch_stack_write = ;
	2656	// inst->_branch_direction = ;
	2657
	2658	// if (inst->_is_delay_slot)
	2659	// inst->_address_next = inst->_address_previous;
	2660	// else
	2661	// inst->_address_next = inst->_address;
	2662
	2663
[97]	2664	// inst->_address_next = ; // already define : PC+4 // don't change
[88]	2665	inst->_no_execute = 1;
[78]	2666	inst->_event_type = EVENT_TYPE_EXCEPTION;
	2667	}
	2668	}
	2669
	2670	void instruction_l_trap (decod_instruction_t * inst, decod_param_t * param)
	2671	{
	2672	log_printf(TRACE,Decod,"instruction_l_trap"," * instruction : l.trap");
	2673
	2674	if (range<uint32_t>(inst->_instruction,22,16) != 0)
	2675	{
	2676	instruction_illegal (inst, param);
	2677	}
	2678	else
	2679	{
[88]	2680	inst->_type = instruction_information(INSTRUCTION_L_TRAP)._type ; //TYPE_SPECIAL;
	2681	inst->_operation = instruction_information(INSTRUCTION_L_TRAP)._operation; //OPERATION_SPECIAL_L_TRAP;
[78]	2682	inst->_has_immediat = 1;
	2683	inst->_immediat = EXTENDZ(inst->_instruction,16);
	2684	inst->_read_ra = 0;
[97]	2685	inst->_num_reg_ra = 0; //unnecessary
[78]	2686	inst->_read_rb = 0;
[97]	2687	inst->_num_reg_rb = 0; //unnecessary
[78]	2688	inst->_read_rc = 0; // read all SR
[97]	2689	inst->_num_reg_rc = 0; //unnecessary
[78]	2690	inst->_write_rd = 0;
[97]	2691	inst->_num_reg_rd = 0; //unnecessary
[78]	2692	inst->_write_re = 0;
[97]	2693	inst->_num_reg_re = 0; //unnecessary
[78]	2694	inst->_exception_use = EXCEPTION_USE_TRAP;
[88]	2695	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2696	// inst->_branch_condition = ;
	2697	// inst->_branch_stack_write = ;
	2698	// inst->_branch_direction = ;
[97]	2699	// inst->_address_next = ; // already define : PC+4
[88]	2700	inst->_no_execute = 1;
[78]	2701	inst->_event_type = EVENT_TYPE_NONE;
	2702	}
	2703	}
	2704
	2705	void instruction_l_xor (decod_instruction_t * inst, decod_param_t * param)
	2706	{
	2707	log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor");
	2708
[88]	2709	inst->_type = instruction_information(INSTRUCTION_L_XOR)._type ; //TYPE_ALU;
	2710	inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR;
[78]	2711	inst->_has_immediat = 0;
[97]	2712	inst->_immediat = 0; // unnecessary
[78]	2713	inst->_read_ra = 1;
	2714	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2715	inst->_read_rb = 1;
	2716	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
	2717	inst->_read_rc = 0;
[97]	2718	inst->_num_reg_rc = 0; //unnecessary
[78]	2719	inst->_write_rd = 1;
	2720	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2721	inst->_write_re = 0;
[97]	2722	inst->_num_reg_re = 0; //unnecessary
[78]	2723	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2724	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2725	// inst->_branch_condition = ;
	2726	// inst->_branch_stack_write = ;
	2727	// inst->_branch_direction = ;
[97]	2728	// inst->_address_next = ; // already define : PC+4
[88]	2729	inst->_no_execute = 0;
[78]	2730	inst->_event_type = EVENT_TYPE_NONE;
	2731	}
	2732
	2733	void instruction_l_xori (decod_instruction_t * inst, decod_param_t * param)
	2734	{
	2735	log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori");
	2736
[88]	2737	inst->_type = instruction_information(INSTRUCTION_L_XORI)._type ; //TYPE_ALU;
	2738	inst->_operation = instruction_information(INSTRUCTION_L_XORI)._operation; //OPERATION_ALU_L_XOR;
[78]	2739	inst->_has_immediat = 1;
	2740	inst->_immediat = EXTENDS(inst->_instruction,16);
	2741	inst->_read_ra = 1;
	2742	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
	2743	inst->_read_rb = 0;
[97]	2744	inst->_num_reg_rb = 0; //unnecessary
[78]	2745	inst->_read_rc = 0;
[97]	2746	inst->_num_reg_rc = 0; //unnecessary
[78]	2747	inst->_write_rd = 1;
	2748	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
	2749	inst->_write_re = 0;
[97]	2750	inst->_num_reg_re = 0; //unnecessary
[78]	2751	inst->_exception_use = EXCEPTION_USE_NONE;
[88]	2752	inst->_exception = EXCEPTION_DECOD_NONE;
[78]	2753	// inst->_branch_condition = ;
	2754	// inst->_branch_stack_write = ;
	2755	// inst->_branch_direction = ;
[97]	2756	// inst->_address_next = ; // already define : PC+4
[88]	2757	inst->_no_execute = 0;
[78]	2758	inst->_event_type = EVENT_TYPE_NONE;
	2759	}
	2760
	2761	// // ORFPX
	2762	// void instruction_lf_add_d (decod_instruction_t * inst, decod_param_t * param)
	2763	// void instruction_lf_add_s (decod_instruction_t * inst, decod_param_t * param)
	2764	// void instruction_lf_cust1_d (decod_instruction_t * inst, decod_param_t * param)
	2765	// void instruction_lf_cust1_s (decod_instruction_t * inst, decod_param_t * param)
	2766	// void instruction_lf_div_d (decod_instruction_t * inst, decod_param_t * param)
	2767	// void instruction_lf_div_s (decod_instruction_t * inst, decod_param_t * param)
	2768	// void instruction_lf_ftoi_d (decod_instruction_t * inst, decod_param_t * param)
	2769	// void instruction_lf_ftoi_s (decod_instruction_t * inst, decod_param_t * param)
	2770	// void instruction_lf_itof_d (decod_instruction_t * inst, decod_param_t * param)
	2771	// void instruction_lf_itof_s (decod_instruction_t * inst, decod_param_t * param)
	2772	// void instruction_lf_madd_d (decod_instruction_t * inst, decod_param_t * param)
	2773	// void instruction_lf_madd_s (decod_instruction_t * inst, decod_param_t * param)
	2774	// void instruction_lf_mul_d (decod_instruction_t * inst, decod_param_t * param)
	2775	// void instruction_lf_mul_s (decod_instruction_t * inst, decod_param_t * param)
	2776	// void instruction_lf_rem_d (decod_instruction_t * inst, decod_param_t * param)
	2777	// void instruction_lf_rem_s (decod_instruction_t * inst, decod_param_t * param)
	2778	// void instruction_lf_sfeq_d (decod_instruction_t * inst, decod_param_t * param)
	2779	// void instruction_lf_sfeq_s (decod_instruction_t * inst, decod_param_t * param)
	2780	// void instruction_lf_sfge_d (decod_instruction_t * inst, decod_param_t * param)
	2781	// void instruction_lf_sfge_s (decod_instruction_t * inst, decod_param_t * param)
	2782	// void instruction_lf_sfgt_d (decod_instruction_t * inst, decod_param_t * param)
	2783	// void instruction_lf_sfgt_s (decod_instruction_t * inst, decod_param_t * param)
	2784	// void instruction_lf_sfle_d (decod_instruction_t * inst, decod_param_t * param)
	2785	// void instruction_lf_sfle_s (decod_instruction_t * inst, decod_param_t * param)
	2786	// void instruction_lf_sflt_d (decod_instruction_t * inst, decod_param_t * param)
	2787	// void instruction_lf_sflt_s (decod_instruction_t * inst, decod_param_t * param)
	2788	// void instruction_lf_sfne_d (decod_instruction_t * inst, decod_param_t * param)
	2789	// void instruction_lf_sfne_s (decod_instruction_t * inst, decod_param_t * param)
	2790	// void instruction_lf_sub_d (decod_instruction_t * inst, decod_param_t * param)
	2791	// void instruction_lf_sub_s (decod_instruction_t * inst, decod_param_t * param)
	2792
	2793	// // ORVDX
	2794	// void instruction_lv_add_b (decod_instruction_t * inst, decod_param_t * param)
	2795	// void instruction_lv_add_h (decod_instruction_t * inst, decod_param_t * param)
	2796	// void instruction_lv_adds_b (decod_instruction_t * inst, decod_param_t * param)
	2797	// void instruction_lv_adds_h (decod_instruction_t * inst, decod_param_t * param)
	2798	// void instruction_lv_addu_b (decod_instruction_t * inst, decod_param_t * param)
	2799	// void instruction_lv_addu_h (decod_instruction_t * inst, decod_param_t * param)
	2800	// void instruction_lv_addus_b (decod_instruction_t * inst, decod_param_t * param)
	2801	// void instruction_lv_addus_h (decod_instruction_t * inst, decod_param_t * param)
	2802	// void instruction_lv_all_eq_b (decod_instruction_t * inst, decod_param_t * param)
	2803	// void instruction_lv_all_eq_h (decod_instruction_t * inst, decod_param_t * param)
	2804	// void instruction_lv_all_ge_b (decod_instruction_t * inst, decod_param_t * param)
	2805	// void instruction_lv_all_ge_h (decod_instruction_t * inst, decod_param_t * param)
	2806	// void instruction_lv_all_gt_b (decod_instruction_t * inst, decod_param_t * param)
	2807	// void instruction_lv_all_gt_h (decod_instruction_t * inst, decod_param_t * param)
	2808	// void instruction_lv_all_le_b (decod_instruction_t * inst, decod_param_t * param)
	2809	// void instruction_lv_all_le_h (decod_instruction_t * inst, decod_param_t * param)
	2810	// void instruction_lv_all_lt_b (decod_instruction_t * inst, decod_param_t * param)
	2811	// void instruction_lv_all_lt_h (decod_instruction_t * inst, decod_param_t * param)
	2812	// void instruction_lv_all_ne_b (decod_instruction_t * inst, decod_param_t * param)
	2813	// void instruction_lv_all_ne_h (decod_instruction_t * inst, decod_param_t * param)
	2814	// void instruction_lv_and (decod_instruction_t * inst, decod_param_t * param)
	2815	// void instruction_lv_any_eq_b (decod_instruction_t * inst, decod_param_t * param)
	2816	// void instruction_lv_any_eq_h (decod_instruction_t * inst, decod_param_t * param)
	2817	// void instruction_lv_any_ge_b (decod_instruction_t * inst, decod_param_t * param)
	2818	// void instruction_lv_any_ge_h (decod_instruction_t * inst, decod_param_t * param)
	2819	// void instruction_lv_any_gt_b (decod_instruction_t * inst, decod_param_t * param)
	2820	// void instruction_lv_any_gt_h (decod_instruction_t * inst, decod_param_t * param)
	2821	// void instruction_lv_any_le_b (decod_instruction_t * inst, decod_param_t * param)
	2822	// void instruction_lv_any_le_h (decod_instruction_t * inst, decod_param_t * param)
	2823	// void instruction_lv_any_lt_b (decod_instruction_t * inst, decod_param_t * param)
	2824	// void instruction_lv_any_lt_h (decod_instruction_t * inst, decod_param_t * param)
	2825	// void instruction_lv_any_ne_b (decod_instruction_t * inst, decod_param_t * param)
	2826	// void instruction_lv_any_ne_h (decod_instruction_t * inst, decod_param_t * param)
	2827	// void instruction_lv_avg_b (decod_instruction_t * inst, decod_param_t * param)
	2828	// void instruction_lv_avg_h (decod_instruction_t * inst, decod_param_t * param)
	2829	// void instruction_lv_cmp_eq_b (decod_instruction_t * inst, decod_param_t * param)
	2830	// void instruction_lv_cmp_eq_h (decod_instruction_t * inst, decod_param_t * param)
	2831	// void instruction_lv_cmp_ge_b (decod_instruction_t * inst, decod_param_t * param)
	2832	// void instruction_lv_cmp_ge_h (decod_instruction_t * inst, decod_param_t * param)
	2833	// void instruction_lv_cmp_gt_b (decod_instruction_t * inst, decod_param_t * param)
	2834	// void instruction_lv_cmp_gt_h (decod_instruction_t * inst, decod_param_t * param)
	2835	// void instruction_lv_cmp_le_b (decod_instruction_t * inst, decod_param_t * param)
	2836	// void instruction_lv_cmp_le_h (decod_instruction_t * inst, decod_param_t * param)
	2837	// void instruction_lv_cmp_lt_b (decod_instruction_t * inst, decod_param_t * param)
	2838	// void instruction_lv_cmp_lt_h (decod_instruction_t * inst, decod_param_t * param)
	2839	// void instruction_lv_cmp_ne_b (decod_instruction_t * inst, decod_param_t * param)
	2840	// void instruction_lv_cmp_ne_h (decod_instruction_t * inst, decod_param_t * param)
	2841	// void instruction_lv_cust1 (decod_instruction_t * inst, decod_param_t * param)
	2842	// void instruction_lv_cust2 (decod_instruction_t * inst, decod_param_t * param)
	2843	// void instruction_lv_cust3 (decod_instruction_t * inst, decod_param_t * param)
	2844	// void instruction_lv_cust4 (decod_instruction_t * inst, decod_param_t * param)
	2845	// void instruction_lv_madds_h (decod_instruction_t * inst, decod_param_t * param)
	2846	// void instruction_lv_max_b (decod_instruction_t * inst, decod_param_t * param)
	2847	// void instruction_lv_max_h (decod_instruction_t * inst, decod_param_t * param)
	2848	// void instruction_lv_merge_b (decod_instruction_t * inst, decod_param_t * param)
	2849	// void instruction_lv_merge_h (decod_instruction_t * inst, decod_param_t * param)
	2850	// void instruction_lv_min_b (decod_instruction_t * inst, decod_param_t * param)
	2851	// void instruction_lv_min_h (decod_instruction_t * inst, decod_param_t * param)
	2852	// void instruction_lv_msubs_h (decod_instruction_t * inst, decod_param_t * param)
	2853	// void instruction_lv_muls_h (decod_instruction_t * inst, decod_param_t * param)
	2854	// void instruction_lv_nand (decod_instruction_t * inst, decod_param_t * param)
	2855	// void instruction_lv_nor (decod_instruction_t * inst, decod_param_t * param)
	2856	// void instruction_lv_or (decod_instruction_t * inst, decod_param_t * param)
	2857	// void instruction_lv_pack_b (decod_instruction_t * inst, decod_param_t * param)
	2858	// void instruction_lv_pack_h (decod_instruction_t * inst, decod_param_t * param)
	2859	// void instruction_lv_packs_b (decod_instruction_t * inst, decod_param_t * param)
	2860	// void instruction_lv_packs_h (decod_instruction_t * inst, decod_param_t * param)
	2861	// void instruction_lv_packus_b (decod_instruction_t * inst, decod_param_t * param)
	2862	// void instruction_lv_packus_h (decod_instruction_t * inst, decod_param_t * param)
	2863	// void instruction_lv_perm_n (decod_instruction_t * inst, decod_param_t * param)
	2864	// void instruction_lv_rl_b (decod_instruction_t * inst, decod_param_t * param)
	2865	// void instruction_lv_rl_h (decod_instruction_t * inst, decod_param_t * param)
	2866	// void instruction_lv_sll (decod_instruction_t * inst, decod_param_t * param)
	2867	// void instruction_lv_sll_b (decod_instruction_t * inst, decod_param_t * param)
	2868	// void instruction_lv_sll_h (decod_instruction_t * inst, decod_param_t * param)
	2869	// void instruction_lv_sra_b (decod_instruction_t * inst, decod_param_t * param)
	2870	// void instruction_lv_sra_h (decod_instruction_t * inst, decod_param_t * param)
	2871	// void instruction_lv_srl (decod_instruction_t * inst, decod_param_t * param)
	2872	// void instruction_lv_srl_b (decod_instruction_t * inst, decod_param_t * param)
	2873	// void instruction_lv_srl_h (decod_instruction_t * inst, decod_param_t * param)
	2874	// void instruction_lv_sub_b (decod_instruction_t * inst, decod_param_t * param)
	2875	// void instruction_lv_sub_h (decod_instruction_t * inst, decod_param_t * param)
	2876	// void instruction_lv_subs_b (decod_instruction_t * inst, decod_param_t * param)
	2877	// void instruction_lv_subs_h (decod_instruction_t * inst, decod_param_t * param)
	2878	// void instruction_lv_subu_b (decod_instruction_t * inst, decod_param_t * param)
	2879	// void instruction_lv_subu_h (decod_instruction_t * inst, decod_param_t * param)
	2880	// void instruction_lv_subus_b (decod_instruction_t * inst, decod_param_t * param)
	2881	// void instruction_lv_subus_h (decod_instruction_t * inst, decod_param_t * param)
	2882	// void instruction_lv_unpack_b (decod_instruction_t * inst, decod_param_t * param)
	2883	// void instruction_lv_unpack_h (decod_instruction_t * inst, decod_param_t * param)
	2884	// void instruction_lv_xor (decod_instruction_t * inst, decod_param_t * param)
	2885
	2886	}; // end namespace decod
	2887	}; // end namespace decod_unit
	2888	}; // end namespace front_end
	2889	}; // end namespace multi_front_end
	2890	}; // end namespace core
	2891	}; // end namespace behavioural
	2892	}; // end namespace morpheo

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