[78] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * instruction MAC_UNIT (l.mac, l.maci, l.macrc, l.msb) throw a context event. Also is sequential. |
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| 7 | * If your program need intensive mac_unit, you can change the implementation of this unit : |
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| 8 | * 1) "decod" : inst->_event_type = EVENT_TYPE_NONE; |
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| 9 | * 2) "rename" : add component as load_store_unit pointer management |
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| 10 | * 3) "functionnal_unit" : test type instruction, if type=MAC_UNIT, insert in queue, the localisation is the ptr give by rename stage. Retire in this queue in sequence (as the store queue). |
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| 11 | * |
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| 12 | */ |
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| 13 | |
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| 14 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h" |
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| 15 | |
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| 16 | namespace morpheo { |
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| 17 | namespace behavioural { |
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| 18 | namespace core { |
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| 19 | namespace multi_front_end { |
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| 20 | namespace front_end { |
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| 21 | namespace decod_unit { |
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| 22 | namespace decod { |
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| 23 | |
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| 24 | #define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>(32, x,true ,nb_bits) |
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| 25 | #define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>(32, x,false,nb_bits) |
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| 26 | |
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| 27 | void instruction_decod (decod_instruction_t * inst, decod_param_t * param) |
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| 28 | { |
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| 29 | // instruction_decod_type_0 (inst,param); |
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| 30 | |
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| 31 | uint32_t opcod = range<uint32_t>(inst->_instruction,31,26); |
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| 32 | (* param->_function_decod[ 0][opcod]) (inst,param); |
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| 33 | } |
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| 34 | |
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| 35 | // void instruction_decod_type_0 (decod_instruction_t * inst, decod_param_t * param) |
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| 36 | // { |
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| 37 | // uint32_t opcod = range<uint32_t>(inst->_instruction,31,26); |
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| 38 | // (* param->_function_decod[ 0][opcod]) (inst,param); |
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| 39 | // } |
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| 40 | |
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| 41 | void instruction_decod_type_1 (decod_instruction_t * inst, decod_param_t * param) |
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| 42 | { |
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| 43 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); |
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| 44 | (* param->_function_decod[ 1][opcod]) (inst,param); |
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| 45 | } |
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| 46 | |
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| 47 | void instruction_decod_type_2 (decod_instruction_t * inst, decod_param_t * param) |
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| 48 | { |
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| 49 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); |
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| 50 | (* param->_function_decod[ 2][opcod]) (inst,param); |
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| 51 | } |
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| 52 | |
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| 53 | void instruction_decod_type_3 (decod_instruction_t * inst, decod_param_t * param) |
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| 54 | { |
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| 55 | uint32_t opcod = ((range<uint32_t>(inst->_instruction, 9, 8)<<4) | |
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| 56 | (range<uint32_t>(inst->_instruction, 3, 0))); |
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| 57 | (* param->_function_decod[ 3][opcod]) (inst,param); |
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| 58 | } |
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| 59 | |
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| 60 | void instruction_decod_type_4 (decod_instruction_t * inst, decod_param_t * param) |
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| 61 | { |
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| 62 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,21); |
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| 63 | (* param->_function_decod[ 4][opcod]) (inst,param); |
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| 64 | } |
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| 65 | |
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| 66 | void instruction_decod_type_5 (decod_instruction_t * inst, decod_param_t * param) |
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| 67 | { |
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| 68 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,21); |
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| 69 | (* param->_function_decod[ 5][opcod]) (inst,param); |
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| 70 | } |
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| 71 | |
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| 72 | void instruction_decod_type_6 (decod_instruction_t * inst, decod_param_t * param) |
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| 73 | { |
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| 74 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 75 | (* param->_function_decod[ 6][opcod]) (inst,param); |
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| 76 | } |
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| 77 | |
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| 78 | void instruction_decod_type_7 (decod_instruction_t * inst, decod_param_t * param) |
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| 79 | { |
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| 80 | uint32_t opcod = range<uint32_t>(inst->_instruction, 3, 0); |
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| 81 | (* param->_function_decod[ 7][opcod]) (inst,param); |
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| 82 | } |
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| 83 | |
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| 84 | void instruction_decod_type_8 (decod_instruction_t * inst, decod_param_t * param) |
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| 85 | { |
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| 86 | uint32_t opcod = range<uint32_t>(inst->_instruction,16,16); |
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| 87 | (* param->_function_decod[ 8][opcod]) (inst,param); |
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| 88 | } |
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| 89 | |
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| 90 | void instruction_decod_type_9 (decod_instruction_t * inst, decod_param_t * param) |
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| 91 | { |
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| 92 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,23); |
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| 93 | (* param->_function_decod[ 9][opcod]) (inst,param); |
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| 94 | } |
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| 95 | |
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| 96 | void instruction_decod_type_10 (decod_instruction_t * inst, decod_param_t * param) |
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| 97 | { |
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| 98 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,24); |
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| 99 | (* param->_function_decod[10][opcod]) (inst,param); |
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| 100 | } |
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| 101 | |
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| 102 | void instruction_decod_type_11 (decod_instruction_t * inst, decod_param_t * param) |
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| 103 | { |
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| 104 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 105 | (* param->_function_decod[11][opcod]) (inst,param); |
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| 106 | } |
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| 107 | |
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| 108 | void instruction_decod_type_12 (decod_instruction_t * inst, decod_param_t * param) |
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| 109 | { |
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| 110 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 111 | (* param->_function_decod[12][opcod]) (inst,param); |
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| 112 | } |
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| 113 | |
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| 114 | void instruction_decod_type_13 (decod_instruction_t * inst, decod_param_t * param) |
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| 115 | { |
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| 116 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 117 | (* param->_function_decod[13][opcod]) (inst,param); |
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| 118 | } |
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| 119 | |
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| 120 | void instruction_illegal (decod_instruction_t * inst, decod_param_t * param) |
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| 121 | { |
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| 122 | log_printf(TRACE,Decod,"instruction_illegal","instruction_illegal"); |
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| 123 | |
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| 124 | inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION; |
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| 125 | |
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| 126 | if (inst->_is_delay_slot) |
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| 127 | inst->_address_next = inst->_address_previous; |
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| 128 | else |
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| 129 | inst->_address_next = inst->_address; |
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| 130 | |
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| 131 | inst->_event_type = EVENT_TYPE_EXCEPTION; |
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| 132 | } |
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| 133 | |
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| 134 | // ORBIS |
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| 135 | void instruction_l_add (decod_instruction_t * inst, decod_param_t * param) |
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| 136 | { |
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| 137 | log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add"); |
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| 138 | inst->_type = TYPE_ALU; |
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| 139 | inst->_operation = OPERATION_ALU_L_ADD; |
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| 140 | inst->_has_immediat = 0; |
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| 141 | // inst->_immediat = ; |
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| 142 | inst->_read_ra = 1; |
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| 143 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 144 | inst->_read_rb = 1; |
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| 145 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
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| 146 | inst->_read_rc = 0; |
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| 147 | // inst->_num_reg_rc = ; |
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| 148 | inst->_write_rd = 1; |
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| 149 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 150 | inst->_write_re = 1; |
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| 151 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 152 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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| 153 | // inst->_branch_condition = ; |
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| 154 | // inst->_branch_stack_write = ; |
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| 155 | // inst->_branch_direction = ; |
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| 156 | // inst->_address_next = ; |
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| 157 | inst->_event_type = EVENT_TYPE_NONE; |
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| 158 | } |
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| 159 | |
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| 160 | void instruction_l_addc (decod_instruction_t * inst, decod_param_t * param) |
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| 161 | { |
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| 162 | log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc"); |
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| 163 | |
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| 164 | inst->_type = TYPE_ALU; |
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| 165 | inst->_operation = OPERATION_ALU_L_ADD; |
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| 166 | inst->_has_immediat = 0; |
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| 167 | // inst->_immediat = ; |
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| 168 | inst->_read_ra = 1; |
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| 169 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 170 | inst->_read_rb = 1; |
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| 171 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
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| 172 | inst->_read_rc = 1; |
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| 173 | inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; |
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| 174 | inst->_write_rd = 1; |
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| 175 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 176 | inst->_write_re = 1; |
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| 177 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 178 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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| 179 | // inst->_branch_condition = ; |
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| 180 | // inst->_branch_stack_write = ; |
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| 181 | // inst->_branch_direction = ; |
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| 182 | // inst->_address_next = ; |
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| 183 | inst->_event_type = EVENT_TYPE_NONE; |
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| 184 | } |
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| 185 | |
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| 186 | void instruction_l_addi (decod_instruction_t * inst, decod_param_t * param) |
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| 187 | { |
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| 188 | log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi"); |
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| 189 | |
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| 190 | inst->_type = TYPE_ALU; |
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| 191 | inst->_operation = OPERATION_ALU_L_ADD; |
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| 192 | inst->_has_immediat = 1; |
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| 193 | inst->_immediat = EXTENDS(inst->_instruction,16); |
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| 194 | inst->_read_ra = 1; |
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| 195 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 196 | inst->_read_rb = 0; |
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| 197 | // inst->_num_reg_rb = ; |
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| 198 | inst->_read_rc = 0; |
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| 199 | // inst->_num_reg_rc = ; |
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| 200 | inst->_write_rd = 1; |
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| 201 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 202 | inst->_write_re = 1; |
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| 203 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 204 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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| 205 | // inst->_branch_condition = ; |
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| 206 | // inst->_branch_stack_write = ; |
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| 207 | // inst->_branch_direction = ; |
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| 208 | // inst->_address_next = ; |
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| 209 | inst->_event_type = EVENT_TYPE_NONE; |
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| 210 | } |
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| 211 | |
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| 212 | void instruction_l_addic (decod_instruction_t * inst, decod_param_t * param) |
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| 213 | { |
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| 214 | log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic"); |
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| 215 | |
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| 216 | inst->_type = TYPE_ALU; |
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| 217 | inst->_operation = OPERATION_ALU_L_ADD; |
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| 218 | inst->_has_immediat = 1; |
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| 219 | inst->_immediat = EXTENDS(inst->_instruction,16); |
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| 220 | inst->_read_ra = 1; |
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| 221 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 222 | inst->_read_rb = 0; |
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| 223 | // inst->_num_reg_rb = ; |
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| 224 | inst->_read_rc = 1; |
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| 225 | inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; |
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| 226 | inst->_write_rd = 1; |
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| 227 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 228 | inst->_write_re = 1; |
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| 229 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 230 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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| 231 | // inst->_branch_condition = ; |
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| 232 | // inst->_branch_stack_write = ; |
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| 233 | // inst->_branch_direction = ; |
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| 234 | // inst->_address_next = ; |
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| 235 | inst->_event_type = EVENT_TYPE_NONE; |
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| 236 | } |
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| 237 | |
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| 238 | void instruction_l_and (decod_instruction_t * inst, decod_param_t * param) |
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| 239 | { |
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| 240 | log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and"); |
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| 241 | |
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| 242 | inst->_type = TYPE_ALU; |
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| 243 | inst->_operation = OPERATION_ALU_L_AND; |
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| 244 | inst->_has_immediat = 0; |
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| 245 | // inst->_immediat = ; |
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| 246 | inst->_read_ra = 1; |
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| 247 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 248 | inst->_read_rb = 1; |
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| 249 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
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| 250 | inst->_read_rc = 0; |
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| 251 | // inst->_num_reg_rc = ; |
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| 252 | inst->_write_rd = 1; |
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| 253 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 254 | inst->_write_re = 0; |
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| 255 | // inst->_num_reg_re = ; |
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| 256 | inst->_exception_use = EXCEPTION_USE_NONE; |
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| 257 | // inst->_branch_condition = ; |
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| 258 | // inst->_branch_stack_write = ; |
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| 259 | // inst->_branch_direction = ; |
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| 260 | // inst->_address_next = ; |
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| 261 | inst->_event_type = EVENT_TYPE_NONE; |
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| 262 | } |
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| 263 | |
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| 264 | void instruction_l_andi (decod_instruction_t * inst, decod_param_t * param) |
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| 265 | { |
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| 266 | log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi"); |
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| 267 | |
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| 268 | inst->_type = TYPE_ALU; |
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| 269 | inst->_operation = OPERATION_ALU_L_AND; |
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| 270 | inst->_has_immediat = 1; |
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| 271 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
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| 272 | inst->_read_ra = 1; |
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| 273 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 274 | inst->_read_rb = 0; |
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| 275 | // inst->_num_reg_rb = ; |
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| 276 | inst->_read_rc = 0; |
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| 277 | // inst->_num_reg_rc = ; |
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| 278 | inst->_write_rd = 1; |
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| 279 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 280 | inst->_write_re = 0; |
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| 281 | // inst->_num_reg_re = ; |
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| 282 | inst->_exception_use = EXCEPTION_USE_NONE; |
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| 283 | // inst->_branch_condition = ; |
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| 284 | // inst->_branch_stack_write = ; |
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| 285 | // inst->_branch_direction = ; |
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| 286 | // inst->_address_next = ; |
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| 287 | inst->_event_type = EVENT_TYPE_NONE; |
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| 288 | } |
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| 289 | |
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| 290 | void instruction_l_bf (decod_instruction_t * inst, decod_param_t * param) |
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| 291 | { |
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| 292 | log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf"); |
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| 293 | |
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| 294 | Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); |
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| 295 | |
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| 296 | inst->_type = TYPE_BRANCH; |
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| 297 | inst->_operation = OPERATION_BRANCH_L_TEST_F; |
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| 298 | inst->_has_immediat = 1; |
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| 299 | inst->_immediat = address_next; |
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| 300 | inst->_read_ra = 0; |
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| 301 | // inst->_num_reg_ra = ; |
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| 302 | inst->_read_rb = 0; |
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| 303 | // inst->_num_reg_rb = ; |
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| 304 | inst->_read_rc = 1; |
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| 305 | inst->_num_reg_rc = SPR_LOGIC_SR_F; |
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| 306 | inst->_write_rd = 0; |
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| 307 | // inst->_num_reg_rd = ; |
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| 308 | inst->_write_re = 0; |
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| 309 | // inst->_num_reg_re = ; |
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| 310 | inst->_exception_use = EXCEPTION_USE_NONE; |
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| 311 | inst->_branch_condition = BRANCH_CONDITION_FLAG_SET; |
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| 312 | // inst->_branch_stack_write = 0; |
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| 313 | |
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| 314 | inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25); |
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| 315 | inst->_address_next = address_next; |
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| 316 | inst->_event_type = EVENT_TYPE_NONE; |
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| 317 | } |
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| 318 | |
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| 319 | void instruction_l_bnf (decod_instruction_t * inst, decod_param_t * param) |
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| 320 | { |
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| 321 | log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf"); |
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| 322 | |
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| 323 | Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); |
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| 324 | |
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| 325 | inst->_type = TYPE_BRANCH; |
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| 326 | inst->_operation = OPERATION_BRANCH_L_TEST_NF; |
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| 327 | inst->_has_immediat = 1; |
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| 328 | inst->_immediat = address_next; |
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| 329 | inst->_read_ra = 0; |
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| 330 | // inst->_num_reg_ra = ; |
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| 331 | inst->_read_rb = 0; |
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| 332 | // inst->_num_reg_rb = ; |
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| 333 | inst->_read_rc = 1; |
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| 334 | inst->_num_reg_rc = SPR_LOGIC_SR_F; |
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| 335 | inst->_write_rd = 0; |
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| 336 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 337 | inst->_write_re = 0; |
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| 338 | // inst->_num_reg_re = ; |
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| 339 | inst->_exception_use = EXCEPTION_USE_NONE; |
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| 340 | inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET; |
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| 341 | // inst->_branch_stack_write = 0; |
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| 342 | inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25); |
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| 343 | inst->_address_next = address_next; |
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| 344 | inst->_event_type = EVENT_TYPE_NONE; |
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| 345 | } |
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| 346 | |
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| 347 | void instruction_l_cmov (decod_instruction_t * inst, decod_param_t * param) |
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| 348 | { |
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| 349 | log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov"); |
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| 350 | |
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| 351 | inst->_type = TYPE_MOVE; |
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| 352 | inst->_operation = OPERATION_MOVE_L_CMOV; |
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| 353 | inst->_has_immediat = 0; |
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| 354 | // inst->_immediat = ; |
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| 355 | inst->_read_ra = 1; |
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| 356 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 357 | inst->_read_rb = 1; |
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| 358 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
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| 359 | inst->_read_rc = 1; |
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| 360 | inst->_num_reg_rc = SPR_LOGIC_SR_F; |
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| 361 | inst->_write_rd = 1; |
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| 362 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 363 | inst->_write_re = 0; |
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| 364 | // inst->_num_reg_re = ; |
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| 365 | inst->_exception_use = EXCEPTION_USE_NONE; |
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| 366 | // inst->_branch_condition = ; |
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| 367 | // inst->_branch_stack_write = ; |
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| 368 | // inst->_branch_direction = ; |
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| 369 | // inst->_address_next = ; |
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| 370 | inst->_event_type = EVENT_TYPE_NONE; |
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| 371 | } |
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| 372 | |
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| 373 | void instruction_l_csync (decod_instruction_t * inst, decod_param_t * param) |
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| 374 | { |
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| 375 | log_printf(TRACE,Decod,"instruction_l_csync"," * instruction : l.csync"); |
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| 376 | |
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| 377 | if (range<Tinstruction_t>(inst->_instruction,23) != 0) |
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| 378 | { |
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| 379 | instruction_illegal (inst, param); |
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| 380 | } |
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| 381 | else |
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| 382 | { |
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| 383 | inst->_type = TYPE_SPECIAL; |
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| 384 | inst->_operation = OPERATION_SPECIAL_L_CSYNC; |
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| 385 | inst->_has_immediat = 0; |
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| 386 | // inst->_immediat = ; |
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| 387 | inst->_read_ra = 0; |
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| 388 | // inst->_num_reg_ra = ; |
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| 389 | inst->_read_rb = 0; |
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| 390 | // inst->_num_reg_rb = ; |
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| 391 | inst->_read_rc = 0; |
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| 392 | // inst->_num_reg_rc = ; |
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| 393 | inst->_write_rd = 0; |
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| 394 | // inst->_num_reg_rd = ; |
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| 395 | inst->_write_re = 0; |
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| 396 | // inst->_num_reg_re = ; |
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| 397 | inst->_exception_use = EXCEPTION_USE_NONE; |
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| 398 | // inst->_branch_condition = ; |
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| 399 | // inst->_branch_stack_write = ; |
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| 400 | // inst->_branch_direction = ; |
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| 401 | // inst->_address_next = ; // don't change |
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| 402 | inst->_event_type = EVENT_TYPE_CSYNC; |
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| 403 | } |
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| 404 | } |
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| 405 | |
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| 406 | // void instruction_l_cust1 (decod_instruction_t * inst, decod_param_t * param) |
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| 407 | // void instruction_l_cust2 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 408 | // void instruction_l_cust3 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 409 | // void instruction_l_cust4 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 410 | // void instruction_l_cust5 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 411 | // void instruction_l_cust6 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 412 | // void instruction_l_cust7 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 413 | // void instruction_l_cust8 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 414 | |
---|
| 415 | void instruction_l_div (decod_instruction_t * inst, decod_param_t * param) |
---|
| 416 | { |
---|
| 417 | log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div"); |
---|
| 418 | |
---|
| 419 | inst->_type = TYPE_MUL_DIV; |
---|
| 420 | inst->_operation = OPERATION_MUL_DIV_L_DIV; |
---|
| 421 | inst->_has_immediat = 0; |
---|
| 422 | // inst->_immediat = ; |
---|
| 423 | inst->_read_ra = 1; |
---|
| 424 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 425 | inst->_read_rb = 1; |
---|
| 426 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 427 | inst->_read_rc = 0; |
---|
| 428 | // inst->_num_reg_rc = ; |
---|
| 429 | inst->_write_rd = 1; |
---|
| 430 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 431 | inst->_write_re = 1; |
---|
| 432 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 433 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
| 434 | // inst->_branch_condition = ; |
---|
| 435 | // inst->_branch_stack_write = ; |
---|
| 436 | // inst->_branch_direction = ; |
---|
| 437 | // inst->_address_next = ; |
---|
| 438 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 439 | } |
---|
| 440 | |
---|
| 441 | void instruction_l_divu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 442 | { |
---|
| 443 | log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu"); |
---|
| 444 | |
---|
| 445 | inst->_type = TYPE_MUL_DIV; |
---|
| 446 | inst->_operation = OPERATION_MUL_DIV_L_DIVU; |
---|
| 447 | inst->_has_immediat = 0; |
---|
| 448 | // inst->_immediat = ; |
---|
| 449 | inst->_read_ra = 1; |
---|
| 450 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 451 | inst->_read_rb = 1; |
---|
| 452 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 453 | inst->_read_rc = 0; |
---|
| 454 | // inst->_num_reg_rc = ; |
---|
| 455 | inst->_write_rd = 1; |
---|
| 456 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 457 | inst->_write_re = 1; |
---|
| 458 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 459 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
| 460 | // inst->_branch_condition = ; |
---|
| 461 | // inst->_branch_stack_write = ; |
---|
| 462 | // inst->_branch_direction = ; |
---|
| 463 | // inst->_address_next = ; |
---|
| 464 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 465 | } |
---|
| 466 | |
---|
| 467 | void instruction_l_extbs (decod_instruction_t * inst, decod_param_t * param) |
---|
| 468 | { |
---|
| 469 | log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs"); |
---|
| 470 | |
---|
| 471 | inst->_type = TYPE_EXTEND; |
---|
| 472 | inst->_operation = OPERATION_EXTEND_L_EXTEND_S; |
---|
| 473 | inst->_has_immediat = 1; |
---|
| 474 | inst->_immediat = 8; |
---|
| 475 | inst->_read_ra = 1; |
---|
| 476 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 477 | inst->_read_rb = 0; |
---|
| 478 | // inst->_num_reg_rb = ; |
---|
| 479 | inst->_read_rc = 0; |
---|
| 480 | // inst->_num_reg_rc = ; |
---|
| 481 | inst->_write_rd = 1; |
---|
| 482 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 483 | inst->_write_re = 0; |
---|
| 484 | // inst->_num_reg_re = ; |
---|
| 485 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 486 | // inst->_branch_condition = ; |
---|
| 487 | // inst->_branch_stack_write = ; |
---|
| 488 | // inst->_branch_direction = ; |
---|
| 489 | // inst->_address_next = ; |
---|
| 490 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 491 | } |
---|
| 492 | |
---|
| 493 | void instruction_l_extbz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 494 | { |
---|
| 495 | log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz"); |
---|
| 496 | |
---|
| 497 | inst->_type = TYPE_EXTEND; |
---|
| 498 | inst->_operation = OPERATION_EXTEND_L_EXTEND_Z; |
---|
| 499 | inst->_has_immediat = 1; |
---|
| 500 | inst->_immediat = 8; |
---|
| 501 | inst->_read_ra = 1; |
---|
| 502 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 503 | inst->_read_rb = 0; |
---|
| 504 | // inst->_num_reg_rb = ; |
---|
| 505 | inst->_read_rc = 0; |
---|
| 506 | // inst->_num_reg_rc = ; |
---|
| 507 | inst->_write_rd = 1; |
---|
| 508 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 509 | inst->_write_re = 0; |
---|
| 510 | // inst->_num_reg_re = ; |
---|
| 511 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 512 | // inst->_branch_condition = ; |
---|
| 513 | // inst->_branch_stack_write = ; |
---|
| 514 | // inst->_branch_direction = ; |
---|
| 515 | // inst->_address_next = ; |
---|
| 516 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 517 | } |
---|
| 518 | |
---|
| 519 | void instruction_l_exths (decod_instruction_t * inst, decod_param_t * param) |
---|
| 520 | { |
---|
| 521 | log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths"); |
---|
| 522 | |
---|
| 523 | inst->_type = TYPE_EXTEND; |
---|
| 524 | inst->_operation = OPERATION_EXTEND_L_EXTEND_S; |
---|
| 525 | inst->_has_immediat = 1; |
---|
| 526 | inst->_immediat = 16; |
---|
| 527 | inst->_read_ra = 1; |
---|
| 528 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 529 | inst->_read_rb = 0; |
---|
| 530 | // inst->_num_reg_rb = ; |
---|
| 531 | inst->_read_rc = 0; |
---|
| 532 | // inst->_num_reg_rc = ; |
---|
| 533 | inst->_write_rd = 1; |
---|
| 534 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 535 | inst->_write_re = 0; |
---|
| 536 | // inst->_num_reg_re = ; |
---|
| 537 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 538 | // inst->_branch_condition = ; |
---|
| 539 | // inst->_branch_stack_write = ; |
---|
| 540 | // inst->_branch_direction = ; |
---|
| 541 | // inst->_address_next = ; |
---|
| 542 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 543 | } |
---|
| 544 | |
---|
| 545 | void instruction_l_exthz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 546 | { |
---|
| 547 | log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz"); |
---|
| 548 | |
---|
| 549 | inst->_type = TYPE_EXTEND; |
---|
| 550 | inst->_operation = OPERATION_EXTEND_L_EXTEND_Z; |
---|
| 551 | inst->_has_immediat = 1; |
---|
| 552 | inst->_immediat = 16; |
---|
| 553 | inst->_read_ra = 1; |
---|
| 554 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 555 | inst->_read_rb = 0; |
---|
| 556 | // inst->_num_reg_rb = ; |
---|
| 557 | inst->_read_rc = 0; |
---|
| 558 | // inst->_num_reg_rc = ; |
---|
| 559 | inst->_write_rd = 1; |
---|
| 560 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 561 | inst->_write_re = 0; |
---|
| 562 | // inst->_num_reg_re = ; |
---|
| 563 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 564 | // inst->_branch_condition = ; |
---|
| 565 | // inst->_branch_stack_write = ; |
---|
| 566 | // inst->_branch_direction = ; |
---|
| 567 | // inst->_address_next = ; |
---|
| 568 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 569 | } |
---|
| 570 | |
---|
| 571 | void instruction_l_extws (decod_instruction_t * inst, decod_param_t * param) |
---|
| 572 | { |
---|
| 573 | log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws"); |
---|
| 574 | |
---|
| 575 | inst->_type = TYPE_EXTEND; |
---|
| 576 | inst->_operation = OPERATION_EXTEND_L_EXTEND_S; |
---|
| 577 | inst->_has_immediat = 1; |
---|
| 578 | inst->_immediat = 32; |
---|
| 579 | inst->_read_ra = 1; |
---|
| 580 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 581 | inst->_read_rb = 0; |
---|
| 582 | // inst->_num_reg_rb = ; |
---|
| 583 | inst->_read_rc = 0; |
---|
| 584 | // inst->_num_reg_rc = ; |
---|
| 585 | inst->_write_rd = 1; |
---|
| 586 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 587 | inst->_write_re = 0; |
---|
| 588 | // inst->_num_reg_re = ; |
---|
| 589 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 590 | // inst->_branch_condition = ; |
---|
| 591 | // inst->_branch_stack_write = ; |
---|
| 592 | // inst->_branch_direction = ; |
---|
| 593 | // inst->_address_next = ; |
---|
| 594 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 595 | } |
---|
| 596 | |
---|
| 597 | void instruction_l_extwz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 598 | { |
---|
| 599 | log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz"); |
---|
| 600 | |
---|
| 601 | inst->_type = TYPE_EXTEND; |
---|
| 602 | inst->_operation = OPERATION_EXTEND_L_EXTEND_Z; |
---|
| 603 | inst->_has_immediat = 1; |
---|
| 604 | inst->_immediat = 32; |
---|
| 605 | inst->_read_ra = 1; |
---|
| 606 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 607 | inst->_read_rb = 0; |
---|
| 608 | // inst->_num_reg_rb = ; |
---|
| 609 | inst->_read_rc = 0; |
---|
| 610 | // inst->_num_reg_rc = ; |
---|
| 611 | inst->_write_rd = 1; |
---|
| 612 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 613 | inst->_write_re = 0; |
---|
| 614 | // inst->_num_reg_re = ; |
---|
| 615 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 616 | // inst->_branch_condition = ; |
---|
| 617 | // inst->_branch_stack_write = ; |
---|
| 618 | // inst->_branch_direction = ; |
---|
| 619 | // inst->_address_next = ; |
---|
| 620 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 621 | } |
---|
| 622 | |
---|
| 623 | void instruction_l_ff1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 624 | { |
---|
| 625 | log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1"); |
---|
| 626 | |
---|
| 627 | inst->_type = TYPE_FIND; |
---|
| 628 | inst->_operation = OPERATION_FIND_L_FF1; |
---|
| 629 | inst->_has_immediat = 0; |
---|
| 630 | // inst->_immediat = ; |
---|
| 631 | inst->_read_ra = 1; |
---|
| 632 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 633 | inst->_read_rb = 0; |
---|
| 634 | // inst->_num_reg_rb = ; |
---|
| 635 | inst->_read_rc = 0; |
---|
| 636 | // inst->_num_reg_rc = ; |
---|
| 637 | inst->_write_rd = 1; |
---|
| 638 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 639 | inst->_write_re = 0; |
---|
| 640 | // inst->_num_reg_re = ; |
---|
| 641 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 642 | // inst->_branch_condition = ; |
---|
| 643 | // inst->_branch_stack_write = ; |
---|
| 644 | // inst->_branch_direction = ; |
---|
| 645 | // inst->_address_next = ; |
---|
| 646 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 647 | } |
---|
| 648 | |
---|
| 649 | void instruction_l_fl1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 650 | { |
---|
| 651 | log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1"); |
---|
| 652 | |
---|
| 653 | inst->_type = TYPE_FIND; |
---|
| 654 | inst->_operation = OPERATION_FIND_L_FL1; |
---|
| 655 | inst->_has_immediat = 0; |
---|
| 656 | // inst->_immediat = ; |
---|
| 657 | inst->_read_ra = 1; |
---|
| 658 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 659 | inst->_read_rb = 0; |
---|
| 660 | // inst->_num_reg_rb = ; |
---|
| 661 | inst->_read_rc = 0; |
---|
| 662 | // inst->_num_reg_rc = ; |
---|
| 663 | inst->_write_rd = 1; |
---|
| 664 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 665 | inst->_write_re = 0; |
---|
| 666 | // inst->_num_reg_re = ; |
---|
| 667 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 668 | // inst->_branch_condition = ; |
---|
| 669 | // inst->_branch_stack_write = ; |
---|
| 670 | // inst->_branch_direction = ; |
---|
| 671 | // inst->_address_next = ; |
---|
| 672 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 673 | } |
---|
| 674 | |
---|
| 675 | void instruction_l_j (decod_instruction_t * inst, decod_param_t * param) |
---|
| 676 | { |
---|
| 677 | log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j"); |
---|
| 678 | |
---|
| 679 | inst->_type = TYPE_BRANCH; |
---|
| 680 | inst->_operation = OPERATION_BRANCH_NONE; |
---|
| 681 | inst->_has_immediat = 0; |
---|
| 682 | // inst->_immediat = ; |
---|
| 683 | inst->_read_ra = 0; |
---|
| 684 | // inst->_num_reg_ra = ; |
---|
| 685 | inst->_read_rb = 0; |
---|
| 686 | // inst->_num_reg_rb = ; |
---|
| 687 | inst->_read_rc = 0; |
---|
| 688 | // inst->_num_reg_rc = ; |
---|
| 689 | inst->_write_rd = 0; |
---|
| 690 | // inst->_num_reg_rd = ; |
---|
| 691 | inst->_write_re = 0; |
---|
| 692 | // inst->_num_reg_re = ; |
---|
| 693 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 694 | inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK; |
---|
| 695 | // inst->_branch_stack_write = 0; |
---|
| 696 | inst->_branch_direction = 1; |
---|
| 697 | inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); |
---|
| 698 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 699 | } |
---|
| 700 | |
---|
| 701 | void instruction_l_jal (decod_instruction_t * inst, decod_param_t * param) |
---|
| 702 | { |
---|
| 703 | log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal"); |
---|
| 704 | |
---|
| 705 | inst->_type = TYPE_BRANCH; |
---|
| 706 | inst->_operation = OPERATION_BRANCH_L_JALR; |
---|
| 707 | inst->_has_immediat = 1; |
---|
| 708 | inst->_immediat = inst->_address_next+4; |
---|
| 709 | inst->_read_ra = 0; |
---|
| 710 | // inst->_num_reg_ra = ; |
---|
| 711 | inst->_read_rb = 0; |
---|
| 712 | // inst->_num_reg_rb = ; |
---|
| 713 | inst->_read_rc = 0; |
---|
| 714 | // inst->_num_reg_rc = ; |
---|
| 715 | inst->_write_rd = 1; |
---|
| 716 | inst->_num_reg_rd = 9; // Link register |
---|
| 717 | inst->_write_re = 0; |
---|
| 718 | // inst->_num_reg_re = ; |
---|
| 719 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 720 | inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump |
---|
| 721 | // inst->_branch_stack_write = 1; |
---|
| 722 | inst->_branch_direction = 1; |
---|
| 723 | inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); |
---|
| 724 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 725 | } |
---|
| 726 | |
---|
| 727 | void instruction_l_jalr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 728 | { |
---|
| 729 | log_printf(TRACE,Decod,"instruction_l_jalr"," * instruction : l.jalr"); |
---|
| 730 | |
---|
| 731 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 732 | |
---|
| 733 | if (inst->_num_reg_rb == 9) |
---|
| 734 | { |
---|
| 735 | instruction_illegal (inst, param); |
---|
| 736 | } |
---|
| 737 | else |
---|
| 738 | { |
---|
| 739 | inst->_type = TYPE_BRANCH; |
---|
| 740 | inst->_operation = OPERATION_BRANCH_L_JALR; |
---|
| 741 | inst->_has_immediat = 0; |
---|
| 742 | // inst->_immediat = ; |
---|
| 743 | inst->_read_ra = 0; |
---|
| 744 | // inst->_num_reg_ra = ; |
---|
| 745 | inst->_read_rb = 1; |
---|
| 746 | // inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 747 | inst->_read_rc = 0; |
---|
| 748 | // inst->_num_reg_rc = ; |
---|
| 749 | inst->_write_rd = 1; |
---|
| 750 | inst->_num_reg_rd = 9; // Link register |
---|
| 751 | inst->_write_re = 0; |
---|
| 752 | // inst->_num_reg_re = ; |
---|
| 753 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 754 | // inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER; |
---|
| 755 | inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK; |
---|
| 756 | // inst->_branch_stack_write = 1; |
---|
| 757 | inst->_branch_direction = 1; |
---|
| 758 | // inst->_address_next = ; |
---|
| 759 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 760 | } |
---|
| 761 | } |
---|
| 762 | |
---|
| 763 | void instruction_l_jr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 764 | { |
---|
| 765 | log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr"); |
---|
| 766 | |
---|
| 767 | inst->_type = TYPE_BRANCH; |
---|
| 768 | inst->_operation = OPERATION_BRANCH_L_JALR; |
---|
| 769 | inst->_has_immediat = 0; |
---|
| 770 | // inst->_immediat = ; |
---|
| 771 | inst->_read_ra = 0; |
---|
| 772 | // inst->_num_reg_ra = ; |
---|
| 773 | inst->_read_rb = 1; |
---|
| 774 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 775 | inst->_read_rc = 0; |
---|
| 776 | // inst->_num_reg_rc = ; |
---|
| 777 | inst->_write_rd = 0; |
---|
| 778 | // inst->_num_reg_rd = ; |
---|
| 779 | inst->_write_re = 0; |
---|
| 780 | // inst->_num_reg_re = ; |
---|
| 781 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 782 | inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK; |
---|
| 783 | // inst->_branch_stack_write = 0; |
---|
| 784 | inst->_branch_direction = 1; |
---|
| 785 | // inst->_address_next = ; |
---|
| 786 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 787 | } |
---|
| 788 | |
---|
| 789 | void instruction_l_lbs (decod_instruction_t * inst, decod_param_t * param) |
---|
| 790 | { |
---|
| 791 | log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs"); |
---|
| 792 | |
---|
| 793 | inst->_type = TYPE_MEMORY; |
---|
| 794 | inst->_operation = OPERATION_MEMORY_LOAD_8_S; |
---|
| 795 | inst->_has_immediat = 1; |
---|
| 796 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 797 | inst->_read_ra = 1; |
---|
| 798 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 799 | inst->_read_rb = 0; |
---|
| 800 | // inst->_num_reg_rb = ; |
---|
| 801 | inst->_read_rc = 0; |
---|
| 802 | // inst->_num_reg_rc = ; |
---|
| 803 | inst->_write_rd = 1; |
---|
| 804 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 805 | inst->_write_re = 0; |
---|
| 806 | // inst->_num_reg_re = ; |
---|
| 807 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; |
---|
| 808 | // inst->_branch_condition = ; |
---|
| 809 | // inst->_branch_stack_write = ; |
---|
| 810 | // inst->_branch_direction = ; |
---|
| 811 | // inst->_address_next = ; |
---|
| 812 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 813 | } |
---|
| 814 | |
---|
| 815 | void instruction_l_lbz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 816 | { |
---|
| 817 | log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz"); |
---|
| 818 | |
---|
| 819 | inst->_type = TYPE_MEMORY; |
---|
| 820 | inst->_operation = OPERATION_MEMORY_LOAD_8_Z; |
---|
| 821 | inst->_has_immediat = 1; |
---|
| 822 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 823 | inst->_read_ra = 1; |
---|
| 824 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 825 | inst->_read_rb = 0; |
---|
| 826 | // inst->_num_reg_rb = ; |
---|
| 827 | inst->_read_rc = 0; |
---|
| 828 | // inst->_num_reg_rc = ; |
---|
| 829 | inst->_write_rd = 1; |
---|
| 830 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 831 | inst->_write_re = 0; |
---|
| 832 | // inst->_num_reg_re = ; |
---|
| 833 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; |
---|
| 834 | // inst->_branch_condition = ; |
---|
| 835 | // inst->_branch_stack_write = ; |
---|
| 836 | // inst->_branch_direction = ; |
---|
| 837 | // inst->_address_next = ; |
---|
| 838 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 839 | } |
---|
| 840 | |
---|
| 841 | void instruction_l_ld (decod_instruction_t * inst, decod_param_t * param) |
---|
| 842 | { |
---|
| 843 | log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld"); |
---|
| 844 | |
---|
| 845 | inst->_type = TYPE_MEMORY; |
---|
| 846 | inst->_operation = OPERATION_MEMORY_LOAD_64_S; |
---|
| 847 | inst->_has_immediat = 1; |
---|
| 848 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 849 | inst->_read_ra = 1; |
---|
| 850 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 851 | inst->_read_rb = 0; |
---|
| 852 | // inst->_num_reg_rb = ; |
---|
| 853 | inst->_read_rc = 0; |
---|
| 854 | // inst->_num_reg_rc = ; |
---|
| 855 | inst->_write_rd = 1; |
---|
| 856 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 857 | inst->_write_re = 0; |
---|
| 858 | // inst->_num_reg_re = ; |
---|
| 859 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 860 | // inst->_branch_condition = ; |
---|
| 861 | // inst->_branch_stack_write = ; |
---|
| 862 | // inst->_branch_direction = ; |
---|
| 863 | // inst->_address_next = ; |
---|
| 864 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 865 | } |
---|
| 866 | |
---|
| 867 | void instruction_l_lhs (decod_instruction_t * inst, decod_param_t * param) |
---|
| 868 | { |
---|
| 869 | log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs"); |
---|
| 870 | |
---|
| 871 | inst->_type = TYPE_MEMORY; |
---|
| 872 | inst->_operation = OPERATION_MEMORY_LOAD_16_S; |
---|
| 873 | inst->_has_immediat = 1; |
---|
| 874 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 875 | inst->_read_ra = 1; |
---|
| 876 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 877 | inst->_read_rb = 0; |
---|
| 878 | // inst->_num_reg_rb = ; |
---|
| 879 | inst->_read_rc = 0; |
---|
| 880 | // inst->_num_reg_rc = ; |
---|
| 881 | inst->_write_rd = 1; |
---|
| 882 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 883 | inst->_write_re = 0; |
---|
| 884 | // inst->_num_reg_re = ; |
---|
| 885 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 886 | // inst->_branch_condition = ; |
---|
| 887 | // inst->_branch_stack_write = ; |
---|
| 888 | // inst->_branch_direction = ; |
---|
| 889 | // inst->_address_next = ; |
---|
| 890 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 891 | } |
---|
| 892 | |
---|
| 893 | void instruction_l_lhz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 894 | { |
---|
| 895 | log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz"); |
---|
| 896 | |
---|
| 897 | inst->_type = TYPE_MEMORY; |
---|
| 898 | inst->_operation = OPERATION_MEMORY_LOAD_16_Z; |
---|
| 899 | inst->_has_immediat = 1; |
---|
| 900 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 901 | inst->_read_ra = 1; |
---|
| 902 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 903 | inst->_read_rb = 0; |
---|
| 904 | // inst->_num_reg_rb = ; |
---|
| 905 | inst->_read_rc = 0; |
---|
| 906 | // inst->_num_reg_rc = ; |
---|
| 907 | inst->_write_rd = 1; |
---|
| 908 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 909 | inst->_write_re = 0; |
---|
| 910 | // inst->_num_reg_re = ; |
---|
| 911 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 912 | // inst->_branch_condition = ; |
---|
| 913 | // inst->_branch_stack_write = ; |
---|
| 914 | // inst->_branch_direction = ; |
---|
| 915 | // inst->_address_next = ; |
---|
| 916 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 917 | } |
---|
| 918 | |
---|
| 919 | void instruction_l_lws (decod_instruction_t * inst, decod_param_t * param) |
---|
| 920 | { |
---|
| 921 | log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws"); |
---|
| 922 | |
---|
| 923 | inst->_type = TYPE_MEMORY; |
---|
| 924 | inst->_operation = OPERATION_MEMORY_LOAD_32_S; |
---|
| 925 | inst->_has_immediat = 1; |
---|
| 926 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 927 | inst->_read_ra = 1; |
---|
| 928 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 929 | inst->_read_rb = 0; |
---|
| 930 | // inst->_num_reg_rb = ; |
---|
| 931 | inst->_read_rc = 0; |
---|
| 932 | // inst->_num_reg_rc = ; |
---|
| 933 | inst->_write_rd = 1; |
---|
| 934 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 935 | inst->_write_re = 0; |
---|
| 936 | // inst->_num_reg_re = ; |
---|
| 937 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 938 | // inst->_branch_condition = ; |
---|
| 939 | // inst->_branch_stack_write = ; |
---|
| 940 | // inst->_branch_direction = ; |
---|
| 941 | // inst->_address_next = ; |
---|
| 942 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 943 | } |
---|
| 944 | |
---|
| 945 | void instruction_l_lwz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 946 | { |
---|
| 947 | log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz"); |
---|
| 948 | |
---|
| 949 | inst->_type = TYPE_MEMORY; |
---|
| 950 | inst->_operation = OPERATION_MEMORY_LOAD_32_Z; |
---|
| 951 | inst->_has_immediat = 1; |
---|
| 952 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 953 | inst->_read_ra = 1; |
---|
| 954 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 955 | inst->_read_rb = 0; |
---|
| 956 | // inst->_num_reg_rb = ; |
---|
| 957 | inst->_read_rc = 0; |
---|
| 958 | // inst->_num_reg_rc = ; |
---|
| 959 | inst->_write_rd = 1; |
---|
| 960 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 961 | inst->_write_re = 0; |
---|
| 962 | // inst->_num_reg_re = ; |
---|
| 963 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 964 | // inst->_branch_condition = ; |
---|
| 965 | // inst->_branch_stack_write = ; |
---|
| 966 | // inst->_branch_direction = ; |
---|
| 967 | // inst->_address_next = ; |
---|
| 968 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 969 | } |
---|
| 970 | |
---|
| 971 | void instruction_l_mac (decod_instruction_t * inst, decod_param_t * param) |
---|
| 972 | { |
---|
| 973 | log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac"); |
---|
| 974 | |
---|
| 975 | inst->_type = TYPE_SPECIAL; |
---|
| 976 | inst->_operation = OPERATION_SPECIAL_L_MAC; |
---|
| 977 | inst->_has_immediat = 0; |
---|
| 978 | // inst->_immediat = ; |
---|
| 979 | inst->_read_ra = 1; |
---|
| 980 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 981 | inst->_read_rb = 1; |
---|
| 982 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 983 | inst->_read_rc = 0; |
---|
| 984 | // inst->_num_reg_rc = ; |
---|
| 985 | inst->_write_rd = 0; |
---|
| 986 | // inst->_num_reg_rd = ; |
---|
| 987 | inst->_write_re = 0; |
---|
| 988 | // inst->_num_reg_re = ; |
---|
| 989 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 990 | // inst->_branch_condition = ; |
---|
| 991 | // inst->_branch_stack_write = ; |
---|
| 992 | // inst->_branch_direction = ; |
---|
| 993 | // inst->_address_next = ; // don't change |
---|
| 994 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 995 | } |
---|
| 996 | |
---|
| 997 | void instruction_l_maci (decod_instruction_t * inst, decod_param_t * param) |
---|
| 998 | { |
---|
| 999 | log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci"); |
---|
| 1000 | |
---|
| 1001 | inst->_type = TYPE_SPECIAL; |
---|
| 1002 | inst->_operation = OPERATION_SPECIAL_L_MAC; |
---|
| 1003 | inst->_has_immediat = 1; |
---|
| 1004 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1005 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1006 | inst->_read_ra = 1; |
---|
| 1007 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1008 | inst->_read_rb = 0; |
---|
| 1009 | // inst->_num_reg_rb = ; |
---|
| 1010 | inst->_read_rc = 0; |
---|
| 1011 | // inst->_num_reg_rc = ; |
---|
| 1012 | inst->_write_rd = 0; |
---|
| 1013 | // inst->_num_reg_rd = ; |
---|
| 1014 | inst->_write_re = 0; |
---|
| 1015 | // inst->_num_reg_re = ; |
---|
| 1016 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1017 | // inst->_branch_condition = ; |
---|
| 1018 | // inst->_branch_stack_write = ; |
---|
| 1019 | // inst->_branch_direction = ; |
---|
| 1020 | // inst->_address_next = ; // don't change |
---|
| 1021 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1022 | } |
---|
| 1023 | |
---|
| 1024 | void instruction_l_macrc (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1025 | { |
---|
| 1026 | log_printf(TRACE,Decod,"instruction_l_macrc"," * instruction : l.macrc"); |
---|
| 1027 | |
---|
| 1028 | if (range<uint32_t>(inst->_instruction,15, 0) != 0) |
---|
| 1029 | { |
---|
| 1030 | instruction_illegal (inst, param); |
---|
| 1031 | } |
---|
| 1032 | else |
---|
| 1033 | { |
---|
| 1034 | inst->_type = TYPE_SPECIAL; |
---|
| 1035 | inst->_operation = OPERATION_SPECIAL_L_MACRC; |
---|
| 1036 | inst->_has_immediat = 0; |
---|
| 1037 | // inst->_immediat = ; |
---|
| 1038 | inst->_read_ra = 0; |
---|
| 1039 | // inst->_num_reg_ra = ; |
---|
| 1040 | inst->_read_rb = 0; |
---|
| 1041 | // inst->_num_reg_rb = ; |
---|
| 1042 | inst->_read_rc = 0; |
---|
| 1043 | // inst->_num_reg_rc = ; |
---|
| 1044 | inst->_write_rd = 1; |
---|
| 1045 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1046 | inst->_write_re = 0; |
---|
| 1047 | // inst->_num_reg_re = ; |
---|
| 1048 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1049 | // inst->_branch_condition = ; |
---|
| 1050 | // inst->_branch_stack_write = ; |
---|
| 1051 | // inst->_branch_direction = ; |
---|
| 1052 | // inst->_address_next = ; // don't change |
---|
| 1053 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1054 | } |
---|
| 1055 | } |
---|
| 1056 | |
---|
| 1057 | void instruction_l_mfspr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1058 | { |
---|
| 1059 | log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr"); |
---|
| 1060 | |
---|
| 1061 | inst->_type = TYPE_SPECIAL; |
---|
| 1062 | inst->_operation = OPERATION_SPECIAL_L_MFSPR; |
---|
| 1063 | inst->_has_immediat = 1; |
---|
| 1064 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1065 | inst->_read_ra = 1; |
---|
| 1066 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1067 | inst->_read_rb = 0; |
---|
| 1068 | // inst->_num_reg_rb = ; |
---|
| 1069 | inst->_read_rc = 0; |
---|
| 1070 | // inst->_num_reg_rc = ; |
---|
| 1071 | inst->_write_rd = 1; |
---|
| 1072 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1073 | inst->_write_re = 0; |
---|
| 1074 | // inst->_num_reg_re = ; |
---|
| 1075 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1076 | // inst->_branch_condition = ; |
---|
| 1077 | // inst->_branch_stack_write = ; |
---|
| 1078 | // inst->_branch_direction = ; |
---|
| 1079 | // inst->_address_next = ; // don't change |
---|
| 1080 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1081 | } |
---|
| 1082 | |
---|
| 1083 | void instruction_l_movhi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1084 | { |
---|
| 1085 | log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi"); |
---|
| 1086 | |
---|
| 1087 | inst->_type = TYPE_MOVE; |
---|
| 1088 | inst->_operation = OPERATION_MOVE_L_MOVHI; |
---|
| 1089 | inst->_has_immediat = 1; |
---|
| 1090 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1091 | inst->_read_ra = 0; |
---|
| 1092 | // inst->_num_reg_ra = ; |
---|
| 1093 | inst->_read_rb = 0; |
---|
| 1094 | // inst->_num_reg_rb = ; |
---|
| 1095 | inst->_read_rc = 0; |
---|
| 1096 | // inst->_num_reg_rc = ; |
---|
| 1097 | inst->_write_rd = 1; |
---|
| 1098 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1099 | inst->_write_re = 0; |
---|
| 1100 | // inst->_num_reg_re = ; |
---|
| 1101 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1102 | // inst->_branch_condition = ; |
---|
| 1103 | // inst->_branch_stack_write = ; |
---|
| 1104 | // inst->_branch_direction = ; |
---|
| 1105 | // inst->_address_next = ; |
---|
| 1106 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1107 | } |
---|
| 1108 | |
---|
| 1109 | void instruction_l_msb (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1110 | { |
---|
| 1111 | log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb"); |
---|
| 1112 | |
---|
| 1113 | inst->_type = TYPE_SPECIAL; |
---|
| 1114 | inst->_operation = OPERATION_SPECIAL_L_MSB; |
---|
| 1115 | inst->_has_immediat = 0; |
---|
| 1116 | // inst->_immediat = ; |
---|
| 1117 | inst->_read_ra = 1; |
---|
| 1118 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1119 | inst->_read_rb = 1; |
---|
| 1120 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1121 | inst->_read_rc = 0; |
---|
| 1122 | // inst->_num_reg_rc = ; |
---|
| 1123 | inst->_write_rd = 0; |
---|
| 1124 | // inst->_num_reg_rd = ; |
---|
| 1125 | inst->_write_re = 0; |
---|
| 1126 | // inst->_num_reg_re = ; |
---|
| 1127 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1128 | // inst->_branch_condition = ; |
---|
| 1129 | // inst->_branch_stack_write = ; |
---|
| 1130 | // inst->_branch_direction = ; |
---|
| 1131 | // inst->_address_next = ; // don't change |
---|
| 1132 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1133 | } |
---|
| 1134 | |
---|
| 1135 | void instruction_l_msync (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1136 | { |
---|
| 1137 | log_printf(TRACE,Decod,"instruction_l_msync"," * instruction : l.msync"); |
---|
| 1138 | |
---|
| 1139 | if (range<uint32_t>(inst->_instruction,22, 0) != 0) |
---|
| 1140 | { |
---|
| 1141 | instruction_illegal (inst, param); |
---|
| 1142 | } |
---|
| 1143 | else |
---|
| 1144 | { |
---|
| 1145 | inst->_type = TYPE_SPECIAL; |
---|
| 1146 | inst->_operation = OPERATION_SPECIAL_L_MSYNC; |
---|
| 1147 | inst->_has_immediat = 0; |
---|
| 1148 | // inst->_immediat = ; |
---|
| 1149 | inst->_read_ra = 0; |
---|
| 1150 | // inst->_num_reg_ra = ; |
---|
| 1151 | inst->_read_rb = 0; |
---|
| 1152 | // inst->_num_reg_rb = ; |
---|
| 1153 | inst->_read_rc = 0; |
---|
| 1154 | // inst->_num_reg_rc = ; |
---|
| 1155 | inst->_write_rd = 0; |
---|
| 1156 | // inst->_num_reg_rd = ; |
---|
| 1157 | inst->_write_re = 0; |
---|
| 1158 | // inst->_num_reg_re = ; |
---|
| 1159 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1160 | // inst->_branch_condition = ; |
---|
| 1161 | // inst->_branch_stack_write = ; |
---|
| 1162 | // inst->_branch_direction = ; |
---|
| 1163 | // inst->_address_next = ; // don't change |
---|
| 1164 | inst->_event_type = EVENT_TYPE_MSYNC; |
---|
| 1165 | } |
---|
| 1166 | } |
---|
| 1167 | |
---|
| 1168 | void instruction_l_mtspr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1169 | { |
---|
| 1170 | log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr"); |
---|
| 1171 | |
---|
| 1172 | inst->_type = TYPE_SPECIAL; |
---|
| 1173 | inst->_operation = OPERATION_SPECIAL_L_MTSPR; |
---|
| 1174 | inst->_has_immediat = 1; |
---|
| 1175 | inst->_immediat = EXTENDZ(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1176 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1177 | inst->_read_ra = 1; |
---|
| 1178 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1179 | inst->_read_rb = 1; |
---|
| 1180 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1181 | inst->_read_rc = 0; |
---|
| 1182 | // inst->_num_reg_rc = ; |
---|
| 1183 | inst->_write_rd = 0; |
---|
| 1184 | // inst->_num_reg_rd = ; |
---|
| 1185 | inst->_write_re = 0; |
---|
| 1186 | // inst->_num_reg_re = ; |
---|
| 1187 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1188 | // inst->_branch_condition = ; |
---|
| 1189 | // inst->_branch_stack_write = ; |
---|
| 1190 | // inst->_branch_direction = ; |
---|
| 1191 | // inst->_address_next = ; // don't change |
---|
| 1192 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1193 | } |
---|
| 1194 | |
---|
| 1195 | void instruction_l_mul (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1196 | { |
---|
| 1197 | log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul"); |
---|
| 1198 | |
---|
| 1199 | inst->_type = TYPE_MUL_DIV; |
---|
| 1200 | inst->_operation = OPERATION_MUL_DIV_L_MUL; |
---|
| 1201 | inst->_has_immediat = 0; |
---|
| 1202 | // inst->_immediat = ; |
---|
| 1203 | inst->_read_ra = 1; |
---|
| 1204 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1205 | inst->_read_rb = 1; |
---|
| 1206 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1207 | inst->_read_rc = 0; |
---|
| 1208 | // inst->_num_reg_rc = ; |
---|
| 1209 | inst->_write_rd = 1; |
---|
| 1210 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1211 | inst->_write_re = 1; |
---|
| 1212 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 1213 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
| 1214 | // inst->_branch_condition = ; |
---|
| 1215 | // inst->_branch_stack_write = ; |
---|
| 1216 | // inst->_branch_direction = ; |
---|
| 1217 | // inst->_address_next = ; |
---|
| 1218 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1219 | } |
---|
| 1220 | |
---|
| 1221 | void instruction_l_muli (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1222 | { |
---|
| 1223 | log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli"); |
---|
| 1224 | |
---|
| 1225 | inst->_type = TYPE_MUL_DIV; |
---|
| 1226 | inst->_operation = OPERATION_MUL_DIV_L_MUL; |
---|
| 1227 | inst->_has_immediat = 1; |
---|
| 1228 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1229 | inst->_read_ra = 1; |
---|
| 1230 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1231 | inst->_read_rb = 0; |
---|
| 1232 | // inst->_num_reg_rb = ; |
---|
| 1233 | inst->_read_rc = 0; |
---|
| 1234 | // inst->_num_reg_rc = ; |
---|
| 1235 | inst->_write_rd = 1; |
---|
| 1236 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1237 | inst->_write_re = 1; |
---|
| 1238 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 1239 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
| 1240 | // inst->_branch_condition = ; |
---|
| 1241 | // inst->_branch_stack_write = ; |
---|
| 1242 | // inst->_branch_direction = ; |
---|
| 1243 | // inst->_address_next = ; |
---|
| 1244 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1245 | } |
---|
| 1246 | |
---|
| 1247 | void instruction_l_mulu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1248 | { |
---|
| 1249 | log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu"); |
---|
| 1250 | |
---|
| 1251 | inst->_type = TYPE_MUL_DIV; |
---|
| 1252 | inst->_operation = OPERATION_MUL_DIV_L_MULU; |
---|
| 1253 | inst->_has_immediat = 0; |
---|
| 1254 | // inst->_immediat = ; |
---|
| 1255 | inst->_read_ra = 1; |
---|
| 1256 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1257 | inst->_read_rb = 1; |
---|
| 1258 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1259 | inst->_read_rc = 0; |
---|
| 1260 | // inst->_num_reg_rc = ; |
---|
| 1261 | inst->_write_rd = 1; |
---|
| 1262 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1263 | inst->_write_re = 1; |
---|
| 1264 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 1265 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
| 1266 | // inst->_branch_condition = ; |
---|
| 1267 | // inst->_branch_stack_write = ; |
---|
| 1268 | // inst->_branch_direction = ; |
---|
| 1269 | // inst->_address_next = ; |
---|
| 1270 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1271 | } |
---|
| 1272 | |
---|
| 1273 | void instruction_l_nop (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1274 | { |
---|
| 1275 | log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop"); |
---|
| 1276 | |
---|
| 1277 | inst->_type = TYPE_SPECIAL; |
---|
| 1278 | inst->_operation = OPERATION_SPECIAL_L_NOP; |
---|
| 1279 | // inst->_has_immediat = 1; |
---|
| 1280 | // inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1281 | inst->_has_immediat = 0; |
---|
| 1282 | // inst->_immediat = ; |
---|
| 1283 | inst->_read_ra = 0; |
---|
| 1284 | // inst->_num_reg_ra = ; |
---|
| 1285 | inst->_read_rb = 0; |
---|
| 1286 | // inst->_num_reg_rb = ; |
---|
| 1287 | inst->_read_rc = 0; |
---|
| 1288 | // inst->_num_reg_rc = ; |
---|
| 1289 | inst->_write_rd = 0; |
---|
| 1290 | // inst->_num_reg_rd = ; |
---|
| 1291 | inst->_write_re = 0; |
---|
| 1292 | // inst->_num_reg_re = ; |
---|
| 1293 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1294 | // inst->_branch_condition = ; |
---|
| 1295 | // inst->_branch_stack_write = ; |
---|
| 1296 | // inst->_branch_direction = ; |
---|
| 1297 | // inst->_address_next = ; |
---|
| 1298 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1299 | } |
---|
| 1300 | |
---|
| 1301 | void instruction_l_or (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1302 | { |
---|
| 1303 | log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or"); |
---|
| 1304 | |
---|
| 1305 | inst->_type = TYPE_ALU; |
---|
| 1306 | inst->_operation = OPERATION_ALU_L_OR; |
---|
| 1307 | inst->_has_immediat = 0; |
---|
| 1308 | // inst->_immediat = ; |
---|
| 1309 | inst->_read_ra = 1; |
---|
| 1310 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1311 | inst->_read_rb = 1; |
---|
| 1312 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1313 | inst->_read_rc = 0; |
---|
| 1314 | // inst->_num_reg_rc = ; |
---|
| 1315 | inst->_write_rd = 1; |
---|
| 1316 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1317 | inst->_write_re = 0; |
---|
| 1318 | // inst->_num_reg_re = ; |
---|
| 1319 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1320 | // inst->_branch_condition = ; |
---|
| 1321 | // inst->_branch_stack_write = ; |
---|
| 1322 | // inst->_branch_direction = ; |
---|
| 1323 | // inst->_address_next = ; |
---|
| 1324 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1325 | } |
---|
| 1326 | |
---|
| 1327 | void instruction_l_ori (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1328 | { |
---|
| 1329 | log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori"); |
---|
| 1330 | |
---|
| 1331 | inst->_type = TYPE_ALU; |
---|
| 1332 | inst->_operation = OPERATION_ALU_L_OR; |
---|
| 1333 | inst->_has_immediat = 1; |
---|
| 1334 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1335 | inst->_read_ra = 1; |
---|
| 1336 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1337 | inst->_read_rb = 0; |
---|
| 1338 | // inst->_num_reg_rb = ; |
---|
| 1339 | inst->_read_rc = 0; |
---|
| 1340 | // inst->_num_reg_rc = ; |
---|
| 1341 | inst->_write_rd = 1; |
---|
| 1342 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1343 | inst->_write_re = 0; |
---|
| 1344 | // inst->_num_reg_re = ; |
---|
| 1345 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1346 | // inst->_branch_condition = ; |
---|
| 1347 | // inst->_branch_stack_write = ; |
---|
| 1348 | // inst->_branch_direction = ; |
---|
| 1349 | // inst->_address_next = ; |
---|
| 1350 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1351 | } |
---|
| 1352 | |
---|
| 1353 | void instruction_l_psync (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1354 | { |
---|
| 1355 | log_printf(TRACE,Decod,"instruction_l_psync"," * instruction : l.psync"); |
---|
| 1356 | |
---|
| 1357 | if (range<uint32_t>(inst->_instruction,22, 0) != 0) |
---|
| 1358 | { |
---|
| 1359 | instruction_illegal (inst, param); |
---|
| 1360 | } |
---|
| 1361 | else |
---|
| 1362 | { |
---|
| 1363 | inst->_type = TYPE_SPECIAL; |
---|
| 1364 | inst->_operation = OPERATION_SPECIAL_L_PSYNC; |
---|
| 1365 | inst->_has_immediat = 0; |
---|
| 1366 | // inst->_immediat = ; |
---|
| 1367 | inst->_read_ra = 0; |
---|
| 1368 | // inst->_num_reg_ra = ; |
---|
| 1369 | inst->_read_rb = 0; |
---|
| 1370 | // inst->_num_reg_rb = ; |
---|
| 1371 | inst->_read_rc = 0; |
---|
| 1372 | // inst->_num_reg_rc = ; |
---|
| 1373 | inst->_write_rd = 0; |
---|
| 1374 | // inst->_num_reg_rd = ; |
---|
| 1375 | inst->_write_re = 0; |
---|
| 1376 | // inst->_num_reg_re = ; |
---|
| 1377 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1378 | // inst->_branch_condition = ; |
---|
| 1379 | // inst->_branch_stack_write = ; |
---|
| 1380 | // inst->_branch_direction = ; |
---|
| 1381 | // inst->_address_next = ; // don't change |
---|
| 1382 | inst->_event_type = EVENT_TYPE_PSYNC; |
---|
| 1383 | } |
---|
| 1384 | } |
---|
| 1385 | |
---|
| 1386 | void instruction_l_rfe (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1387 | { |
---|
| 1388 | log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe"); |
---|
| 1389 | |
---|
| 1390 | inst->_type = TYPE_SPECIAL; |
---|
| 1391 | inst->_operation = OPERATION_SPECIAL_L_RFE; |
---|
| 1392 | inst->_has_immediat = 0; |
---|
| 1393 | // inst->_immediat = ; |
---|
| 1394 | inst->_read_ra = 0; |
---|
| 1395 | // inst->_num_reg_ra = ; |
---|
| 1396 | inst->_read_rb = 0; |
---|
| 1397 | // inst->_num_reg_rb = ; |
---|
| 1398 | inst->_read_rc = 0; |
---|
| 1399 | // inst->_num_reg_rc = ; |
---|
| 1400 | inst->_write_rd = 0; |
---|
| 1401 | // inst->_num_reg_rd = ; |
---|
| 1402 | inst->_write_re = 0; |
---|
| 1403 | // inst->_num_reg_re = ; |
---|
| 1404 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1405 | // inst->_branch_condition = ; |
---|
| 1406 | // inst->_branch_stack_write = ; |
---|
| 1407 | // inst->_branch_direction = ; |
---|
| 1408 | // inst->_address_next = ; // don't change |
---|
| 1409 | inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage |
---|
| 1410 | } |
---|
| 1411 | |
---|
| 1412 | void instruction_l_ror (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1413 | { |
---|
| 1414 | log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror"); |
---|
| 1415 | |
---|
| 1416 | inst->_type = TYPE_SHIFT; |
---|
| 1417 | inst->_operation = OPERATION_SHIFT_L_ROR; |
---|
| 1418 | inst->_has_immediat = 0; |
---|
| 1419 | // inst->_immediat = ; |
---|
| 1420 | inst->_read_ra = 1; |
---|
| 1421 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1422 | inst->_read_rb = 1; |
---|
| 1423 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1424 | inst->_read_rc = 0; |
---|
| 1425 | // inst->_num_reg_rc = ; |
---|
| 1426 | inst->_write_rd = 1; |
---|
| 1427 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1428 | inst->_write_re = 0; |
---|
| 1429 | // inst->_num_reg_re = ; |
---|
| 1430 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1431 | // inst->_branch_condition = ; |
---|
| 1432 | // inst->_branch_stack_write = ; |
---|
| 1433 | // inst->_branch_direction = ; |
---|
| 1434 | // inst->_address_next = ; |
---|
| 1435 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1436 | } |
---|
| 1437 | |
---|
| 1438 | void instruction_l_rori (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1439 | { |
---|
| 1440 | log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori"); |
---|
| 1441 | |
---|
| 1442 | inst->_type = TYPE_SHIFT; |
---|
| 1443 | inst->_operation = OPERATION_SHIFT_L_ROR; |
---|
| 1444 | inst->_has_immediat = 1; |
---|
| 1445 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 1446 | inst->_read_ra = 1; |
---|
| 1447 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1448 | inst->_read_rb = 0; |
---|
| 1449 | // inst->_num_reg_rb = ; |
---|
| 1450 | inst->_read_rc = 0; |
---|
| 1451 | // inst->_num_reg_rc = ; |
---|
| 1452 | inst->_write_rd = 1; |
---|
| 1453 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1454 | inst->_write_re = 0; |
---|
| 1455 | // inst->_num_reg_re = ; |
---|
| 1456 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1457 | // inst->_branch_condition = ; |
---|
| 1458 | // inst->_branch_stack_write = ; |
---|
| 1459 | // inst->_branch_direction = ; |
---|
| 1460 | // inst->_address_next = ; |
---|
| 1461 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1462 | } |
---|
| 1463 | |
---|
| 1464 | void instruction_l_sb (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1465 | { |
---|
| 1466 | log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); |
---|
| 1467 | |
---|
| 1468 | inst->_type = TYPE_MEMORY; |
---|
| 1469 | inst->_operation = OPERATION_MEMORY_STORE_8; |
---|
| 1470 | inst->_has_immediat = 1; |
---|
| 1471 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1472 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1473 | inst->_read_ra = 1; |
---|
| 1474 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1475 | inst->_read_rb = 1; |
---|
| 1476 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1477 | inst->_read_rc = 0; |
---|
| 1478 | // inst->_num_reg_rc = ; |
---|
| 1479 | inst->_write_rd = 0; |
---|
| 1480 | // inst->_num_reg_rd = ; |
---|
| 1481 | inst->_write_re = 0; |
---|
| 1482 | // inst->_num_reg_re = ; |
---|
| 1483 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; |
---|
| 1484 | // inst->_branch_condition = ; |
---|
| 1485 | // inst->_branch_stack_write = ; |
---|
| 1486 | // inst->_branch_direction = ; |
---|
| 1487 | // inst->_address_next = ; |
---|
| 1488 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1489 | } |
---|
| 1490 | |
---|
| 1491 | void instruction_l_sd (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1492 | { |
---|
| 1493 | log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); |
---|
| 1494 | |
---|
| 1495 | inst->_type = TYPE_MEMORY; |
---|
| 1496 | inst->_operation = OPERATION_MEMORY_STORE_64; |
---|
| 1497 | inst->_has_immediat = 1; |
---|
| 1498 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1499 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1500 | inst->_read_ra = 1; |
---|
| 1501 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1502 | inst->_read_rb = 1; |
---|
| 1503 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1504 | inst->_read_rc = 0; |
---|
| 1505 | // inst->_num_reg_rc = ; |
---|
| 1506 | inst->_write_rd = 0; |
---|
| 1507 | // inst->_num_reg_rd = ; |
---|
| 1508 | inst->_write_re = 0; |
---|
| 1509 | // inst->_num_reg_re = ; |
---|
| 1510 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 1511 | // inst->_branch_condition = ; |
---|
| 1512 | // inst->_branch_stack_write = ; |
---|
| 1513 | // inst->_branch_direction = ; |
---|
| 1514 | // inst->_address_next = ; |
---|
| 1515 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1516 | } |
---|
| 1517 | |
---|
| 1518 | void instruction_l_sfeq (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1519 | { |
---|
| 1520 | log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq"); |
---|
| 1521 | |
---|
| 1522 | inst->_type = TYPE_TEST; |
---|
| 1523 | inst->_operation = OPERATION_TEST_L_SFEQ; |
---|
| 1524 | inst->_has_immediat = 0; |
---|
| 1525 | // inst->_immediat = ; |
---|
| 1526 | inst->_read_ra = 1; |
---|
| 1527 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1528 | inst->_read_rb = 1; |
---|
| 1529 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1530 | inst->_read_rc = 0; |
---|
| 1531 | // inst->_num_reg_rc = ; |
---|
| 1532 | inst->_write_rd = 0; |
---|
| 1533 | // inst->_num_reg_rd = ; |
---|
| 1534 | inst->_write_re = 1; |
---|
| 1535 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1536 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1537 | // inst->_branch_condition = ; |
---|
| 1538 | // inst->_branch_stack_write = ; |
---|
| 1539 | // inst->_branch_direction = ; |
---|
| 1540 | // inst->_address_next = ; |
---|
| 1541 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1542 | } |
---|
| 1543 | |
---|
| 1544 | void instruction_l_sfeqi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1545 | { |
---|
| 1546 | log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi"); |
---|
| 1547 | |
---|
| 1548 | inst->_type = TYPE_TEST; |
---|
| 1549 | inst->_operation = OPERATION_TEST_L_SFEQ; |
---|
| 1550 | inst->_has_immediat = 1; |
---|
| 1551 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1552 | inst->_read_ra = 1; |
---|
| 1553 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1554 | inst->_read_rb = 0; |
---|
| 1555 | // inst->_num_reg_rb = ; |
---|
| 1556 | inst->_read_rc = 0; |
---|
| 1557 | // inst->_num_reg_rc = ; |
---|
| 1558 | inst->_write_rd = 0; |
---|
| 1559 | // inst->_num_reg_rd = ; |
---|
| 1560 | inst->_write_re = 1; |
---|
| 1561 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1562 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1563 | // inst->_branch_condition = ; |
---|
| 1564 | // inst->_branch_stack_write = ; |
---|
| 1565 | // inst->_branch_direction = ; |
---|
| 1566 | // inst->_address_next = ; |
---|
| 1567 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1568 | } |
---|
| 1569 | |
---|
| 1570 | void instruction_l_sfges (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1571 | { |
---|
| 1572 | log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges"); |
---|
| 1573 | |
---|
| 1574 | inst->_type = TYPE_TEST; |
---|
| 1575 | inst->_operation = OPERATION_TEST_L_SFGES; |
---|
| 1576 | inst->_has_immediat = 0; |
---|
| 1577 | // inst->_immediat = ; |
---|
| 1578 | inst->_read_ra = 1; |
---|
| 1579 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1580 | inst->_read_rb = 1; |
---|
| 1581 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1582 | inst->_read_rc = 0; |
---|
| 1583 | // inst->_num_reg_rc = ; |
---|
| 1584 | inst->_write_rd = 0; |
---|
| 1585 | // inst->_num_reg_rd = ; |
---|
| 1586 | inst->_write_re = 1; |
---|
| 1587 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1588 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1589 | // inst->_branch_condition = ; |
---|
| 1590 | // inst->_branch_stack_write = ; |
---|
| 1591 | // inst->_branch_direction = ; |
---|
| 1592 | // inst->_address_next = ; |
---|
| 1593 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1594 | } |
---|
| 1595 | |
---|
| 1596 | void instruction_l_sfgesi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1597 | { |
---|
| 1598 | log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi"); |
---|
| 1599 | |
---|
| 1600 | inst->_type = TYPE_TEST; |
---|
| 1601 | inst->_operation = OPERATION_TEST_L_SFGES; |
---|
| 1602 | inst->_has_immediat = 1; |
---|
| 1603 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1604 | inst->_read_ra = 1; |
---|
| 1605 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1606 | inst->_read_rb = 0; |
---|
| 1607 | // inst->_num_reg_rb = ; |
---|
| 1608 | inst->_read_rc = 0; |
---|
| 1609 | // inst->_num_reg_rc = ; |
---|
| 1610 | inst->_write_rd = 0; |
---|
| 1611 | // inst->_num_reg_rd = ; |
---|
| 1612 | inst->_write_re = 1; |
---|
| 1613 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1614 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1615 | // inst->_branch_condition = ; |
---|
| 1616 | // inst->_branch_stack_write = ; |
---|
| 1617 | // inst->_branch_direction = ; |
---|
| 1618 | // inst->_address_next = ; |
---|
| 1619 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1620 | } |
---|
| 1621 | |
---|
| 1622 | void instruction_l_sfgeu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1623 | { |
---|
| 1624 | log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu"); |
---|
| 1625 | |
---|
| 1626 | inst->_type = TYPE_TEST; |
---|
| 1627 | inst->_operation = OPERATION_TEST_L_SFGEU; |
---|
| 1628 | inst->_has_immediat = 0; |
---|
| 1629 | // inst->_immediat = ; |
---|
| 1630 | inst->_read_ra = 1; |
---|
| 1631 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1632 | inst->_read_rb = 1; |
---|
| 1633 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1634 | inst->_read_rc = 0; |
---|
| 1635 | // inst->_num_reg_rc = ; |
---|
| 1636 | inst->_write_rd = 0; |
---|
| 1637 | // inst->_num_reg_rd = ; |
---|
| 1638 | inst->_write_re = 1; |
---|
| 1639 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1640 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1641 | // inst->_branch_condition = ; |
---|
| 1642 | // inst->_branch_stack_write = ; |
---|
| 1643 | // inst->_branch_direction = ; |
---|
| 1644 | // inst->_address_next = ; |
---|
| 1645 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1646 | } |
---|
| 1647 | |
---|
| 1648 | void instruction_l_sfgeui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1649 | { |
---|
| 1650 | log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui"); |
---|
| 1651 | |
---|
| 1652 | inst->_type = TYPE_TEST; |
---|
| 1653 | inst->_operation = OPERATION_TEST_L_SFGEU; |
---|
| 1654 | inst->_has_immediat = 1; |
---|
| 1655 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1656 | inst->_read_ra = 1; |
---|
| 1657 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1658 | inst->_read_rb = 0; |
---|
| 1659 | // inst->_num_reg_rb = ; |
---|
| 1660 | inst->_read_rc = 0; |
---|
| 1661 | // inst->_num_reg_rc = ; |
---|
| 1662 | inst->_write_rd = 0; |
---|
| 1663 | // inst->_num_reg_rd = ; |
---|
| 1664 | inst->_write_re = 1; |
---|
| 1665 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1666 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1667 | // inst->_branch_condition = ; |
---|
| 1668 | // inst->_branch_stack_write = ; |
---|
| 1669 | // inst->_branch_direction = ; |
---|
| 1670 | // inst->_address_next = ; |
---|
| 1671 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1672 | } |
---|
| 1673 | |
---|
| 1674 | void instruction_l_sfgts (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1675 | { |
---|
| 1676 | log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts"); |
---|
| 1677 | |
---|
| 1678 | inst->_type = TYPE_TEST; |
---|
| 1679 | inst->_operation = OPERATION_TEST_L_SFGTS; |
---|
| 1680 | inst->_has_immediat = 0; |
---|
| 1681 | // inst->_immediat = ; |
---|
| 1682 | inst->_read_ra = 1; |
---|
| 1683 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1684 | inst->_read_rb = 1; |
---|
| 1685 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1686 | inst->_read_rc = 0; |
---|
| 1687 | // inst->_num_reg_rc = ; |
---|
| 1688 | inst->_write_rd = 0; |
---|
| 1689 | // inst->_num_reg_rd = ; |
---|
| 1690 | inst->_write_re = 1; |
---|
| 1691 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1692 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1693 | // inst->_branch_condition = ; |
---|
| 1694 | // inst->_branch_stack_write = ; |
---|
| 1695 | // inst->_branch_direction = ; |
---|
| 1696 | // inst->_address_next = ; |
---|
| 1697 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1698 | } |
---|
| 1699 | |
---|
| 1700 | void instruction_l_sfgtsi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1701 | { |
---|
| 1702 | log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi"); |
---|
| 1703 | |
---|
| 1704 | inst->_type = TYPE_TEST; |
---|
| 1705 | inst->_operation = OPERATION_TEST_L_SFGTS; |
---|
| 1706 | inst->_has_immediat = 1; |
---|
| 1707 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1708 | inst->_read_ra = 1; |
---|
| 1709 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1710 | inst->_read_rb = 0; |
---|
| 1711 | // inst->_num_reg_rb = ; |
---|
| 1712 | inst->_read_rc = 0; |
---|
| 1713 | // inst->_num_reg_rc = ; |
---|
| 1714 | inst->_write_rd = 0; |
---|
| 1715 | // inst->_num_reg_rd = ; |
---|
| 1716 | inst->_write_re = 1; |
---|
| 1717 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1718 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1719 | // inst->_branch_condition = ; |
---|
| 1720 | // inst->_branch_stack_write = ; |
---|
| 1721 | // inst->_branch_direction = ; |
---|
| 1722 | // inst->_address_next = ; |
---|
| 1723 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1724 | } |
---|
| 1725 | |
---|
| 1726 | void instruction_l_sfgtu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1727 | { |
---|
| 1728 | log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu"); |
---|
| 1729 | |
---|
| 1730 | inst->_type = TYPE_TEST; |
---|
| 1731 | inst->_operation = OPERATION_TEST_L_SFGTU; |
---|
| 1732 | inst->_has_immediat = 0; |
---|
| 1733 | // inst->_immediat = ; |
---|
| 1734 | inst->_read_ra = 1; |
---|
| 1735 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1736 | inst->_read_rb = 1; |
---|
| 1737 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1738 | inst->_read_rc = 0; |
---|
| 1739 | // inst->_num_reg_rc = ; |
---|
| 1740 | inst->_write_rd = 0; |
---|
| 1741 | // inst->_num_reg_rd = ; |
---|
| 1742 | inst->_write_re = 1; |
---|
| 1743 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1744 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1745 | // inst->_branch_condition = ; |
---|
| 1746 | // inst->_branch_stack_write = ; |
---|
| 1747 | // inst->_branch_direction = ; |
---|
| 1748 | // inst->_address_next = ; |
---|
| 1749 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1750 | } |
---|
| 1751 | |
---|
| 1752 | void instruction_l_sfgtui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1753 | { |
---|
| 1754 | log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui"); |
---|
| 1755 | |
---|
| 1756 | inst->_type = TYPE_TEST; |
---|
| 1757 | inst->_operation = OPERATION_TEST_L_SFGTU; |
---|
| 1758 | inst->_has_immediat = 1; |
---|
| 1759 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1760 | inst->_read_ra = 1; |
---|
| 1761 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1762 | inst->_read_rb = 0; |
---|
| 1763 | // inst->_num_reg_rb = ; |
---|
| 1764 | inst->_read_rc = 0; |
---|
| 1765 | // inst->_num_reg_rc = ; |
---|
| 1766 | inst->_write_rd = 0; |
---|
| 1767 | // inst->_num_reg_rd = ; |
---|
| 1768 | inst->_write_re = 1; |
---|
| 1769 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1770 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1771 | // inst->_branch_condition = ; |
---|
| 1772 | // inst->_branch_stack_write = ; |
---|
| 1773 | // inst->_branch_direction = ; |
---|
| 1774 | // inst->_address_next = ; |
---|
| 1775 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1776 | } |
---|
| 1777 | |
---|
| 1778 | void instruction_l_sfles (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1779 | { |
---|
| 1780 | log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles"); |
---|
| 1781 | |
---|
| 1782 | inst->_type = TYPE_TEST; |
---|
| 1783 | inst->_operation = OPERATION_TEST_L_SFLES; |
---|
| 1784 | inst->_has_immediat = 0; |
---|
| 1785 | // inst->_immediat = ; |
---|
| 1786 | inst->_read_ra = 1; |
---|
| 1787 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1788 | inst->_read_rb = 1; |
---|
| 1789 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1790 | inst->_read_rc = 0; |
---|
| 1791 | // inst->_num_reg_rc = ; |
---|
| 1792 | inst->_write_rd = 0; |
---|
| 1793 | // inst->_num_reg_rd = ; |
---|
| 1794 | inst->_write_re = 1; |
---|
| 1795 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1796 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1797 | // inst->_branch_condition = ; |
---|
| 1798 | // inst->_branch_stack_write = ; |
---|
| 1799 | // inst->_branch_direction = ; |
---|
| 1800 | // inst->_address_next = ; |
---|
| 1801 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1802 | } |
---|
| 1803 | |
---|
| 1804 | void instruction_l_sflesi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1805 | { |
---|
| 1806 | log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi"); |
---|
| 1807 | |
---|
| 1808 | inst->_type = TYPE_TEST; |
---|
| 1809 | inst->_operation = OPERATION_TEST_L_SFLES; |
---|
| 1810 | inst->_has_immediat = 1; |
---|
| 1811 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1812 | inst->_read_ra = 1; |
---|
| 1813 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1814 | inst->_read_rb = 0; |
---|
| 1815 | // inst->_num_reg_rb = ; |
---|
| 1816 | inst->_read_rc = 0; |
---|
| 1817 | // inst->_num_reg_rc = ; |
---|
| 1818 | inst->_write_rd = 0; |
---|
| 1819 | // inst->_num_reg_rd = ; |
---|
| 1820 | inst->_write_re = 1; |
---|
| 1821 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1822 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1823 | // inst->_branch_condition = ; |
---|
| 1824 | // inst->_branch_stack_write = ; |
---|
| 1825 | // inst->_branch_direction = ; |
---|
| 1826 | // inst->_address_next = ; |
---|
| 1827 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1828 | } |
---|
| 1829 | |
---|
| 1830 | void instruction_l_sfleu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1831 | { |
---|
| 1832 | log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu"); |
---|
| 1833 | |
---|
| 1834 | inst->_type = TYPE_TEST; |
---|
| 1835 | inst->_operation = OPERATION_TEST_L_SFLEU; |
---|
| 1836 | inst->_has_immediat = 0; |
---|
| 1837 | // inst->_immediat = ; |
---|
| 1838 | inst->_read_ra = 1; |
---|
| 1839 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1840 | inst->_read_rb = 1; |
---|
| 1841 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1842 | inst->_read_rc = 0; |
---|
| 1843 | // inst->_num_reg_rc = ; |
---|
| 1844 | inst->_write_rd = 0; |
---|
| 1845 | // inst->_num_reg_rd = ; |
---|
| 1846 | inst->_write_re = 1; |
---|
| 1847 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1848 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1849 | // inst->_branch_condition = ; |
---|
| 1850 | // inst->_branch_stack_write = ; |
---|
| 1851 | // inst->_branch_direction = ; |
---|
| 1852 | // inst->_address_next = ; |
---|
| 1853 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1854 | } |
---|
| 1855 | |
---|
| 1856 | void instruction_l_sfleui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1857 | { |
---|
| 1858 | log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui"); |
---|
| 1859 | |
---|
| 1860 | inst->_type = TYPE_TEST; |
---|
| 1861 | inst->_operation = OPERATION_TEST_L_SFLEU; |
---|
| 1862 | inst->_has_immediat = 1; |
---|
| 1863 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1864 | inst->_read_ra = 1; |
---|
| 1865 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1866 | inst->_read_rb = 0; |
---|
| 1867 | // inst->_num_reg_rb = ; |
---|
| 1868 | inst->_read_rc = 0; |
---|
| 1869 | // inst->_num_reg_rc = ; |
---|
| 1870 | inst->_write_rd = 0; |
---|
| 1871 | // inst->_num_reg_rd = ; |
---|
| 1872 | inst->_write_re = 1; |
---|
| 1873 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1874 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1875 | // inst->_branch_condition = ; |
---|
| 1876 | // inst->_branch_stack_write = ; |
---|
| 1877 | // inst->_branch_direction = ; |
---|
| 1878 | // inst->_address_next = ; |
---|
| 1879 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1880 | } |
---|
| 1881 | |
---|
| 1882 | void instruction_l_sflts (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1883 | { |
---|
| 1884 | log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts"); |
---|
| 1885 | |
---|
| 1886 | inst->_type = TYPE_TEST; |
---|
| 1887 | inst->_operation = OPERATION_TEST_L_SFLTS; |
---|
| 1888 | inst->_has_immediat = 0; |
---|
| 1889 | // inst->_immediat = ; |
---|
| 1890 | inst->_read_ra = 1; |
---|
| 1891 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1892 | inst->_read_rb = 1; |
---|
| 1893 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1894 | inst->_read_rc = 0; |
---|
| 1895 | // inst->_num_reg_rc = ; |
---|
| 1896 | inst->_write_rd = 0; |
---|
| 1897 | // inst->_num_reg_rd = ; |
---|
| 1898 | inst->_write_re = 1; |
---|
| 1899 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1900 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1901 | // inst->_branch_condition = ; |
---|
| 1902 | // inst->_branch_stack_write = ; |
---|
| 1903 | // inst->_branch_direction = ; |
---|
| 1904 | // inst->_address_next = ; |
---|
| 1905 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1906 | } |
---|
| 1907 | |
---|
| 1908 | void instruction_l_sfltsi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1909 | { |
---|
| 1910 | log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi"); |
---|
| 1911 | |
---|
| 1912 | inst->_type = TYPE_TEST; |
---|
| 1913 | inst->_operation = OPERATION_TEST_L_SFLTS; |
---|
| 1914 | inst->_has_immediat = 1; |
---|
| 1915 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1916 | inst->_read_ra = 1; |
---|
| 1917 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1918 | inst->_read_rb = 0; |
---|
| 1919 | // inst->_num_reg_rb = ; |
---|
| 1920 | inst->_read_rc = 0; |
---|
| 1921 | // inst->_num_reg_rc = ; |
---|
| 1922 | inst->_write_rd = 0; |
---|
| 1923 | // inst->_num_reg_rd = ; |
---|
| 1924 | inst->_write_re = 1; |
---|
| 1925 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1926 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1927 | // inst->_branch_condition = ; |
---|
| 1928 | // inst->_branch_stack_write = ; |
---|
| 1929 | // inst->_branch_direction = ; |
---|
| 1930 | // inst->_address_next = ; |
---|
| 1931 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1932 | } |
---|
| 1933 | |
---|
| 1934 | void instruction_l_sfltu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1935 | { |
---|
| 1936 | log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu"); |
---|
| 1937 | |
---|
| 1938 | inst->_type = TYPE_TEST; |
---|
| 1939 | inst->_operation = OPERATION_TEST_L_SFLTU; |
---|
| 1940 | inst->_has_immediat = 0; |
---|
| 1941 | // inst->_immediat = ; |
---|
| 1942 | inst->_read_ra = 1; |
---|
| 1943 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1944 | inst->_read_rb = 1; |
---|
| 1945 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1946 | inst->_read_rc = 0; |
---|
| 1947 | // inst->_num_reg_rc = ; |
---|
| 1948 | inst->_write_rd = 0; |
---|
| 1949 | // inst->_num_reg_rd = ; |
---|
| 1950 | inst->_write_re = 1; |
---|
| 1951 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1952 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1953 | // inst->_branch_condition = ; |
---|
| 1954 | // inst->_branch_stack_write = ; |
---|
| 1955 | // inst->_branch_direction = ; |
---|
| 1956 | // inst->_address_next = ; |
---|
| 1957 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1958 | } |
---|
| 1959 | |
---|
| 1960 | void instruction_l_sfltui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1961 | { |
---|
| 1962 | log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui"); |
---|
| 1963 | |
---|
| 1964 | inst->_type = TYPE_TEST; |
---|
| 1965 | inst->_operation = OPERATION_TEST_L_SFLTU; |
---|
| 1966 | inst->_has_immediat = 1; |
---|
| 1967 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1968 | inst->_read_ra = 1; |
---|
| 1969 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1970 | inst->_read_rb = 0; |
---|
| 1971 | // inst->_num_reg_rb = ; |
---|
| 1972 | inst->_read_rc = 0; |
---|
| 1973 | // inst->_num_reg_rc = ; |
---|
| 1974 | inst->_write_rd = 0; |
---|
| 1975 | // inst->_num_reg_rd = ; |
---|
| 1976 | inst->_write_re = 1; |
---|
| 1977 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1978 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 1979 | // inst->_branch_condition = ; |
---|
| 1980 | // inst->_branch_stack_write = ; |
---|
| 1981 | // inst->_branch_direction = ; |
---|
| 1982 | // inst->_address_next = ; |
---|
| 1983 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1984 | } |
---|
| 1985 | |
---|
| 1986 | void instruction_l_sfne (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1987 | { |
---|
| 1988 | log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne"); |
---|
| 1989 | |
---|
| 1990 | inst->_type = TYPE_TEST; |
---|
| 1991 | inst->_operation = OPERATION_TEST_L_SFNE; |
---|
| 1992 | inst->_has_immediat = 0; |
---|
| 1993 | // inst->_immediat = ; |
---|
| 1994 | inst->_read_ra = 1; |
---|
| 1995 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1996 | inst->_read_rb = 1; |
---|
| 1997 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1998 | inst->_read_rc = 0; |
---|
| 1999 | // inst->_num_reg_rc = ; |
---|
| 2000 | inst->_write_rd = 0; |
---|
| 2001 | // inst->_num_reg_rd = ; |
---|
| 2002 | inst->_write_re = 1; |
---|
| 2003 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2004 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2005 | // inst->_branch_condition = ; |
---|
| 2006 | // inst->_branch_stack_write = ; |
---|
| 2007 | // inst->_branch_direction = ; |
---|
| 2008 | // inst->_address_next = ; |
---|
| 2009 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2010 | } |
---|
| 2011 | |
---|
| 2012 | void instruction_l_sfnei (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2013 | { |
---|
| 2014 | log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei"); |
---|
| 2015 | |
---|
| 2016 | inst->_type = TYPE_TEST; |
---|
| 2017 | inst->_operation = OPERATION_TEST_L_SFNE; |
---|
| 2018 | inst->_has_immediat = 1; |
---|
| 2019 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2020 | inst->_read_ra = 1; |
---|
| 2021 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2022 | inst->_read_rb = 0; |
---|
| 2023 | // inst->_num_reg_rb = ; |
---|
| 2024 | inst->_read_rc = 0; |
---|
| 2025 | // inst->_num_reg_rc = ; |
---|
| 2026 | inst->_write_rd = 0; |
---|
| 2027 | // inst->_num_reg_rd = ; |
---|
| 2028 | inst->_write_re = 1; |
---|
| 2029 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2030 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2031 | // inst->_branch_condition = ; |
---|
| 2032 | // inst->_branch_stack_write = ; |
---|
| 2033 | // inst->_branch_direction = ; |
---|
| 2034 | // inst->_address_next = ; |
---|
| 2035 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2036 | } |
---|
| 2037 | |
---|
| 2038 | void instruction_l_sh (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2039 | { |
---|
| 2040 | log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh"); |
---|
| 2041 | |
---|
| 2042 | inst->_type = TYPE_MEMORY; |
---|
| 2043 | inst->_operation = OPERATION_MEMORY_STORE_16; |
---|
| 2044 | inst->_has_immediat = 1; |
---|
| 2045 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 2046 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 2047 | inst->_read_ra = 1; |
---|
| 2048 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2049 | inst->_read_rb = 1; |
---|
| 2050 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2051 | inst->_read_rc = 0; |
---|
| 2052 | // inst->_num_reg_rc = ; |
---|
| 2053 | inst->_write_rd = 0; |
---|
| 2054 | // inst->_num_reg_rd = ; |
---|
| 2055 | inst->_write_re = 0; |
---|
| 2056 | // inst->_num_reg_re = ; |
---|
| 2057 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 2058 | // inst->_branch_condition = ; |
---|
| 2059 | // inst->_branch_stack_write = ; |
---|
| 2060 | // inst->_branch_direction = ; |
---|
| 2061 | // inst->_address_next = ; |
---|
| 2062 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2063 | } |
---|
| 2064 | |
---|
| 2065 | void instruction_l_sll (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2066 | { |
---|
| 2067 | log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll"); |
---|
| 2068 | |
---|
| 2069 | inst->_type = TYPE_SHIFT; |
---|
| 2070 | inst->_operation = OPERATION_SHIFT_L_SLL; |
---|
| 2071 | inst->_has_immediat = 0; |
---|
| 2072 | // inst->_immediat = ; |
---|
| 2073 | inst->_read_ra = 1; |
---|
| 2074 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2075 | inst->_read_rb = 1; |
---|
| 2076 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2077 | inst->_read_rc = 0; |
---|
| 2078 | // inst->_num_reg_rc = ; |
---|
| 2079 | inst->_write_rd = 1; |
---|
| 2080 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2081 | inst->_write_re = 0; |
---|
| 2082 | // inst->_num_reg_re = ; |
---|
| 2083 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2084 | // inst->_branch_condition = ; |
---|
| 2085 | // inst->_branch_stack_write = ; |
---|
| 2086 | // inst->_branch_direction = ; |
---|
| 2087 | // inst->_address_next = ; |
---|
| 2088 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2089 | } |
---|
| 2090 | |
---|
| 2091 | void instruction_l_slli (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2092 | { |
---|
| 2093 | log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli"); |
---|
| 2094 | |
---|
| 2095 | inst->_type = TYPE_SHIFT; |
---|
| 2096 | inst->_operation = OPERATION_SHIFT_L_SLL; |
---|
| 2097 | inst->_has_immediat = 1; |
---|
| 2098 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 2099 | inst->_read_ra = 1; |
---|
| 2100 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2101 | inst->_read_rb = 0; |
---|
| 2102 | // inst->_num_reg_rb = ; |
---|
| 2103 | inst->_read_rc = 0; |
---|
| 2104 | // inst->_num_reg_rc = ; |
---|
| 2105 | inst->_write_rd = 1; |
---|
| 2106 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2107 | inst->_write_re = 0; |
---|
| 2108 | // inst->_num_reg_re = ; |
---|
| 2109 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2110 | // inst->_branch_condition = ; |
---|
| 2111 | // inst->_branch_stack_write = ; |
---|
| 2112 | // inst->_branch_direction = ; |
---|
| 2113 | // inst->_address_next = ; |
---|
| 2114 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2115 | } |
---|
| 2116 | |
---|
| 2117 | void instruction_l_sra (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2118 | { |
---|
| 2119 | log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra"); |
---|
| 2120 | |
---|
| 2121 | inst->_type = TYPE_SHIFT; |
---|
| 2122 | inst->_operation = OPERATION_SHIFT_L_SRA; |
---|
| 2123 | inst->_has_immediat = 0; |
---|
| 2124 | // inst->_immediat = ; |
---|
| 2125 | inst->_read_ra = 1; |
---|
| 2126 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2127 | inst->_read_rb = 1; |
---|
| 2128 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2129 | inst->_read_rc = 0; |
---|
| 2130 | // inst->_num_reg_rc = ; |
---|
| 2131 | inst->_write_rd = 1; |
---|
| 2132 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2133 | inst->_write_re = 0; |
---|
| 2134 | // inst->_num_reg_re = ; |
---|
| 2135 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2136 | // inst->_branch_condition = ; |
---|
| 2137 | // inst->_branch_stack_write = ; |
---|
| 2138 | // inst->_branch_direction = ; |
---|
| 2139 | // inst->_address_next = ; |
---|
| 2140 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2141 | } |
---|
| 2142 | |
---|
| 2143 | void instruction_l_srai (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2144 | { |
---|
| 2145 | log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai"); |
---|
| 2146 | |
---|
| 2147 | inst->_type = TYPE_SHIFT; |
---|
| 2148 | inst->_operation = OPERATION_SHIFT_L_SRA; |
---|
| 2149 | inst->_has_immediat = 1; |
---|
| 2150 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 2151 | inst->_read_ra = 1; |
---|
| 2152 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2153 | inst->_read_rb = 0; |
---|
| 2154 | // inst->_num_reg_rb = ; |
---|
| 2155 | inst->_read_rc = 0; |
---|
| 2156 | // inst->_num_reg_rc = ; |
---|
| 2157 | inst->_write_rd = 1; |
---|
| 2158 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2159 | inst->_write_re = 0; |
---|
| 2160 | // inst->_num_reg_re = ; |
---|
| 2161 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2162 | // inst->_branch_condition = ; |
---|
| 2163 | // inst->_branch_stack_write = ; |
---|
| 2164 | // inst->_branch_direction = ; |
---|
| 2165 | // inst->_address_next = ; |
---|
| 2166 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2167 | } |
---|
| 2168 | |
---|
| 2169 | void instruction_l_srl (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2170 | { |
---|
| 2171 | log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl"); |
---|
| 2172 | |
---|
| 2173 | inst->_type = TYPE_SHIFT; |
---|
| 2174 | inst->_operation = OPERATION_SHIFT_L_SRL; |
---|
| 2175 | inst->_has_immediat = 0; |
---|
| 2176 | // inst->_immediat = ; |
---|
| 2177 | inst->_read_ra = 1; |
---|
| 2178 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2179 | inst->_read_rb = 1; |
---|
| 2180 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2181 | inst->_read_rc = 0; |
---|
| 2182 | // inst->_num_reg_rc = ; |
---|
| 2183 | inst->_write_rd = 1; |
---|
| 2184 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2185 | inst->_write_re = 0; |
---|
| 2186 | // inst->_num_reg_re = ; |
---|
| 2187 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2188 | // inst->_branch_condition = ; |
---|
| 2189 | // inst->_branch_stack_write = ; |
---|
| 2190 | // inst->_branch_direction = ; |
---|
| 2191 | // inst->_address_next = ; |
---|
| 2192 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2193 | } |
---|
| 2194 | |
---|
| 2195 | void instruction_l_srli (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2196 | { |
---|
| 2197 | log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli"); |
---|
| 2198 | |
---|
| 2199 | inst->_type = TYPE_SHIFT; |
---|
| 2200 | inst->_operation = OPERATION_SHIFT_L_SRL; |
---|
| 2201 | inst->_has_immediat = 1; |
---|
| 2202 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 2203 | inst->_read_ra = 1; |
---|
| 2204 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2205 | inst->_read_rb = 0; |
---|
| 2206 | // inst->_num_reg_rb = ; |
---|
| 2207 | inst->_read_rc = 0; |
---|
| 2208 | // inst->_num_reg_rc = ; |
---|
| 2209 | inst->_write_rd = 1; |
---|
| 2210 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2211 | inst->_write_re = 0; |
---|
| 2212 | // inst->_num_reg_re = ; |
---|
| 2213 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2214 | // inst->_branch_condition = ; |
---|
| 2215 | // inst->_branch_stack_write = ; |
---|
| 2216 | // inst->_branch_direction = ; |
---|
| 2217 | // inst->_address_next = ; |
---|
| 2218 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2219 | } |
---|
| 2220 | |
---|
| 2221 | void instruction_l_sub (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2222 | { |
---|
| 2223 | log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub"); |
---|
| 2224 | |
---|
| 2225 | inst->_type = TYPE_ALU; |
---|
| 2226 | inst->_operation = OPERATION_ALU_L_SUB; |
---|
| 2227 | inst->_has_immediat = 0; |
---|
| 2228 | // inst->_immediat = ; |
---|
| 2229 | inst->_read_ra = 1; |
---|
| 2230 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2231 | inst->_read_rb = 1; |
---|
| 2232 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2233 | inst->_read_rc = 0; |
---|
| 2234 | // inst->_num_reg_rc = ; |
---|
| 2235 | inst->_write_rd = 1; |
---|
| 2236 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2237 | inst->_write_re = 1; |
---|
| 2238 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 2239 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
| 2240 | // inst->_branch_condition = ; |
---|
| 2241 | // inst->_branch_stack_write = ; |
---|
| 2242 | // inst->_branch_direction = ; |
---|
| 2243 | // inst->_address_next = ; |
---|
| 2244 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2245 | } |
---|
| 2246 | |
---|
| 2247 | void instruction_l_sw (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2248 | { |
---|
| 2249 | log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw"); |
---|
| 2250 | |
---|
| 2251 | inst->_type = TYPE_MEMORY; |
---|
| 2252 | inst->_operation = OPERATION_MEMORY_STORE_32; |
---|
| 2253 | inst->_has_immediat = 1; |
---|
| 2254 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 2255 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 2256 | inst->_read_ra = 1; |
---|
| 2257 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2258 | inst->_read_rb = 1; |
---|
| 2259 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2260 | inst->_read_rc = 0; |
---|
| 2261 | // inst->_num_reg_rc = ; |
---|
| 2262 | inst->_write_rd = 0; |
---|
| 2263 | // inst->_num_reg_rd = ; |
---|
| 2264 | inst->_write_re = 0; |
---|
| 2265 | // inst->_num_reg_re = ; |
---|
| 2266 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
| 2267 | // inst->_branch_condition = ; |
---|
| 2268 | // inst->_branch_stack_write = ; |
---|
| 2269 | // inst->_branch_direction = ; |
---|
| 2270 | // inst->_address_next = ; |
---|
| 2271 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2272 | } |
---|
| 2273 | |
---|
| 2274 | void instruction_l_sys (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2275 | { |
---|
| 2276 | log_printf(TRACE,Decod,"instruction_l_sys"," * instruction : l.sys"); |
---|
| 2277 | |
---|
| 2278 | if (range<uint32_t>(inst->_instruction,22,16) != 0) |
---|
| 2279 | { |
---|
| 2280 | instruction_illegal (inst, param); |
---|
| 2281 | } |
---|
| 2282 | else |
---|
| 2283 | { |
---|
| 2284 | inst->_type = TYPE_SPECIAL; |
---|
| 2285 | inst->_operation = OPERATION_SPECIAL_L_SYS; |
---|
| 2286 | // inst->_has_immediat = 1; |
---|
| 2287 | // inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 2288 | inst->_has_immediat = 0; |
---|
| 2289 | // inst->_immediat = ; |
---|
| 2290 | inst->_read_ra = 0; |
---|
| 2291 | // inst->_num_reg_ra = ; |
---|
| 2292 | inst->_read_rb = 0; |
---|
| 2293 | // inst->_num_reg_rb = ; |
---|
| 2294 | inst->_read_rc = 0; |
---|
| 2295 | // inst->_num_reg_rc = ; |
---|
| 2296 | inst->_write_rd = 0; |
---|
| 2297 | // inst->_num_reg_rd = ; |
---|
| 2298 | inst->_write_re = 0; |
---|
| 2299 | // inst->_num_reg_re = ; |
---|
| 2300 | inst->_exception_use = EXCEPTION_USE_SYSCALL; |
---|
| 2301 | // inst->_branch_condition = ; |
---|
| 2302 | // inst->_branch_stack_write = ; |
---|
| 2303 | // inst->_branch_direction = ; |
---|
| 2304 | |
---|
| 2305 | // if (inst->_is_delay_slot) |
---|
| 2306 | // inst->_address_next = inst->_address_previous; |
---|
| 2307 | // else |
---|
| 2308 | // inst->_address_next = inst->_address; |
---|
| 2309 | |
---|
| 2310 | |
---|
| 2311 | // inst->_address_next = ; // don't change |
---|
| 2312 | inst->_event_type = EVENT_TYPE_EXCEPTION; |
---|
| 2313 | } |
---|
| 2314 | } |
---|
| 2315 | |
---|
| 2316 | void instruction_l_trap (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2317 | { |
---|
| 2318 | log_printf(TRACE,Decod,"instruction_l_trap"," * instruction : l.trap"); |
---|
| 2319 | |
---|
| 2320 | if (range<uint32_t>(inst->_instruction,22,16) != 0) |
---|
| 2321 | { |
---|
| 2322 | instruction_illegal (inst, param); |
---|
| 2323 | } |
---|
| 2324 | else |
---|
| 2325 | { |
---|
| 2326 | inst->_type = TYPE_SPECIAL; |
---|
| 2327 | inst->_operation = OPERATION_SPECIAL_L_TRAP; |
---|
| 2328 | inst->_has_immediat = 1; |
---|
| 2329 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 2330 | inst->_read_ra = 0; |
---|
| 2331 | // inst->_num_reg_ra = ; |
---|
| 2332 | inst->_read_rb = 0; |
---|
| 2333 | // inst->_num_reg_rb = ; |
---|
| 2334 | inst->_read_rc = 0; // read all SR |
---|
| 2335 | // inst->_num_reg_rc = ; |
---|
| 2336 | inst->_write_rd = 0; |
---|
| 2337 | // inst->_num_reg_rd = ; |
---|
| 2338 | inst->_write_re = 0; |
---|
| 2339 | // inst->_num_reg_re = ; |
---|
| 2340 | inst->_exception_use = EXCEPTION_USE_TRAP; |
---|
| 2341 | // inst->_branch_condition = ; |
---|
| 2342 | // inst->_branch_stack_write = ; |
---|
| 2343 | // inst->_branch_direction = ; |
---|
| 2344 | // inst->_address_next = ; |
---|
| 2345 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2346 | } |
---|
| 2347 | } |
---|
| 2348 | |
---|
| 2349 | void instruction_l_xor (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2350 | { |
---|
| 2351 | log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor"); |
---|
| 2352 | |
---|
| 2353 | inst->_type = TYPE_ALU; |
---|
| 2354 | inst->_operation = OPERATION_ALU_L_XOR; |
---|
| 2355 | inst->_has_immediat = 0; |
---|
| 2356 | // inst->_immediat = ; |
---|
| 2357 | inst->_read_ra = 1; |
---|
| 2358 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2359 | inst->_read_rb = 1; |
---|
| 2360 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2361 | inst->_read_rc = 0; |
---|
| 2362 | // inst->_num_reg_rc = ; |
---|
| 2363 | inst->_write_rd = 1; |
---|
| 2364 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2365 | inst->_write_re = 0; |
---|
| 2366 | // inst->_num_reg_re = ; |
---|
| 2367 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2368 | // inst->_branch_condition = ; |
---|
| 2369 | // inst->_branch_stack_write = ; |
---|
| 2370 | // inst->_branch_direction = ; |
---|
| 2371 | // inst->_address_next = ; |
---|
| 2372 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2373 | } |
---|
| 2374 | |
---|
| 2375 | void instruction_l_xori (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2376 | { |
---|
| 2377 | log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori"); |
---|
| 2378 | |
---|
| 2379 | inst->_type = TYPE_ALU; |
---|
| 2380 | inst->_operation = OPERATION_ALU_L_XOR; |
---|
| 2381 | inst->_has_immediat = 1; |
---|
| 2382 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2383 | inst->_read_ra = 1; |
---|
| 2384 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2385 | inst->_read_rb = 0; |
---|
| 2386 | // inst->_num_reg_rb = ; |
---|
| 2387 | inst->_read_rc = 0; |
---|
| 2388 | // inst->_num_reg_rc = ; |
---|
| 2389 | inst->_write_rd = 1; |
---|
| 2390 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2391 | inst->_write_re = 0; |
---|
| 2392 | // inst->_num_reg_re = ; |
---|
| 2393 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
| 2394 | // inst->_branch_condition = ; |
---|
| 2395 | // inst->_branch_stack_write = ; |
---|
| 2396 | // inst->_branch_direction = ; |
---|
| 2397 | // inst->_address_next = ; |
---|
| 2398 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2399 | } |
---|
| 2400 | |
---|
| 2401 | // // ORFPX |
---|
| 2402 | // void instruction_lf_add_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2403 | // void instruction_lf_add_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2404 | // void instruction_lf_cust1_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2405 | // void instruction_lf_cust1_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2406 | // void instruction_lf_div_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2407 | // void instruction_lf_div_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2408 | // void instruction_lf_ftoi_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2409 | // void instruction_lf_ftoi_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2410 | // void instruction_lf_itof_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2411 | // void instruction_lf_itof_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2412 | // void instruction_lf_madd_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2413 | // void instruction_lf_madd_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2414 | // void instruction_lf_mul_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2415 | // void instruction_lf_mul_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2416 | // void instruction_lf_rem_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2417 | // void instruction_lf_rem_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2418 | // void instruction_lf_sfeq_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2419 | // void instruction_lf_sfeq_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2420 | // void instruction_lf_sfge_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2421 | // void instruction_lf_sfge_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2422 | // void instruction_lf_sfgt_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2423 | // void instruction_lf_sfgt_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2424 | // void instruction_lf_sfle_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2425 | // void instruction_lf_sfle_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2426 | // void instruction_lf_sflt_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2427 | // void instruction_lf_sflt_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2428 | // void instruction_lf_sfne_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2429 | // void instruction_lf_sfne_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2430 | // void instruction_lf_sub_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2431 | // void instruction_lf_sub_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2432 | |
---|
| 2433 | // // ORVDX |
---|
| 2434 | // void instruction_lv_add_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2435 | // void instruction_lv_add_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2436 | // void instruction_lv_adds_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2437 | // void instruction_lv_adds_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2438 | // void instruction_lv_addu_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2439 | // void instruction_lv_addu_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2440 | // void instruction_lv_addus_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2441 | // void instruction_lv_addus_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2442 | // void instruction_lv_all_eq_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2443 | // void instruction_lv_all_eq_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2444 | // void instruction_lv_all_ge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2445 | // void instruction_lv_all_ge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2446 | // void instruction_lv_all_gt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2447 | // void instruction_lv_all_gt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2448 | // void instruction_lv_all_le_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2449 | // void instruction_lv_all_le_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2450 | // void instruction_lv_all_lt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2451 | // void instruction_lv_all_lt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2452 | // void instruction_lv_all_ne_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2453 | // void instruction_lv_all_ne_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2454 | // void instruction_lv_and (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2455 | // void instruction_lv_any_eq_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2456 | // void instruction_lv_any_eq_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2457 | // void instruction_lv_any_ge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2458 | // void instruction_lv_any_ge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2459 | // void instruction_lv_any_gt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2460 | // void instruction_lv_any_gt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2461 | // void instruction_lv_any_le_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2462 | // void instruction_lv_any_le_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2463 | // void instruction_lv_any_lt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2464 | // void instruction_lv_any_lt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2465 | // void instruction_lv_any_ne_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2466 | // void instruction_lv_any_ne_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2467 | // void instruction_lv_avg_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2468 | // void instruction_lv_avg_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2469 | // void instruction_lv_cmp_eq_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2470 | // void instruction_lv_cmp_eq_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2471 | // void instruction_lv_cmp_ge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2472 | // void instruction_lv_cmp_ge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2473 | // void instruction_lv_cmp_gt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2474 | // void instruction_lv_cmp_gt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2475 | // void instruction_lv_cmp_le_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2476 | // void instruction_lv_cmp_le_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2477 | // void instruction_lv_cmp_lt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2478 | // void instruction_lv_cmp_lt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2479 | // void instruction_lv_cmp_ne_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2480 | // void instruction_lv_cmp_ne_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2481 | // void instruction_lv_cust1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2482 | // void instruction_lv_cust2 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2483 | // void instruction_lv_cust3 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2484 | // void instruction_lv_cust4 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2485 | // void instruction_lv_madds_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2486 | // void instruction_lv_max_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2487 | // void instruction_lv_max_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2488 | // void instruction_lv_merge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2489 | // void instruction_lv_merge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2490 | // void instruction_lv_min_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2491 | // void instruction_lv_min_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2492 | // void instruction_lv_msubs_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2493 | // void instruction_lv_muls_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2494 | // void instruction_lv_nand (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2495 | // void instruction_lv_nor (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2496 | // void instruction_lv_or (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2497 | // void instruction_lv_pack_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2498 | // void instruction_lv_pack_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2499 | // void instruction_lv_packs_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2500 | // void instruction_lv_packs_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2501 | // void instruction_lv_packus_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2502 | // void instruction_lv_packus_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2503 | // void instruction_lv_perm_n (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2504 | // void instruction_lv_rl_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2505 | // void instruction_lv_rl_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2506 | // void instruction_lv_sll (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2507 | // void instruction_lv_sll_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2508 | // void instruction_lv_sll_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2509 | // void instruction_lv_sra_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2510 | // void instruction_lv_sra_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2511 | // void instruction_lv_srl (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2512 | // void instruction_lv_srl_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2513 | // void instruction_lv_srl_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2514 | // void instruction_lv_sub_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2515 | // void instruction_lv_sub_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2516 | // void instruction_lv_subs_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2517 | // void instruction_lv_subs_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2518 | // void instruction_lv_subu_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2519 | // void instruction_lv_subu_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2520 | // void instruction_lv_subus_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2521 | // void instruction_lv_subus_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2522 | // void instruction_lv_unpack_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2523 | // void instruction_lv_unpack_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2524 | // void instruction_lv_xor (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2525 | |
---|
| 2526 | }; // end namespace decod |
---|
| 2527 | }; // end namespace decod_unit |
---|
| 2528 | }; // end namespace front_end |
---|
| 2529 | }; // end namespace multi_front_end |
---|
| 2530 | }; // end namespace core |
---|
| 2531 | }; // end namespace behavioural |
---|
| 2532 | }; // end namespace morpheo |
---|