Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp @ 86

Last change on this file since 86 was 86, checked in by rosiere, 16 years ago

Decod :

Correct selftest
Set Instruction address on (32/64)-2 bits,
Decod Custom Instruction : valid and tested. (add an test to verify the decod information)

Property svn:keywords set to Id

File size: 110.3 KB

Line
1	/*
2	* $Id: Instruction.cpp 86 2008-05-14 17:08:56Z rosiere $
3	*
4	* [ Description ]
5	*
6	* instruction MAC_UNIT (l.mac, l.maci, l.macrc, l.msb) throw a context event. Also is sequential.
7	* If your program need intensive mac_unit, you can change the implementation of this unit :
8	* 1) "decod" : inst->_event_type = EVENT_TYPE_NONE;
9	* 2) "rename" : add component as load_store_unit pointer management
10	* 3) "functionnal_unit" : test type instruction, if type=MAC_UNIT, insert in queue, the localisation is the ptr give by rename stage. Retire in this queue in sequence (as the store queue).
11	*
12	*/
13
14	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h"
15	#include "Behavioural/include/Constants.h"
16
17	namespace morpheo {
18	namespace behavioural {
19	namespace core {
20	namespace multi_front_end {
21	namespace front_end {
22	namespace decod_unit {
23	namespace decod {
24
25	#define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>(32, x,true ,nb_bits)
26	#define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>(32, x,false,nb_bits)
27
28	void instruction_decod (decod_instruction_t * inst, decod_param_t * param)
29	{
30	// instruction_decod_type_0 (inst,param);
31
32	uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
33	(* param->_function_decod[ 0][opcod]) (inst,param);
34	}
35
36	// void instruction_decod_type_0 (decod_instruction_t * inst, decod_param_t * param)
37	// {
38	// uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
39	// (* param->_function_decod[ 0][opcod]) (inst,param);
40	// }
41
42	void instruction_decod_type_1 (decod_instruction_t * inst, decod_param_t * param)
43	{
44	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
45	(* param->_function_decod[ 1][opcod]) (inst,param);
46	}
47
48	void instruction_decod_type_2 (decod_instruction_t * inst, decod_param_t * param)
49	{
50	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
51	(* param->_function_decod[ 2][opcod]) (inst,param);
52	}
53
54	void instruction_decod_type_3 (decod_instruction_t * inst, decod_param_t * param)
55	{
56	uint32_t opcod = ((range<uint32_t>(inst->_instruction, 9, 8)<<4) \|
57	(range<uint32_t>(inst->_instruction, 3, 0)));
58	(* param->_function_decod[ 3][opcod]) (inst,param);
59	}
60
61	void instruction_decod_type_4 (decod_instruction_t * inst, decod_param_t * param)
62	{
63	uint32_t opcod = range<uint32_t>(inst->_instruction,25,21);
64	(* param->_function_decod[ 4][opcod]) (inst,param);
65	}
66
67	void instruction_decod_type_5 (decod_instruction_t * inst, decod_param_t * param)
68	{
69	uint32_t opcod = range<uint32_t>(inst->_instruction,25,21);
70	(* param->_function_decod[ 5][opcod]) (inst,param);
71	}
72
73	void instruction_decod_type_6 (decod_instruction_t * inst, decod_param_t * param)
74	{
75	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
76	(* param->_function_decod[ 6][opcod]) (inst,param);
77	}
78
79	void instruction_decod_type_7 (decod_instruction_t * inst, decod_param_t * param)
80	{
81	uint32_t opcod = range<uint32_t>(inst->_instruction, 3, 0);
82	(* param->_function_decod[ 7][opcod]) (inst,param);
83	}
84
85	void instruction_decod_type_8 (decod_instruction_t * inst, decod_param_t * param)
86	{
87	uint32_t opcod = range<uint32_t>(inst->_instruction,16,16);
88	(* param->_function_decod[ 8][opcod]) (inst,param);
89	}
90
91	void instruction_decod_type_9 (decod_instruction_t * inst, decod_param_t * param)
92	{
93	uint32_t opcod = range<uint32_t>(inst->_instruction,25,23);
94	(* param->_function_decod[ 9][opcod]) (inst,param);
95	}
96
97	void instruction_decod_type_10 (decod_instruction_t * inst, decod_param_t * param)
98	{
99	uint32_t opcod = range<uint32_t>(inst->_instruction,25,24);
100	(* param->_function_decod[10][opcod]) (inst,param);
101	}
102
103	void instruction_decod_type_11 (decod_instruction_t * inst, decod_param_t * param)
104	{
105	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
106	(* param->_function_decod[11][opcod]) (inst,param);
107	}
108
109	void instruction_decod_type_12 (decod_instruction_t * inst, decod_param_t * param)
110	{
111	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
112	(* param->_function_decod[12][opcod]) (inst,param);
113	}
114
115	void instruction_decod_type_13 (decod_instruction_t * inst, decod_param_t * param)
116	{
117	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
118	(* param->_function_decod[13][opcod]) (inst,param);
119	}
120
121	void instruction_illegal (decod_instruction_t * inst, decod_param_t * param)
122	{
123	log_printf(TRACE,Decod,"instruction_illegal","instruction_illegal");
124
125	inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION;
126
127	if (inst->_is_delay_slot)
128	inst->_address_next = inst->_address_previous;
129	else
130	inst->_address_next = inst->_address;
131
132	inst->_event_type = EVENT_TYPE_EXCEPTION;
133	}
134
135	void instruction_l_custom (decod_instruction_t * inst, decod_param_t * param)
136	{
137	log_printf(TRACE,Decod,"instruction_l_custom"," * instruction : custom");
138
139	uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
140
141	inst->_type = TYPE_CUSTOM;
142	switch (opcod)
143	{
144	case OPCOD_L_CUST1 : {inst->_operation = OPERATION_CUSTOM_L_1; break;}
145	case OPCOD_L_CUST2 : {inst->_operation = OPERATION_CUSTOM_L_2; break;}
146	case OPCOD_L_CUST3 : {inst->_operation = OPERATION_CUSTOM_L_3; break;}
147	case OPCOD_L_CUST4 : {inst->_operation = OPERATION_CUSTOM_L_4; break;}
148	case OPCOD_L_CUST5 : {inst->_operation = OPERATION_CUSTOM_L_5; break;}
149	case OPCOD_L_CUST6 : {inst->_operation = OPERATION_CUSTOM_L_6; break;}
150	case OPCOD_L_CUST7 : {inst->_operation = OPERATION_CUSTOM_L_7; break;}
151	case OPCOD_L_CUST8 : {inst->_operation = OPERATION_CUSTOM_L_8; break;}
152	default : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));}
153	}
154
155	(* param->_function_custom[ 0][opcod]) (inst,param);
156
157	instruction_custom(inst,param);
158	}
159
160	void instruction_lf_custom (decod_instruction_t * inst, decod_param_t * param)
161	{
162	log_printf(TRACE,Decod,"instruction_lf_custom"," * instruction : custom");
163
164	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
165
166	inst->_type = TYPE_CUSTOM;
167	switch (opcod)
168	{
169	// case OPCOD_LF_CUST1_D : {inst->_operation = OPERATION_CUSTOM_LF_1_D; break;}
170	// case OPCOD_LF_CUST1_S : {inst->_operation = OPERATION_CUSTOM_LF_1_S; break;}
171	default : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));}
172	}
173
174	(* param->_function_custom[ 1][opcod]) (inst,param);
175
176	instruction_custom(inst,param);
177	}
178
179	void instruction_lv_custom (decod_instruction_t * inst, decod_param_t * param)
180	{
181	log_printf(TRACE,Decod,"instruction_lv_custom"," * instruction : custom");
182
183	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
184
185	inst->_type = TYPE_CUSTOM;
186	switch (opcod)
187	{
188	// case OPCOD_LV_CUST1 : {inst->_operation = OPERATION_CUSTOM_LV_1; break;}
189	// case OPCOD_LV_CUST2 : {inst->_operation = OPERATION_CUSTOM_LV_2; break;}
190	// case OPCOD_LV_CUST3 : {inst->_operation = OPERATION_CUSTOM_LV_3; break;}
191	// case OPCOD_LV_CUST4 : {inst->_operation = OPERATION_CUSTOM_LV_4; break;}
192	default : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));}
193	}
194
195	(* param->_function_custom[ 2][opcod]) (inst,param);
196
197	instruction_custom(inst,param);
198	}
199
200	void instruction_custom (decod_instruction_t * inst, decod_param_t * param)
201	{
202	// Test custom operation
203
204	std::string msg = "";
205
206	if (inst->_exception_use != EXCEPTION_USE_ILLEGAL_INSTRUCTION)
207	{
208	if (inst->_type != TYPE_CUSTOM)
209	msg += _("Invalid Type.\n");
210
211	if ((inst->_operation != OPERATION_CUSTOM_L_1 ) and
212	(inst->_operation != OPERATION_CUSTOM_L_2 ) and
213	(inst->_operation != OPERATION_CUSTOM_L_3 ) and
214	(inst->_operation != OPERATION_CUSTOM_L_4 ) and
215	(inst->_operation != OPERATION_CUSTOM_L_5 ) and
216	(inst->_operation != OPERATION_CUSTOM_L_6 ) and
217	(inst->_operation != OPERATION_CUSTOM_L_7 ) and
218	(inst->_operation != OPERATION_CUSTOM_L_8 ) and
219	(inst->_operation != OPERATION_CUSTOM_LF_1_D) and
220	(inst->_operation != OPERATION_CUSTOM_LF_1_S) and
221	(inst->_operation != OPERATION_CUSTOM_LV_1 ) and
222	(inst->_operation != OPERATION_CUSTOM_LV_2 ) and
223	(inst->_operation != OPERATION_CUSTOM_LV_3 ) and
224	(inst->_operation != OPERATION_CUSTOM_LV_4 ))
225	msg += _("Invalid Operation.\n");
226
227	if ((inst->_exception_use != EXCEPTION_USE_NONE ) and
228	(inst->_exception_use != EXCEPTION_USE_RANGE ) and
229	(inst->_exception_use != EXCEPTION_USE_CUSTOM_0 ) and
230	(inst->_exception_use != EXCEPTION_USE_CUSTOM_1 ) and
231	(inst->_exception_use != EXCEPTION_USE_CUSTOM_2 ) and
232	(inst->_exception_use != EXCEPTION_USE_CUSTOM_3 ) and
233	(inst->_exception_use != EXCEPTION_USE_CUSTOM_4 ) and
234	(inst->_exception_use != EXCEPTION_USE_CUSTOM_5 ) and
235	(inst->_exception_use != EXCEPTION_USE_CUSTOM_6 ))
236	msg += _("Invalid Exception.\n");
237
238	if ((inst->_event_type != EVENT_TYPE_NONE ) and
239	(inst->_event_type != EVENT_TYPE_SPR_ACCESS))
240	msg += _("Invalid Event_type.\n");
241
242	if (inst->_address_next != (inst->_address+1))
243	msg += _("Address must be in sequence.\n");
244
245	if (msg != "")
246	throw ERRORMORPHEO("instruction_custom","Invalid decod : "+msg);
247	}
248	}
249
250	// ORBIS
251	void instruction_l_add (decod_instruction_t * inst, decod_param_t * param)
252	{
253	log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add");
254	inst->_type = TYPE_ALU;
255	inst->_operation = OPERATION_ALU_L_ADD;
256	inst->_has_immediat = 0;
257	// inst->_immediat = ;
258	inst->_read_ra = 1;
259	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
260	inst->_read_rb = 1;
261	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
262	inst->_read_rc = 0;
263	// inst->_num_reg_rc = ;
264	inst->_write_rd = 1;
265	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
266	inst->_write_re = 1;
267	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
268	inst->_exception_use = EXCEPTION_USE_RANGE;
269	// inst->_branch_condition = ;
270	// inst->_branch_stack_write = ;
271	// inst->_branch_direction = ;
272	// inst->_address_next = ;
273	inst->_event_type = EVENT_TYPE_NONE;
274	}
275
276	void instruction_l_addc (decod_instruction_t * inst, decod_param_t * param)
277	{
278	log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc");
279
280	inst->_type = TYPE_ALU;
281	inst->_operation = OPERATION_ALU_L_ADD;
282	inst->_has_immediat = 0;
283	// inst->_immediat = ;
284	inst->_read_ra = 1;
285	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
286	inst->_read_rb = 1;
287	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
288	inst->_read_rc = 1;
289	inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV;
290	inst->_write_rd = 1;
291	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
292	inst->_write_re = 1;
293	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
294	inst->_exception_use = EXCEPTION_USE_RANGE;
295	// inst->_branch_condition = ;
296	// inst->_branch_stack_write = ;
297	// inst->_branch_direction = ;
298	// inst->_address_next = ;
299	inst->_event_type = EVENT_TYPE_NONE;
300	}
301
302	void instruction_l_addi (decod_instruction_t * inst, decod_param_t * param)
303	{
304	log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi");
305
306	inst->_type = TYPE_ALU;
307	inst->_operation = OPERATION_ALU_L_ADD;
308	inst->_has_immediat = 1;
309	inst->_immediat = EXTENDS(inst->_instruction,16);
310	inst->_read_ra = 1;
311	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
312	inst->_read_rb = 0;
313	// inst->_num_reg_rb = ;
314	inst->_read_rc = 0;
315	// inst->_num_reg_rc = ;
316	inst->_write_rd = 1;
317	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
318	inst->_write_re = 1;
319	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
320	inst->_exception_use = EXCEPTION_USE_RANGE;
321	// inst->_branch_condition = ;
322	// inst->_branch_stack_write = ;
323	// inst->_branch_direction = ;
324	// inst->_address_next = ;
325	inst->_event_type = EVENT_TYPE_NONE;
326	}
327
328	void instruction_l_addic (decod_instruction_t * inst, decod_param_t * param)
329	{
330	log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic");
331
332	inst->_type = TYPE_ALU;
333	inst->_operation = OPERATION_ALU_L_ADD;
334	inst->_has_immediat = 1;
335	inst->_immediat = EXTENDS(inst->_instruction,16);
336	inst->_read_ra = 1;
337	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
338	inst->_read_rb = 0;
339	// inst->_num_reg_rb = ;
340	inst->_read_rc = 1;
341	inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV;
342	inst->_write_rd = 1;
343	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
344	inst->_write_re = 1;
345	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
346	inst->_exception_use = EXCEPTION_USE_RANGE;
347	// inst->_branch_condition = ;
348	// inst->_branch_stack_write = ;
349	// inst->_branch_direction = ;
350	// inst->_address_next = ;
351	inst->_event_type = EVENT_TYPE_NONE;
352	}
353
354	void instruction_l_and (decod_instruction_t * inst, decod_param_t * param)
355	{
356	log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and");
357
358	inst->_type = TYPE_ALU;
359	inst->_operation = OPERATION_ALU_L_AND;
360	inst->_has_immediat = 0;
361	// inst->_immediat = ;
362	inst->_read_ra = 1;
363	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
364	inst->_read_rb = 1;
365	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
366	inst->_read_rc = 0;
367	// inst->_num_reg_rc = ;
368	inst->_write_rd = 1;
369	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
370	inst->_write_re = 0;
371	// inst->_num_reg_re = ;
372	inst->_exception_use = EXCEPTION_USE_NONE;
373	// inst->_branch_condition = ;
374	// inst->_branch_stack_write = ;
375	// inst->_branch_direction = ;
376	// inst->_address_next = ;
377	inst->_event_type = EVENT_TYPE_NONE;
378	}
379
380	void instruction_l_andi (decod_instruction_t * inst, decod_param_t * param)
381	{
382	log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi");
383
384	inst->_type = TYPE_ALU;
385	inst->_operation = OPERATION_ALU_L_AND;
386	inst->_has_immediat = 1;
387	inst->_immediat = EXTENDZ(inst->_instruction,16);
388	inst->_read_ra = 1;
389	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
390	inst->_read_rb = 0;
391	// inst->_num_reg_rb = ;
392	inst->_read_rc = 0;
393	// inst->_num_reg_rc = ;
394	inst->_write_rd = 1;
395	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
396	inst->_write_re = 0;
397	// inst->_num_reg_re = ;
398	inst->_exception_use = EXCEPTION_USE_NONE;
399	// inst->_branch_condition = ;
400	// inst->_branch_stack_write = ;
401	// inst->_branch_direction = ;
402	// inst->_address_next = ;
403	inst->_event_type = EVENT_TYPE_NONE;
404	}
405
406	void instruction_l_bf (decod_instruction_t * inst, decod_param_t * param)
407	{
408	log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf");
409
410	Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
411
412	inst->_type = TYPE_BRANCH;
413	inst->_operation = OPERATION_BRANCH_L_TEST_F;
414	inst->_has_immediat = 1;
415	inst->_immediat = address_next;
416	inst->_read_ra = 0;
417	// inst->_num_reg_ra = ;
418	inst->_read_rb = 0;
419	// inst->_num_reg_rb = ;
420	inst->_read_rc = 1;
421	inst->_num_reg_rc = SPR_LOGIC_SR_F;
422	inst->_write_rd = 0;
423	// inst->_num_reg_rd = ;
424	inst->_write_re = 0;
425	// inst->_num_reg_re = ;
426	inst->_exception_use = EXCEPTION_USE_NONE;
427	inst->_branch_condition = BRANCH_CONDITION_FLAG_SET;
428	// inst->_branch_stack_write = 0;
429
430	inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25);
431	inst->_address_next = address_next;
432	inst->_event_type = EVENT_TYPE_NONE;
433	}
434
435	void instruction_l_bnf (decod_instruction_t * inst, decod_param_t * param)
436	{
437	log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf");
438
439	Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
440
441	inst->_type = TYPE_BRANCH;
442	inst->_operation = OPERATION_BRANCH_L_TEST_NF;
443	inst->_has_immediat = 1;
444	inst->_immediat = address_next;
445	inst->_read_ra = 0;
446	// inst->_num_reg_ra = ;
447	inst->_read_rb = 0;
448	// inst->_num_reg_rb = ;
449	inst->_read_rc = 1;
450	inst->_num_reg_rc = SPR_LOGIC_SR_F;
451	inst->_write_rd = 0;
452	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
453	inst->_write_re = 0;
454	// inst->_num_reg_re = ;
455	inst->_exception_use = EXCEPTION_USE_NONE;
456	inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET;
457	// inst->_branch_stack_write = 0;
458	inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25);
459	inst->_address_next = address_next;
460	inst->_event_type = EVENT_TYPE_NONE;
461	}
462
463	void instruction_l_cmov (decod_instruction_t * inst, decod_param_t * param)
464	{
465	log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov");
466
467	inst->_type = TYPE_MOVE;
468	inst->_operation = OPERATION_MOVE_L_CMOV;
469	inst->_has_immediat = 0;
470	// inst->_immediat = ;
471	inst->_read_ra = 1;
472	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
473	inst->_read_rb = 1;
474	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
475	inst->_read_rc = 1;
476	inst->_num_reg_rc = SPR_LOGIC_SR_F;
477	inst->_write_rd = 1;
478	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
479	inst->_write_re = 0;
480	// inst->_num_reg_re = ;
481	inst->_exception_use = EXCEPTION_USE_NONE;
482	// inst->_branch_condition = ;
483	// inst->_branch_stack_write = ;
484	// inst->_branch_direction = ;
485	// inst->_address_next = ;
486	inst->_event_type = EVENT_TYPE_NONE;
487	}
488
489	void instruction_l_csync (decod_instruction_t * inst, decod_param_t * param)
490	{
491	log_printf(TRACE,Decod,"instruction_l_csync"," * instruction : l.csync");
492
493	if (range<Tinstruction_t>(inst->_instruction,23) != 0)
494	{
495	instruction_illegal (inst, param);
496	}
497	else
498	{
499	inst->_type = TYPE_SPECIAL;
500	inst->_operation = OPERATION_SPECIAL_L_CSYNC;
501	inst->_has_immediat = 0;
502	// inst->_immediat = ;
503	inst->_read_ra = 0;
504	// inst->_num_reg_ra = ;
505	inst->_read_rb = 0;
506	// inst->_num_reg_rb = ;
507	inst->_read_rc = 0;
508	// inst->_num_reg_rc = ;
509	inst->_write_rd = 0;
510	// inst->_num_reg_rd = ;
511	inst->_write_re = 0;
512	// inst->_num_reg_re = ;
513	inst->_exception_use = EXCEPTION_USE_NONE;
514	// inst->_branch_condition = ;
515	// inst->_branch_stack_write = ;
516	// inst->_branch_direction = ;
517	// inst->_address_next = ; // don't change
518	inst->_event_type = EVENT_TYPE_CSYNC;
519	}
520	}
521
522	// void instruction_l_cust1 (decod_instruction_t * inst, decod_param_t * param)
523	// void instruction_l_cust2 (decod_instruction_t * inst, decod_param_t * param)
524	// void instruction_l_cust3 (decod_instruction_t * inst, decod_param_t * param)
525	// void instruction_l_cust4 (decod_instruction_t * inst, decod_param_t * param)
526	// void instruction_l_cust5 (decod_instruction_t * inst, decod_param_t * param)
527	// void instruction_l_cust6 (decod_instruction_t * inst, decod_param_t * param)
528	// void instruction_l_cust7 (decod_instruction_t * inst, decod_param_t * param)
529	// void instruction_l_cust8 (decod_instruction_t * inst, decod_param_t * param)
530
531	void instruction_l_div (decod_instruction_t * inst, decod_param_t * param)
532	{
533	log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div");
534
535	inst->_type = TYPE_MUL_DIV;
536	inst->_operation = OPERATION_MUL_DIV_L_DIV;
537	inst->_has_immediat = 0;
538	// inst->_immediat = ;
539	inst->_read_ra = 1;
540	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
541	inst->_read_rb = 1;
542	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
543	inst->_read_rc = 0;
544	// inst->_num_reg_rc = ;
545	inst->_write_rd = 1;
546	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
547	inst->_write_re = 1;
548	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
549	inst->_exception_use = EXCEPTION_USE_RANGE;
550	// inst->_branch_condition = ;
551	// inst->_branch_stack_write = ;
552	// inst->_branch_direction = ;
553	// inst->_address_next = ;
554	inst->_event_type = EVENT_TYPE_NONE;
555	}
556
557	void instruction_l_divu (decod_instruction_t * inst, decod_param_t * param)
558	{
559	log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu");
560
561	inst->_type = TYPE_MUL_DIV;
562	inst->_operation = OPERATION_MUL_DIV_L_DIVU;
563	inst->_has_immediat = 0;
564	// inst->_immediat = ;
565	inst->_read_ra = 1;
566	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
567	inst->_read_rb = 1;
568	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
569	inst->_read_rc = 0;
570	// inst->_num_reg_rc = ;
571	inst->_write_rd = 1;
572	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
573	inst->_write_re = 1;
574	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
575	inst->_exception_use = EXCEPTION_USE_RANGE;
576	// inst->_branch_condition = ;
577	// inst->_branch_stack_write = ;
578	// inst->_branch_direction = ;
579	// inst->_address_next = ;
580	inst->_event_type = EVENT_TYPE_NONE;
581	}
582
583	void instruction_l_extbs (decod_instruction_t * inst, decod_param_t * param)
584	{
585	log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs");
586
587	inst->_type = TYPE_EXTEND;
588	inst->_operation = OPERATION_EXTEND_L_EXTEND_S;
589	inst->_has_immediat = 1;
590	inst->_immediat = 8;
591	inst->_read_ra = 1;
592	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
593	inst->_read_rb = 0;
594	// inst->_num_reg_rb = ;
595	inst->_read_rc = 0;
596	// inst->_num_reg_rc = ;
597	inst->_write_rd = 1;
598	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
599	inst->_write_re = 0;
600	// inst->_num_reg_re = ;
601	inst->_exception_use = EXCEPTION_USE_NONE;
602	// inst->_branch_condition = ;
603	// inst->_branch_stack_write = ;
604	// inst->_branch_direction = ;
605	// inst->_address_next = ;
606	inst->_event_type = EVENT_TYPE_NONE;
607	}
608
609	void instruction_l_extbz (decod_instruction_t * inst, decod_param_t * param)
610	{
611	log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz");
612
613	inst->_type = TYPE_EXTEND;
614	inst->_operation = OPERATION_EXTEND_L_EXTEND_Z;
615	inst->_has_immediat = 1;
616	inst->_immediat = 8;
617	inst->_read_ra = 1;
618	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
619	inst->_read_rb = 0;
620	// inst->_num_reg_rb = ;
621	inst->_read_rc = 0;
622	// inst->_num_reg_rc = ;
623	inst->_write_rd = 1;
624	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
625	inst->_write_re = 0;
626	// inst->_num_reg_re = ;
627	inst->_exception_use = EXCEPTION_USE_NONE;
628	// inst->_branch_condition = ;
629	// inst->_branch_stack_write = ;
630	// inst->_branch_direction = ;
631	// inst->_address_next = ;
632	inst->_event_type = EVENT_TYPE_NONE;
633	}
634
635	void instruction_l_exths (decod_instruction_t * inst, decod_param_t * param)
636	{
637	log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths");
638
639	inst->_type = TYPE_EXTEND;
640	inst->_operation = OPERATION_EXTEND_L_EXTEND_S;
641	inst->_has_immediat = 1;
642	inst->_immediat = 16;
643	inst->_read_ra = 1;
644	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
645	inst->_read_rb = 0;
646	// inst->_num_reg_rb = ;
647	inst->_read_rc = 0;
648	// inst->_num_reg_rc = ;
649	inst->_write_rd = 1;
650	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
651	inst->_write_re = 0;
652	// inst->_num_reg_re = ;
653	inst->_exception_use = EXCEPTION_USE_NONE;
654	// inst->_branch_condition = ;
655	// inst->_branch_stack_write = ;
656	// inst->_branch_direction = ;
657	// inst->_address_next = ;
658	inst->_event_type = EVENT_TYPE_NONE;
659	}
660
661	void instruction_l_exthz (decod_instruction_t * inst, decod_param_t * param)
662	{
663	log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz");
664
665	inst->_type = TYPE_EXTEND;
666	inst->_operation = OPERATION_EXTEND_L_EXTEND_Z;
667	inst->_has_immediat = 1;
668	inst->_immediat = 16;
669	inst->_read_ra = 1;
670	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
671	inst->_read_rb = 0;
672	// inst->_num_reg_rb = ;
673	inst->_read_rc = 0;
674	// inst->_num_reg_rc = ;
675	inst->_write_rd = 1;
676	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
677	inst->_write_re = 0;
678	// inst->_num_reg_re = ;
679	inst->_exception_use = EXCEPTION_USE_NONE;
680	// inst->_branch_condition = ;
681	// inst->_branch_stack_write = ;
682	// inst->_branch_direction = ;
683	// inst->_address_next = ;
684	inst->_event_type = EVENT_TYPE_NONE;
685	}
686
687	void instruction_l_extws (decod_instruction_t * inst, decod_param_t * param)
688	{
689	log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws");
690
691	inst->_type = TYPE_EXTEND;
692	inst->_operation = OPERATION_EXTEND_L_EXTEND_S;
693	inst->_has_immediat = 1;
694	inst->_immediat = 32;
695	inst->_read_ra = 1;
696	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
697	inst->_read_rb = 0;
698	// inst->_num_reg_rb = ;
699	inst->_read_rc = 0;
700	// inst->_num_reg_rc = ;
701	inst->_write_rd = 1;
702	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
703	inst->_write_re = 0;
704	// inst->_num_reg_re = ;
705	inst->_exception_use = EXCEPTION_USE_NONE;
706	// inst->_branch_condition = ;
707	// inst->_branch_stack_write = ;
708	// inst->_branch_direction = ;
709	// inst->_address_next = ;
710	inst->_event_type = EVENT_TYPE_NONE;
711	}
712
713	void instruction_l_extwz (decod_instruction_t * inst, decod_param_t * param)
714	{
715	log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz");
716
717	inst->_type = TYPE_EXTEND;
718	inst->_operation = OPERATION_EXTEND_L_EXTEND_Z;
719	inst->_has_immediat = 1;
720	inst->_immediat = 32;
721	inst->_read_ra = 1;
722	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
723	inst->_read_rb = 0;
724	// inst->_num_reg_rb = ;
725	inst->_read_rc = 0;
726	// inst->_num_reg_rc = ;
727	inst->_write_rd = 1;
728	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
729	inst->_write_re = 0;
730	// inst->_num_reg_re = ;
731	inst->_exception_use = EXCEPTION_USE_NONE;
732	// inst->_branch_condition = ;
733	// inst->_branch_stack_write = ;
734	// inst->_branch_direction = ;
735	// inst->_address_next = ;
736	inst->_event_type = EVENT_TYPE_NONE;
737	}
738
739	void instruction_l_ff1 (decod_instruction_t * inst, decod_param_t * param)
740	{
741	log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1");
742
743	inst->_type = TYPE_FIND;
744	inst->_operation = OPERATION_FIND_L_FF1;
745	inst->_has_immediat = 0;
746	// inst->_immediat = ;
747	inst->_read_ra = 1;
748	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
749	inst->_read_rb = 0;
750	// inst->_num_reg_rb = ;
751	inst->_read_rc = 0;
752	// inst->_num_reg_rc = ;
753	inst->_write_rd = 1;
754	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
755	inst->_write_re = 0;
756	// inst->_num_reg_re = ;
757	inst->_exception_use = EXCEPTION_USE_NONE;
758	// inst->_branch_condition = ;
759	// inst->_branch_stack_write = ;
760	// inst->_branch_direction = ;
761	// inst->_address_next = ;
762	inst->_event_type = EVENT_TYPE_NONE;
763	}
764
765	void instruction_l_fl1 (decod_instruction_t * inst, decod_param_t * param)
766	{
767	log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1");
768
769	inst->_type = TYPE_FIND;
770	inst->_operation = OPERATION_FIND_L_FL1;
771	inst->_has_immediat = 0;
772	// inst->_immediat = ;
773	inst->_read_ra = 1;
774	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
775	inst->_read_rb = 0;
776	// inst->_num_reg_rb = ;
777	inst->_read_rc = 0;
778	// inst->_num_reg_rc = ;
779	inst->_write_rd = 1;
780	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
781	inst->_write_re = 0;
782	// inst->_num_reg_re = ;
783	inst->_exception_use = EXCEPTION_USE_NONE;
784	// inst->_branch_condition = ;
785	// inst->_branch_stack_write = ;
786	// inst->_branch_direction = ;
787	// inst->_address_next = ;
788	inst->_event_type = EVENT_TYPE_NONE;
789	}
790
791	void instruction_l_j (decod_instruction_t * inst, decod_param_t * param)
792	{
793	log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j");
794
795	inst->_type = TYPE_BRANCH;
796	inst->_operation = OPERATION_BRANCH_NONE;
797	inst->_has_immediat = 0;
798	// inst->_immediat = ;
799	inst->_read_ra = 0;
800	// inst->_num_reg_ra = ;
801	inst->_read_rb = 0;
802	// inst->_num_reg_rb = ;
803	inst->_read_rc = 0;
804	// inst->_num_reg_rc = ;
805	inst->_write_rd = 0;
806	// inst->_num_reg_rd = ;
807	inst->_write_re = 0;
808	// inst->_num_reg_re = ;
809	inst->_exception_use = EXCEPTION_USE_NONE;
810	inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK;
811	// inst->_branch_stack_write = 0;
812	inst->_branch_direction = 1;
813	inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
814	inst->_event_type = EVENT_TYPE_NONE;
815	}
816
817	void instruction_l_jal (decod_instruction_t * inst, decod_param_t * param)
818	{
819	log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal");
820
821	inst->_type = TYPE_BRANCH;
822	inst->_operation = OPERATION_BRANCH_L_JALR;
823	inst->_has_immediat = 1;
824	inst->_immediat = inst->_address_next+1;
825	inst->_read_ra = 0;
826	// inst->_num_reg_ra = ;
827	inst->_read_rb = 0;
828	// inst->_num_reg_rb = ;
829	inst->_read_rc = 0;
830	// inst->_num_reg_rc = ;
831	inst->_write_rd = 1;
832	inst->_num_reg_rd = 9; // Link register
833	inst->_write_re = 0;
834	// inst->_num_reg_re = ;
835	inst->_exception_use = EXCEPTION_USE_NONE;
836	inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump
837	// inst->_branch_stack_write = 1;
838	inst->_branch_direction = 1;
839	inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
840	inst->_event_type = EVENT_TYPE_NONE;
841	}
842
843	void instruction_l_jalr (decod_instruction_t * inst, decod_param_t * param)
844	{
845	log_printf(TRACE,Decod,"instruction_l_jalr"," * instruction : l.jalr");
846
847	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
848
849	if (inst->_num_reg_rb == 9)
850	{
851	instruction_illegal (inst, param);
852	}
853	else
854	{
855	inst->_type = TYPE_BRANCH;
856	inst->_operation = OPERATION_BRANCH_L_JALR;
857	inst->_has_immediat = 0;
858	// inst->_immediat = ;
859	inst->_read_ra = 0;
860	// inst->_num_reg_ra = ;
861	inst->_read_rb = 1;
862	// inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
863	inst->_read_rc = 0;
864	// inst->_num_reg_rc = ;
865	inst->_write_rd = 1;
866	inst->_num_reg_rd = 9; // Link register
867	inst->_write_re = 0;
868	// inst->_num_reg_re = ;
869	inst->_exception_use = EXCEPTION_USE_NONE;
870	// inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER;
871	inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK;
872	// inst->_branch_stack_write = 1;
873	inst->_branch_direction = 1;
874	// inst->_address_next = ;
875	inst->_event_type = EVENT_TYPE_NONE;
876	}
877	}
878
879	void instruction_l_jr (decod_instruction_t * inst, decod_param_t * param)
880	{
881	log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr");
882
883	inst->_type = TYPE_BRANCH;
884	inst->_operation = OPERATION_BRANCH_L_JALR;
885	inst->_has_immediat = 0;
886	// inst->_immediat = ;
887	inst->_read_ra = 0;
888	// inst->_num_reg_ra = ;
889	inst->_read_rb = 1;
890	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
891	inst->_read_rc = 0;
892	// inst->_num_reg_rc = ;
893	inst->_write_rd = 0;
894	// inst->_num_reg_rd = ;
895	inst->_write_re = 0;
896	// inst->_num_reg_re = ;
897	inst->_exception_use = EXCEPTION_USE_NONE;
898	inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK;
899	// inst->_branch_stack_write = 0;
900	inst->_branch_direction = 1;
901	// inst->_address_next = ;
902	inst->_event_type = EVENT_TYPE_NONE;
903	}
904
905	void instruction_l_lbs (decod_instruction_t * inst, decod_param_t * param)
906	{
907	log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs");
908
909	inst->_type = TYPE_MEMORY;
910	inst->_operation = OPERATION_MEMORY_LOAD_8_S;
911	inst->_has_immediat = 1;
912	inst->_immediat = EXTENDS(inst->_instruction,16);
913	inst->_read_ra = 1;
914	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
915	inst->_read_rb = 0;
916	// inst->_num_reg_rb = ;
917	inst->_read_rc = 0;
918	// inst->_num_reg_rc = ;
919	inst->_write_rd = 1;
920	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
921	inst->_write_re = 0;
922	// inst->_num_reg_re = ;
923	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
924	// inst->_branch_condition = ;
925	// inst->_branch_stack_write = ;
926	// inst->_branch_direction = ;
927	// inst->_address_next = ;
928	inst->_event_type = EVENT_TYPE_NONE;
929	}
930
931	void instruction_l_lbz (decod_instruction_t * inst, decod_param_t * param)
932	{
933	log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz");
934
935	inst->_type = TYPE_MEMORY;
936	inst->_operation = OPERATION_MEMORY_LOAD_8_Z;
937	inst->_has_immediat = 1;
938	inst->_immediat = EXTENDS(inst->_instruction,16);
939	inst->_read_ra = 1;
940	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
941	inst->_read_rb = 0;
942	// inst->_num_reg_rb = ;
943	inst->_read_rc = 0;
944	// inst->_num_reg_rc = ;
945	inst->_write_rd = 1;
946	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
947	inst->_write_re = 0;
948	// inst->_num_reg_re = ;
949	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
950	// inst->_branch_condition = ;
951	// inst->_branch_stack_write = ;
952	// inst->_branch_direction = ;
953	// inst->_address_next = ;
954	inst->_event_type = EVENT_TYPE_NONE;
955	}
956
957	void instruction_l_ld (decod_instruction_t * inst, decod_param_t * param)
958	{
959	log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld");
960
961	inst->_type = TYPE_MEMORY;
962	inst->_operation = OPERATION_MEMORY_LOAD_64_S;
963	inst->_has_immediat = 1;
964	inst->_immediat = EXTENDS(inst->_instruction,16);
965	inst->_read_ra = 1;
966	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
967	inst->_read_rb = 0;
968	// inst->_num_reg_rb = ;
969	inst->_read_rc = 0;
970	// inst->_num_reg_rc = ;
971	inst->_write_rd = 1;
972	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
973	inst->_write_re = 0;
974	// inst->_num_reg_re = ;
975	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
976	// inst->_branch_condition = ;
977	// inst->_branch_stack_write = ;
978	// inst->_branch_direction = ;
979	// inst->_address_next = ;
980	inst->_event_type = EVENT_TYPE_NONE;
981	}
982
983	void instruction_l_lhs (decod_instruction_t * inst, decod_param_t * param)
984	{
985	log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs");
986
987	inst->_type = TYPE_MEMORY;
988	inst->_operation = OPERATION_MEMORY_LOAD_16_S;
989	inst->_has_immediat = 1;
990	inst->_immediat = EXTENDS(inst->_instruction,16);
991	inst->_read_ra = 1;
992	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
993	inst->_read_rb = 0;
994	// inst->_num_reg_rb = ;
995	inst->_read_rc = 0;
996	// inst->_num_reg_rc = ;
997	inst->_write_rd = 1;
998	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
999	inst->_write_re = 0;
1000	// inst->_num_reg_re = ;
1001	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1002	// inst->_branch_condition = ;
1003	// inst->_branch_stack_write = ;
1004	// inst->_branch_direction = ;
1005	// inst->_address_next = ;
1006	inst->_event_type = EVENT_TYPE_NONE;
1007	}
1008
1009	void instruction_l_lhz (decod_instruction_t * inst, decod_param_t * param)
1010	{
1011	log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz");
1012
1013	inst->_type = TYPE_MEMORY;
1014	inst->_operation = OPERATION_MEMORY_LOAD_16_Z;
1015	inst->_has_immediat = 1;
1016	inst->_immediat = EXTENDS(inst->_instruction,16);
1017	inst->_read_ra = 1;
1018	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1019	inst->_read_rb = 0;
1020	// inst->_num_reg_rb = ;
1021	inst->_read_rc = 0;
1022	// inst->_num_reg_rc = ;
1023	inst->_write_rd = 1;
1024	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1025	inst->_write_re = 0;
1026	// inst->_num_reg_re = ;
1027	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1028	// inst->_branch_condition = ;
1029	// inst->_branch_stack_write = ;
1030	// inst->_branch_direction = ;
1031	// inst->_address_next = ;
1032	inst->_event_type = EVENT_TYPE_NONE;
1033	}
1034
1035	void instruction_l_lws (decod_instruction_t * inst, decod_param_t * param)
1036	{
1037	log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws");
1038
1039	inst->_type = TYPE_MEMORY;
1040	inst->_operation = OPERATION_MEMORY_LOAD_32_S;
1041	inst->_has_immediat = 1;
1042	inst->_immediat = EXTENDS(inst->_instruction,16);
1043	inst->_read_ra = 1;
1044	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1045	inst->_read_rb = 0;
1046	// inst->_num_reg_rb = ;
1047	inst->_read_rc = 0;
1048	// inst->_num_reg_rc = ;
1049	inst->_write_rd = 1;
1050	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1051	inst->_write_re = 0;
1052	// inst->_num_reg_re = ;
1053	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1054	// inst->_branch_condition = ;
1055	// inst->_branch_stack_write = ;
1056	// inst->_branch_direction = ;
1057	// inst->_address_next = ;
1058	inst->_event_type = EVENT_TYPE_NONE;
1059	}
1060
1061	void instruction_l_lwz (decod_instruction_t * inst, decod_param_t * param)
1062	{
1063	log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz");
1064
1065	inst->_type = TYPE_MEMORY;
1066	inst->_operation = OPERATION_MEMORY_LOAD_32_Z;
1067	inst->_has_immediat = 1;
1068	inst->_immediat = EXTENDS(inst->_instruction,16);
1069	inst->_read_ra = 1;
1070	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1071	inst->_read_rb = 0;
1072	// inst->_num_reg_rb = ;
1073	inst->_read_rc = 0;
1074	// inst->_num_reg_rc = ;
1075	inst->_write_rd = 1;
1076	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1077	inst->_write_re = 0;
1078	// inst->_num_reg_re = ;
1079	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1080	// inst->_branch_condition = ;
1081	// inst->_branch_stack_write = ;
1082	// inst->_branch_direction = ;
1083	// inst->_address_next = ;
1084	inst->_event_type = EVENT_TYPE_NONE;
1085	}
1086
1087	void instruction_l_mac (decod_instruction_t * inst, decod_param_t * param)
1088	{
1089	log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac");
1090
1091	inst->_type = TYPE_SPECIAL;
1092	inst->_operation = OPERATION_SPECIAL_L_MAC;
1093	inst->_has_immediat = 0;
1094	// inst->_immediat = ;
1095	inst->_read_ra = 1;
1096	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1097	inst->_read_rb = 1;
1098	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1099	inst->_read_rc = 0;
1100	// inst->_num_reg_rc = ;
1101	inst->_write_rd = 0;
1102	// inst->_num_reg_rd = ;
1103	inst->_write_re = 0;
1104	// inst->_num_reg_re = ;
1105	inst->_exception_use = EXCEPTION_USE_NONE;
1106	// inst->_branch_condition = ;
1107	// inst->_branch_stack_write = ;
1108	// inst->_branch_direction = ;
1109	// inst->_address_next = ; // don't change
1110	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1111	}
1112
1113	void instruction_l_maci (decod_instruction_t * inst, decod_param_t * param)
1114	{
1115	log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci");
1116
1117	inst->_type = TYPE_SPECIAL;
1118	inst->_operation = OPERATION_SPECIAL_L_MAC;
1119	inst->_has_immediat = 1;
1120	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
1121	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
1122	inst->_read_ra = 1;
1123	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1124	inst->_read_rb = 0;
1125	// inst->_num_reg_rb = ;
1126	inst->_read_rc = 0;
1127	// inst->_num_reg_rc = ;
1128	inst->_write_rd = 0;
1129	// inst->_num_reg_rd = ;
1130	inst->_write_re = 0;
1131	// inst->_num_reg_re = ;
1132	inst->_exception_use = EXCEPTION_USE_NONE;
1133	// inst->_branch_condition = ;
1134	// inst->_branch_stack_write = ;
1135	// inst->_branch_direction = ;
1136	// inst->_address_next = ; // don't change
1137	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1138	}
1139
1140	void instruction_l_macrc (decod_instruction_t * inst, decod_param_t * param)
1141	{
1142	log_printf(TRACE,Decod,"instruction_l_macrc"," * instruction : l.macrc");
1143
1144	if (range<uint32_t>(inst->_instruction,15, 0) != 0)
1145	{
1146	instruction_illegal (inst, param);
1147	}
1148	else
1149	{
1150	inst->_type = TYPE_SPECIAL;
1151	inst->_operation = OPERATION_SPECIAL_L_MACRC;
1152	inst->_has_immediat = 0;
1153	// inst->_immediat = ;
1154	inst->_read_ra = 0;
1155	// inst->_num_reg_ra = ;
1156	inst->_read_rb = 0;
1157	// inst->_num_reg_rb = ;
1158	inst->_read_rc = 0;
1159	// inst->_num_reg_rc = ;
1160	inst->_write_rd = 1;
1161	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1162	inst->_write_re = 0;
1163	// inst->_num_reg_re = ;
1164	inst->_exception_use = EXCEPTION_USE_NONE;
1165	// inst->_branch_condition = ;
1166	// inst->_branch_stack_write = ;
1167	// inst->_branch_direction = ;
1168	// inst->_address_next = ; // don't change
1169	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1170	}
1171	}
1172
1173	void instruction_l_mfspr (decod_instruction_t * inst, decod_param_t * param)
1174	{
1175	log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr");
1176
1177	inst->_type = TYPE_SPECIAL;
1178	inst->_operation = OPERATION_SPECIAL_L_MFSPR;
1179	inst->_has_immediat = 1;
1180	inst->_immediat = EXTENDZ(inst->_instruction,16);
1181	inst->_read_ra = 1;
1182	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1183	inst->_read_rb = 0;
1184	// inst->_num_reg_rb = ;
1185	inst->_read_rc = 0;
1186	// inst->_num_reg_rc = ;
1187	inst->_write_rd = 1;
1188	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1189	inst->_write_re = 0;
1190	// inst->_num_reg_re = ;
1191	inst->_exception_use = EXCEPTION_USE_NONE;
1192	// inst->_branch_condition = ;
1193	// inst->_branch_stack_write = ;
1194	// inst->_branch_direction = ;
1195	// inst->_address_next = ; // don't change
1196	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1197	}
1198
1199	void instruction_l_movhi (decod_instruction_t * inst, decod_param_t * param)
1200	{
1201	log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi");
1202
1203	inst->_type = TYPE_MOVE;
1204	inst->_operation = OPERATION_MOVE_L_MOVHI;
1205	inst->_has_immediat = 1;
1206	inst->_immediat = EXTENDZ(inst->_instruction,16);
1207	inst->_read_ra = 0;
1208	// inst->_num_reg_ra = ;
1209	inst->_read_rb = 0;
1210	// inst->_num_reg_rb = ;
1211	inst->_read_rc = 0;
1212	// inst->_num_reg_rc = ;
1213	inst->_write_rd = 1;
1214	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1215	inst->_write_re = 0;
1216	// inst->_num_reg_re = ;
1217	inst->_exception_use = EXCEPTION_USE_NONE;
1218	// inst->_branch_condition = ;
1219	// inst->_branch_stack_write = ;
1220	// inst->_branch_direction = ;
1221	// inst->_address_next = ;
1222	inst->_event_type = EVENT_TYPE_NONE;
1223	}
1224
1225	void instruction_l_msb (decod_instruction_t * inst, decod_param_t * param)
1226	{
1227	log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb");
1228
1229	inst->_type = TYPE_SPECIAL;
1230	inst->_operation = OPERATION_SPECIAL_L_MSB;
1231	inst->_has_immediat = 0;
1232	// inst->_immediat = ;
1233	inst->_read_ra = 1;
1234	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1235	inst->_read_rb = 1;
1236	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1237	inst->_read_rc = 0;
1238	// inst->_num_reg_rc = ;
1239	inst->_write_rd = 0;
1240	// inst->_num_reg_rd = ;
1241	inst->_write_re = 0;
1242	// inst->_num_reg_re = ;
1243	inst->_exception_use = EXCEPTION_USE_NONE;
1244	// inst->_branch_condition = ;
1245	// inst->_branch_stack_write = ;
1246	// inst->_branch_direction = ;
1247	// inst->_address_next = ; // don't change
1248	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1249	}
1250
1251	void instruction_l_msync (decod_instruction_t * inst, decod_param_t * param)
1252	{
1253	log_printf(TRACE,Decod,"instruction_l_msync"," * instruction : l.msync");
1254
1255	if (range<uint32_t>(inst->_instruction,22, 0) != 0)
1256	{
1257	instruction_illegal (inst, param);
1258	}
1259	else
1260	{
1261	inst->_type = TYPE_SPECIAL;
1262	inst->_operation = OPERATION_SPECIAL_L_MSYNC;
1263	inst->_has_immediat = 0;
1264	// inst->_immediat = ;
1265	inst->_read_ra = 0;
1266	// inst->_num_reg_ra = ;
1267	inst->_read_rb = 0;
1268	// inst->_num_reg_rb = ;
1269	inst->_read_rc = 0;
1270	// inst->_num_reg_rc = ;
1271	inst->_write_rd = 0;
1272	// inst->_num_reg_rd = ;
1273	inst->_write_re = 0;
1274	// inst->_num_reg_re = ;
1275	inst->_exception_use = EXCEPTION_USE_NONE;
1276	// inst->_branch_condition = ;
1277	// inst->_branch_stack_write = ;
1278	// inst->_branch_direction = ;
1279	// inst->_address_next = ; // don't change
1280	inst->_event_type = EVENT_TYPE_MSYNC;
1281	}
1282	}
1283
1284	void instruction_l_mtspr (decod_instruction_t * inst, decod_param_t * param)
1285	{
1286	log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr");
1287
1288	inst->_type = TYPE_SPECIAL;
1289	inst->_operation = OPERATION_SPECIAL_L_MTSPR;
1290	inst->_has_immediat = 1;
1291	inst->_immediat = EXTENDZ(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
1292	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
1293	inst->_read_ra = 1;
1294	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1295	inst->_read_rb = 1;
1296	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1297	inst->_read_rc = 0;
1298	// inst->_num_reg_rc = ;
1299	inst->_write_rd = 0;
1300	// inst->_num_reg_rd = ;
1301	inst->_write_re = 0;
1302	// inst->_num_reg_re = ;
1303	inst->_exception_use = EXCEPTION_USE_NONE;
1304	// inst->_branch_condition = ;
1305	// inst->_branch_stack_write = ;
1306	// inst->_branch_direction = ;
1307	// inst->_address_next = ; // don't change
1308	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1309	}
1310
1311	void instruction_l_mul (decod_instruction_t * inst, decod_param_t * param)
1312	{
1313	log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul");
1314
1315	inst->_type = TYPE_MUL_DIV;
1316	inst->_operation = OPERATION_MUL_DIV_L_MUL;
1317	inst->_has_immediat = 0;
1318	// inst->_immediat = ;
1319	inst->_read_ra = 1;
1320	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1321	inst->_read_rb = 1;
1322	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1323	inst->_read_rc = 0;
1324	// inst->_num_reg_rc = ;
1325	inst->_write_rd = 1;
1326	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1327	inst->_write_re = 1;
1328	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
1329	inst->_exception_use = EXCEPTION_USE_RANGE;
1330	// inst->_branch_condition = ;
1331	// inst->_branch_stack_write = ;
1332	// inst->_branch_direction = ;
1333	// inst->_address_next = ;
1334	inst->_event_type = EVENT_TYPE_NONE;
1335	}
1336
1337	void instruction_l_muli (decod_instruction_t * inst, decod_param_t * param)
1338	{
1339	log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli");
1340
1341	inst->_type = TYPE_MUL_DIV;
1342	inst->_operation = OPERATION_MUL_DIV_L_MUL;
1343	inst->_has_immediat = 1;
1344	inst->_immediat = EXTENDS(inst->_instruction,16);
1345	inst->_read_ra = 1;
1346	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1347	inst->_read_rb = 0;
1348	// inst->_num_reg_rb = ;
1349	inst->_read_rc = 0;
1350	// inst->_num_reg_rc = ;
1351	inst->_write_rd = 1;
1352	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1353	inst->_write_re = 1;
1354	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
1355	inst->_exception_use = EXCEPTION_USE_RANGE;
1356	// inst->_branch_condition = ;
1357	// inst->_branch_stack_write = ;
1358	// inst->_branch_direction = ;
1359	// inst->_address_next = ;
1360	inst->_event_type = EVENT_TYPE_NONE;
1361	}
1362
1363	void instruction_l_mulu (decod_instruction_t * inst, decod_param_t * param)
1364	{
1365	log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu");
1366
1367	inst->_type = TYPE_MUL_DIV;
1368	inst->_operation = OPERATION_MUL_DIV_L_MULU;
1369	inst->_has_immediat = 0;
1370	// inst->_immediat = ;
1371	inst->_read_ra = 1;
1372	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1373	inst->_read_rb = 1;
1374	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1375	inst->_read_rc = 0;
1376	// inst->_num_reg_rc = ;
1377	inst->_write_rd = 1;
1378	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1379	inst->_write_re = 1;
1380	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
1381	inst->_exception_use = EXCEPTION_USE_RANGE;
1382	// inst->_branch_condition = ;
1383	// inst->_branch_stack_write = ;
1384	// inst->_branch_direction = ;
1385	// inst->_address_next = ;
1386	inst->_event_type = EVENT_TYPE_NONE;
1387	}
1388
1389	void instruction_l_nop (decod_instruction_t * inst, decod_param_t * param)
1390	{
1391	log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop");
1392
1393	inst->_type = TYPE_SPECIAL;
1394	inst->_operation = OPERATION_SPECIAL_L_NOP;
1395	// inst->_has_immediat = 1;
1396	// inst->_immediat = EXTENDZ(inst->_instruction,16);
1397	inst->_has_immediat = 0;
1398	// inst->_immediat = ;
1399	inst->_read_ra = 0;
1400	// inst->_num_reg_ra = ;
1401	inst->_read_rb = 0;
1402	// inst->_num_reg_rb = ;
1403	inst->_read_rc = 0;
1404	// inst->_num_reg_rc = ;
1405	inst->_write_rd = 0;
1406	// inst->_num_reg_rd = ;
1407	inst->_write_re = 0;
1408	// inst->_num_reg_re = ;
1409	inst->_exception_use = EXCEPTION_USE_NONE;
1410	// inst->_branch_condition = ;
1411	// inst->_branch_stack_write = ;
1412	// inst->_branch_direction = ;
1413	// inst->_address_next = ;
1414	inst->_event_type = EVENT_TYPE_NONE;
1415	}
1416
1417	void instruction_l_or (decod_instruction_t * inst, decod_param_t * param)
1418	{
1419	log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or");
1420
1421	inst->_type = TYPE_ALU;
1422	inst->_operation = OPERATION_ALU_L_OR;
1423	inst->_has_immediat = 0;
1424	// inst->_immediat = ;
1425	inst->_read_ra = 1;
1426	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1427	inst->_read_rb = 1;
1428	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1429	inst->_read_rc = 0;
1430	// inst->_num_reg_rc = ;
1431	inst->_write_rd = 1;
1432	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1433	inst->_write_re = 0;
1434	// inst->_num_reg_re = ;
1435	inst->_exception_use = EXCEPTION_USE_NONE;
1436	// inst->_branch_condition = ;
1437	// inst->_branch_stack_write = ;
1438	// inst->_branch_direction = ;
1439	// inst->_address_next = ;
1440	inst->_event_type = EVENT_TYPE_NONE;
1441	}
1442
1443	void instruction_l_ori (decod_instruction_t * inst, decod_param_t * param)
1444	{
1445	log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori");
1446
1447	inst->_type = TYPE_ALU;
1448	inst->_operation = OPERATION_ALU_L_OR;
1449	inst->_has_immediat = 1;
1450	inst->_immediat = EXTENDZ(inst->_instruction,16);
1451	inst->_read_ra = 1;
1452	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1453	inst->_read_rb = 0;
1454	// inst->_num_reg_rb = ;
1455	inst->_read_rc = 0;
1456	// inst->_num_reg_rc = ;
1457	inst->_write_rd = 1;
1458	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1459	inst->_write_re = 0;
1460	// inst->_num_reg_re = ;
1461	inst->_exception_use = EXCEPTION_USE_NONE;
1462	// inst->_branch_condition = ;
1463	// inst->_branch_stack_write = ;
1464	// inst->_branch_direction = ;
1465	// inst->_address_next = ;
1466	inst->_event_type = EVENT_TYPE_NONE;
1467	}
1468
1469	void instruction_l_psync (decod_instruction_t * inst, decod_param_t * param)
1470	{
1471	log_printf(TRACE,Decod,"instruction_l_psync"," * instruction : l.psync");
1472
1473	if (range<uint32_t>(inst->_instruction,22, 0) != 0)
1474	{
1475	instruction_illegal (inst, param);
1476	}
1477	else
1478	{
1479	inst->_type = TYPE_SPECIAL;
1480	inst->_operation = OPERATION_SPECIAL_L_PSYNC;
1481	inst->_has_immediat = 0;
1482	// inst->_immediat = ;
1483	inst->_read_ra = 0;
1484	// inst->_num_reg_ra = ;
1485	inst->_read_rb = 0;
1486	// inst->_num_reg_rb = ;
1487	inst->_read_rc = 0;
1488	// inst->_num_reg_rc = ;
1489	inst->_write_rd = 0;
1490	// inst->_num_reg_rd = ;
1491	inst->_write_re = 0;
1492	// inst->_num_reg_re = ;
1493	inst->_exception_use = EXCEPTION_USE_NONE;
1494	// inst->_branch_condition = ;
1495	// inst->_branch_stack_write = ;
1496	// inst->_branch_direction = ;
1497	// inst->_address_next = ; // don't change
1498	inst->_event_type = EVENT_TYPE_PSYNC;
1499	}
1500	}
1501
1502	void instruction_l_rfe (decod_instruction_t * inst, decod_param_t * param)
1503	{
1504	log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe");
1505
1506	inst->_type = TYPE_SPECIAL;
1507	inst->_operation = OPERATION_SPECIAL_L_RFE;
1508	inst->_has_immediat = 0;
1509	// inst->_immediat = ;
1510	inst->_read_ra = 0;
1511	// inst->_num_reg_ra = ;
1512	inst->_read_rb = 0;
1513	// inst->_num_reg_rb = ;
1514	inst->_read_rc = 0;
1515	// inst->_num_reg_rc = ;
1516	inst->_write_rd = 0;
1517	// inst->_num_reg_rd = ;
1518	inst->_write_re = 0;
1519	// inst->_num_reg_re = ;
1520	inst->_exception_use = EXCEPTION_USE_NONE;
1521	// inst->_branch_condition = ;
1522	// inst->_branch_stack_write = ;
1523	// inst->_branch_direction = ;
1524	// inst->_address_next = ; // don't change
1525	inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage
1526	}
1527
1528	void instruction_l_ror (decod_instruction_t * inst, decod_param_t * param)
1529	{
1530	log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror");
1531
1532	inst->_type = TYPE_SHIFT;
1533	inst->_operation = OPERATION_SHIFT_L_ROR;
1534	inst->_has_immediat = 0;
1535	// inst->_immediat = ;
1536	inst->_read_ra = 1;
1537	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1538	inst->_read_rb = 1;
1539	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1540	inst->_read_rc = 0;
1541	// inst->_num_reg_rc = ;
1542	inst->_write_rd = 1;
1543	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1544	inst->_write_re = 0;
1545	// inst->_num_reg_re = ;
1546	inst->_exception_use = EXCEPTION_USE_NONE;
1547	// inst->_branch_condition = ;
1548	// inst->_branch_stack_write = ;
1549	// inst->_branch_direction = ;
1550	// inst->_address_next = ;
1551	inst->_event_type = EVENT_TYPE_NONE;
1552	}
1553
1554	void instruction_l_rori (decod_instruction_t * inst, decod_param_t * param)
1555	{
1556	log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori");
1557
1558	inst->_type = TYPE_SHIFT;
1559	inst->_operation = OPERATION_SHIFT_L_ROR;
1560	inst->_has_immediat = 1;
1561	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
1562	inst->_read_ra = 1;
1563	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1564	inst->_read_rb = 0;
1565	// inst->_num_reg_rb = ;
1566	inst->_read_rc = 0;
1567	// inst->_num_reg_rc = ;
1568	inst->_write_rd = 1;
1569	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1570	inst->_write_re = 0;
1571	// inst->_num_reg_re = ;
1572	inst->_exception_use = EXCEPTION_USE_NONE;
1573	// inst->_branch_condition = ;
1574	// inst->_branch_stack_write = ;
1575	// inst->_branch_direction = ;
1576	// inst->_address_next = ;
1577	inst->_event_type = EVENT_TYPE_NONE;
1578	}
1579
1580	void instruction_l_sb (decod_instruction_t * inst, decod_param_t * param)
1581	{
1582	log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb");
1583
1584	inst->_type = TYPE_MEMORY;
1585	inst->_operation = OPERATION_MEMORY_STORE_8;
1586	inst->_has_immediat = 1;
1587	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
1588	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
1589	inst->_read_ra = 1;
1590	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1591	inst->_read_rb = 1;
1592	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1593	inst->_read_rc = 0;
1594	// inst->_num_reg_rc = ;
1595	inst->_write_rd = 0;
1596	// inst->_num_reg_rd = ;
1597	inst->_write_re = 0;
1598	// inst->_num_reg_re = ;
1599	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
1600	// inst->_branch_condition = ;
1601	// inst->_branch_stack_write = ;
1602	// inst->_branch_direction = ;
1603	// inst->_address_next = ;
1604	inst->_event_type = EVENT_TYPE_NONE;
1605	}
1606
1607	void instruction_l_sd (decod_instruction_t * inst, decod_param_t * param)
1608	{
1609	log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb");
1610
1611	inst->_type = TYPE_MEMORY;
1612	inst->_operation = OPERATION_MEMORY_STORE_64;
1613	inst->_has_immediat = 1;
1614	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
1615	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
1616	inst->_read_ra = 1;
1617	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1618	inst->_read_rb = 1;
1619	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1620	inst->_read_rc = 0;
1621	// inst->_num_reg_rc = ;
1622	inst->_write_rd = 0;
1623	// inst->_num_reg_rd = ;
1624	inst->_write_re = 0;
1625	// inst->_num_reg_re = ;
1626	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1627	// inst->_branch_condition = ;
1628	// inst->_branch_stack_write = ;
1629	// inst->_branch_direction = ;
1630	// inst->_address_next = ;
1631	inst->_event_type = EVENT_TYPE_NONE;
1632	}
1633
1634	void instruction_l_sfeq (decod_instruction_t * inst, decod_param_t * param)
1635	{
1636	log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq");
1637
1638	inst->_type = TYPE_TEST;
1639	inst->_operation = OPERATION_TEST_L_SFEQ;
1640	inst->_has_immediat = 0;
1641	// inst->_immediat = ;
1642	inst->_read_ra = 1;
1643	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1644	inst->_read_rb = 1;
1645	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1646	inst->_read_rc = 0;
1647	// inst->_num_reg_rc = ;
1648	inst->_write_rd = 0;
1649	// inst->_num_reg_rd = ;
1650	inst->_write_re = 1;
1651	inst->_num_reg_re = SPR_LOGIC_SR_F;
1652	inst->_exception_use = EXCEPTION_USE_NONE;
1653	// inst->_branch_condition = ;
1654	// inst->_branch_stack_write = ;
1655	// inst->_branch_direction = ;
1656	// inst->_address_next = ;
1657	inst->_event_type = EVENT_TYPE_NONE;
1658	}
1659
1660	void instruction_l_sfeqi (decod_instruction_t * inst, decod_param_t * param)
1661	{
1662	log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi");
1663
1664	inst->_type = TYPE_TEST;
1665	inst->_operation = OPERATION_TEST_L_SFEQ;
1666	inst->_has_immediat = 1;
1667	inst->_immediat = EXTENDS(inst->_instruction,16);
1668	inst->_read_ra = 1;
1669	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1670	inst->_read_rb = 0;
1671	// inst->_num_reg_rb = ;
1672	inst->_read_rc = 0;
1673	// inst->_num_reg_rc = ;
1674	inst->_write_rd = 0;
1675	// inst->_num_reg_rd = ;
1676	inst->_write_re = 1;
1677	inst->_num_reg_re = SPR_LOGIC_SR_F;
1678	inst->_exception_use = EXCEPTION_USE_NONE;
1679	// inst->_branch_condition = ;
1680	// inst->_branch_stack_write = ;
1681	// inst->_branch_direction = ;
1682	// inst->_address_next = ;
1683	inst->_event_type = EVENT_TYPE_NONE;
1684	}
1685
1686	void instruction_l_sfges (decod_instruction_t * inst, decod_param_t * param)
1687	{
1688	log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges");
1689
1690	inst->_type = TYPE_TEST;
1691	inst->_operation = OPERATION_TEST_L_SFGES;
1692	inst->_has_immediat = 0;
1693	// inst->_immediat = ;
1694	inst->_read_ra = 1;
1695	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1696	inst->_read_rb = 1;
1697	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1698	inst->_read_rc = 0;
1699	// inst->_num_reg_rc = ;
1700	inst->_write_rd = 0;
1701	// inst->_num_reg_rd = ;
1702	inst->_write_re = 1;
1703	inst->_num_reg_re = SPR_LOGIC_SR_F;
1704	inst->_exception_use = EXCEPTION_USE_NONE;
1705	// inst->_branch_condition = ;
1706	// inst->_branch_stack_write = ;
1707	// inst->_branch_direction = ;
1708	// inst->_address_next = ;
1709	inst->_event_type = EVENT_TYPE_NONE;
1710	}
1711
1712	void instruction_l_sfgesi (decod_instruction_t * inst, decod_param_t * param)
1713	{
1714	log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi");
1715
1716	inst->_type = TYPE_TEST;
1717	inst->_operation = OPERATION_TEST_L_SFGES;
1718	inst->_has_immediat = 1;
1719	inst->_immediat = EXTENDS(inst->_instruction,16);
1720	inst->_read_ra = 1;
1721	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1722	inst->_read_rb = 0;
1723	// inst->_num_reg_rb = ;
1724	inst->_read_rc = 0;
1725	// inst->_num_reg_rc = ;
1726	inst->_write_rd = 0;
1727	// inst->_num_reg_rd = ;
1728	inst->_write_re = 1;
1729	inst->_num_reg_re = SPR_LOGIC_SR_F;
1730	inst->_exception_use = EXCEPTION_USE_NONE;
1731	// inst->_branch_condition = ;
1732	// inst->_branch_stack_write = ;
1733	// inst->_branch_direction = ;
1734	// inst->_address_next = ;
1735	inst->_event_type = EVENT_TYPE_NONE;
1736	}
1737
1738	void instruction_l_sfgeu (decod_instruction_t * inst, decod_param_t * param)
1739	{
1740	log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu");
1741
1742	inst->_type = TYPE_TEST;
1743	inst->_operation = OPERATION_TEST_L_SFGEU;
1744	inst->_has_immediat = 0;
1745	// inst->_immediat = ;
1746	inst->_read_ra = 1;
1747	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1748	inst->_read_rb = 1;
1749	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1750	inst->_read_rc = 0;
1751	// inst->_num_reg_rc = ;
1752	inst->_write_rd = 0;
1753	// inst->_num_reg_rd = ;
1754	inst->_write_re = 1;
1755	inst->_num_reg_re = SPR_LOGIC_SR_F;
1756	inst->_exception_use = EXCEPTION_USE_NONE;
1757	// inst->_branch_condition = ;
1758	// inst->_branch_stack_write = ;
1759	// inst->_branch_direction = ;
1760	// inst->_address_next = ;
1761	inst->_event_type = EVENT_TYPE_NONE;
1762	}
1763
1764	void instruction_l_sfgeui (decod_instruction_t * inst, decod_param_t * param)
1765	{
1766	log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui");
1767
1768	inst->_type = TYPE_TEST;
1769	inst->_operation = OPERATION_TEST_L_SFGEU;
1770	inst->_has_immediat = 1;
1771	inst->_immediat = EXTENDS(inst->_instruction,16);
1772	inst->_read_ra = 1;
1773	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1774	inst->_read_rb = 0;
1775	// inst->_num_reg_rb = ;
1776	inst->_read_rc = 0;
1777	// inst->_num_reg_rc = ;
1778	inst->_write_rd = 0;
1779	// inst->_num_reg_rd = ;
1780	inst->_write_re = 1;
1781	inst->_num_reg_re = SPR_LOGIC_SR_F;
1782	inst->_exception_use = EXCEPTION_USE_NONE;
1783	// inst->_branch_condition = ;
1784	// inst->_branch_stack_write = ;
1785	// inst->_branch_direction = ;
1786	// inst->_address_next = ;
1787	inst->_event_type = EVENT_TYPE_NONE;
1788	}
1789
1790	void instruction_l_sfgts (decod_instruction_t * inst, decod_param_t * param)
1791	{
1792	log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts");
1793
1794	inst->_type = TYPE_TEST;
1795	inst->_operation = OPERATION_TEST_L_SFGTS;
1796	inst->_has_immediat = 0;
1797	// inst->_immediat = ;
1798	inst->_read_ra = 1;
1799	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1800	inst->_read_rb = 1;
1801	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1802	inst->_read_rc = 0;
1803	// inst->_num_reg_rc = ;
1804	inst->_write_rd = 0;
1805	// inst->_num_reg_rd = ;
1806	inst->_write_re = 1;
1807	inst->_num_reg_re = SPR_LOGIC_SR_F;
1808	inst->_exception_use = EXCEPTION_USE_NONE;
1809	// inst->_branch_condition = ;
1810	// inst->_branch_stack_write = ;
1811	// inst->_branch_direction = ;
1812	// inst->_address_next = ;
1813	inst->_event_type = EVENT_TYPE_NONE;
1814	}
1815
1816	void instruction_l_sfgtsi (decod_instruction_t * inst, decod_param_t * param)
1817	{
1818	log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi");
1819
1820	inst->_type = TYPE_TEST;
1821	inst->_operation = OPERATION_TEST_L_SFGTS;
1822	inst->_has_immediat = 1;
1823	inst->_immediat = EXTENDS(inst->_instruction,16);
1824	inst->_read_ra = 1;
1825	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1826	inst->_read_rb = 0;
1827	// inst->_num_reg_rb = ;
1828	inst->_read_rc = 0;
1829	// inst->_num_reg_rc = ;
1830	inst->_write_rd = 0;
1831	// inst->_num_reg_rd = ;
1832	inst->_write_re = 1;
1833	inst->_num_reg_re = SPR_LOGIC_SR_F;
1834	inst->_exception_use = EXCEPTION_USE_NONE;
1835	// inst->_branch_condition = ;
1836	// inst->_branch_stack_write = ;
1837	// inst->_branch_direction = ;
1838	// inst->_address_next = ;
1839	inst->_event_type = EVENT_TYPE_NONE;
1840	}
1841
1842	void instruction_l_sfgtu (decod_instruction_t * inst, decod_param_t * param)
1843	{
1844	log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu");
1845
1846	inst->_type = TYPE_TEST;
1847	inst->_operation = OPERATION_TEST_L_SFGTU;
1848	inst->_has_immediat = 0;
1849	// inst->_immediat = ;
1850	inst->_read_ra = 1;
1851	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1852	inst->_read_rb = 1;
1853	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1854	inst->_read_rc = 0;
1855	// inst->_num_reg_rc = ;
1856	inst->_write_rd = 0;
1857	// inst->_num_reg_rd = ;
1858	inst->_write_re = 1;
1859	inst->_num_reg_re = SPR_LOGIC_SR_F;
1860	inst->_exception_use = EXCEPTION_USE_NONE;
1861	// inst->_branch_condition = ;
1862	// inst->_branch_stack_write = ;
1863	// inst->_branch_direction = ;
1864	// inst->_address_next = ;
1865	inst->_event_type = EVENT_TYPE_NONE;
1866	}
1867
1868	void instruction_l_sfgtui (decod_instruction_t * inst, decod_param_t * param)
1869	{
1870	log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui");
1871
1872	inst->_type = TYPE_TEST;
1873	inst->_operation = OPERATION_TEST_L_SFGTU;
1874	inst->_has_immediat = 1;
1875	inst->_immediat = EXTENDS(inst->_instruction,16);
1876	inst->_read_ra = 1;
1877	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1878	inst->_read_rb = 0;
1879	// inst->_num_reg_rb = ;
1880	inst->_read_rc = 0;
1881	// inst->_num_reg_rc = ;
1882	inst->_write_rd = 0;
1883	// inst->_num_reg_rd = ;
1884	inst->_write_re = 1;
1885	inst->_num_reg_re = SPR_LOGIC_SR_F;
1886	inst->_exception_use = EXCEPTION_USE_NONE;
1887	// inst->_branch_condition = ;
1888	// inst->_branch_stack_write = ;
1889	// inst->_branch_direction = ;
1890	// inst->_address_next = ;
1891	inst->_event_type = EVENT_TYPE_NONE;
1892	}
1893
1894	void instruction_l_sfles (decod_instruction_t * inst, decod_param_t * param)
1895	{
1896	log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles");
1897
1898	inst->_type = TYPE_TEST;
1899	inst->_operation = OPERATION_TEST_L_SFLES;
1900	inst->_has_immediat = 0;
1901	// inst->_immediat = ;
1902	inst->_read_ra = 1;
1903	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1904	inst->_read_rb = 1;
1905	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1906	inst->_read_rc = 0;
1907	// inst->_num_reg_rc = ;
1908	inst->_write_rd = 0;
1909	// inst->_num_reg_rd = ;
1910	inst->_write_re = 1;
1911	inst->_num_reg_re = SPR_LOGIC_SR_F;
1912	inst->_exception_use = EXCEPTION_USE_NONE;
1913	// inst->_branch_condition = ;
1914	// inst->_branch_stack_write = ;
1915	// inst->_branch_direction = ;
1916	// inst->_address_next = ;
1917	inst->_event_type = EVENT_TYPE_NONE;
1918	}
1919
1920	void instruction_l_sflesi (decod_instruction_t * inst, decod_param_t * param)
1921	{
1922	log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi");
1923
1924	inst->_type = TYPE_TEST;
1925	inst->_operation = OPERATION_TEST_L_SFLES;
1926	inst->_has_immediat = 1;
1927	inst->_immediat = EXTENDS(inst->_instruction,16);
1928	inst->_read_ra = 1;
1929	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1930	inst->_read_rb = 0;
1931	// inst->_num_reg_rb = ;
1932	inst->_read_rc = 0;
1933	// inst->_num_reg_rc = ;
1934	inst->_write_rd = 0;
1935	// inst->_num_reg_rd = ;
1936	inst->_write_re = 1;
1937	inst->_num_reg_re = SPR_LOGIC_SR_F;
1938	inst->_exception_use = EXCEPTION_USE_NONE;
1939	// inst->_branch_condition = ;
1940	// inst->_branch_stack_write = ;
1941	// inst->_branch_direction = ;
1942	// inst->_address_next = ;
1943	inst->_event_type = EVENT_TYPE_NONE;
1944	}
1945
1946	void instruction_l_sfleu (decod_instruction_t * inst, decod_param_t * param)
1947	{
1948	log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu");
1949
1950	inst->_type = TYPE_TEST;
1951	inst->_operation = OPERATION_TEST_L_SFLEU;
1952	inst->_has_immediat = 0;
1953	// inst->_immediat = ;
1954	inst->_read_ra = 1;
1955	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1956	inst->_read_rb = 1;
1957	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1958	inst->_read_rc = 0;
1959	// inst->_num_reg_rc = ;
1960	inst->_write_rd = 0;
1961	// inst->_num_reg_rd = ;
1962	inst->_write_re = 1;
1963	inst->_num_reg_re = SPR_LOGIC_SR_F;
1964	inst->_exception_use = EXCEPTION_USE_NONE;
1965	// inst->_branch_condition = ;
1966	// inst->_branch_stack_write = ;
1967	// inst->_branch_direction = ;
1968	// inst->_address_next = ;
1969	inst->_event_type = EVENT_TYPE_NONE;
1970	}
1971
1972	void instruction_l_sfleui (decod_instruction_t * inst, decod_param_t * param)
1973	{
1974	log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui");
1975
1976	inst->_type = TYPE_TEST;
1977	inst->_operation = OPERATION_TEST_L_SFLEU;
1978	inst->_has_immediat = 1;
1979	inst->_immediat = EXTENDS(inst->_instruction,16);
1980	inst->_read_ra = 1;
1981	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1982	inst->_read_rb = 0;
1983	// inst->_num_reg_rb = ;
1984	inst->_read_rc = 0;
1985	// inst->_num_reg_rc = ;
1986	inst->_write_rd = 0;
1987	// inst->_num_reg_rd = ;
1988	inst->_write_re = 1;
1989	inst->_num_reg_re = SPR_LOGIC_SR_F;
1990	inst->_exception_use = EXCEPTION_USE_NONE;
1991	// inst->_branch_condition = ;
1992	// inst->_branch_stack_write = ;
1993	// inst->_branch_direction = ;
1994	// inst->_address_next = ;
1995	inst->_event_type = EVENT_TYPE_NONE;
1996	}
1997
1998	void instruction_l_sflts (decod_instruction_t * inst, decod_param_t * param)
1999	{
2000	log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts");
2001
2002	inst->_type = TYPE_TEST;
2003	inst->_operation = OPERATION_TEST_L_SFLTS;
2004	inst->_has_immediat = 0;
2005	// inst->_immediat = ;
2006	inst->_read_ra = 1;
2007	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2008	inst->_read_rb = 1;
2009	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2010	inst->_read_rc = 0;
2011	// inst->_num_reg_rc = ;
2012	inst->_write_rd = 0;
2013	// inst->_num_reg_rd = ;
2014	inst->_write_re = 1;
2015	inst->_num_reg_re = SPR_LOGIC_SR_F;
2016	inst->_exception_use = EXCEPTION_USE_NONE;
2017	// inst->_branch_condition = ;
2018	// inst->_branch_stack_write = ;
2019	// inst->_branch_direction = ;
2020	// inst->_address_next = ;
2021	inst->_event_type = EVENT_TYPE_NONE;
2022	}
2023
2024	void instruction_l_sfltsi (decod_instruction_t * inst, decod_param_t * param)
2025	{
2026	log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi");
2027
2028	inst->_type = TYPE_TEST;
2029	inst->_operation = OPERATION_TEST_L_SFLTS;
2030	inst->_has_immediat = 1;
2031	inst->_immediat = EXTENDS(inst->_instruction,16);
2032	inst->_read_ra = 1;
2033	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2034	inst->_read_rb = 0;
2035	// inst->_num_reg_rb = ;
2036	inst->_read_rc = 0;
2037	// inst->_num_reg_rc = ;
2038	inst->_write_rd = 0;
2039	// inst->_num_reg_rd = ;
2040	inst->_write_re = 1;
2041	inst->_num_reg_re = SPR_LOGIC_SR_F;
2042	inst->_exception_use = EXCEPTION_USE_NONE;
2043	// inst->_branch_condition = ;
2044	// inst->_branch_stack_write = ;
2045	// inst->_branch_direction = ;
2046	// inst->_address_next = ;
2047	inst->_event_type = EVENT_TYPE_NONE;
2048	}
2049
2050	void instruction_l_sfltu (decod_instruction_t * inst, decod_param_t * param)
2051	{
2052	log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu");
2053
2054	inst->_type = TYPE_TEST;
2055	inst->_operation = OPERATION_TEST_L_SFLTU;
2056	inst->_has_immediat = 0;
2057	// inst->_immediat = ;
2058	inst->_read_ra = 1;
2059	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2060	inst->_read_rb = 1;
2061	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2062	inst->_read_rc = 0;
2063	// inst->_num_reg_rc = ;
2064	inst->_write_rd = 0;
2065	// inst->_num_reg_rd = ;
2066	inst->_write_re = 1;
2067	inst->_num_reg_re = SPR_LOGIC_SR_F;
2068	inst->_exception_use = EXCEPTION_USE_NONE;
2069	// inst->_branch_condition = ;
2070	// inst->_branch_stack_write = ;
2071	// inst->_branch_direction = ;
2072	// inst->_address_next = ;
2073	inst->_event_type = EVENT_TYPE_NONE;
2074	}
2075
2076	void instruction_l_sfltui (decod_instruction_t * inst, decod_param_t * param)
2077	{
2078	log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui");
2079
2080	inst->_type = TYPE_TEST;
2081	inst->_operation = OPERATION_TEST_L_SFLTU;
2082	inst->_has_immediat = 1;
2083	inst->_immediat = EXTENDS(inst->_instruction,16);
2084	inst->_read_ra = 1;
2085	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2086	inst->_read_rb = 0;
2087	// inst->_num_reg_rb = ;
2088	inst->_read_rc = 0;
2089	// inst->_num_reg_rc = ;
2090	inst->_write_rd = 0;
2091	// inst->_num_reg_rd = ;
2092	inst->_write_re = 1;
2093	inst->_num_reg_re = SPR_LOGIC_SR_F;
2094	inst->_exception_use = EXCEPTION_USE_NONE;
2095	// inst->_branch_condition = ;
2096	// inst->_branch_stack_write = ;
2097	// inst->_branch_direction = ;
2098	// inst->_address_next = ;
2099	inst->_event_type = EVENT_TYPE_NONE;
2100	}
2101
2102	void instruction_l_sfne (decod_instruction_t * inst, decod_param_t * param)
2103	{
2104	log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne");
2105
2106	inst->_type = TYPE_TEST;
2107	inst->_operation = OPERATION_TEST_L_SFNE;
2108	inst->_has_immediat = 0;
2109	// inst->_immediat = ;
2110	inst->_read_ra = 1;
2111	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2112	inst->_read_rb = 1;
2113	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2114	inst->_read_rc = 0;
2115	// inst->_num_reg_rc = ;
2116	inst->_write_rd = 0;
2117	// inst->_num_reg_rd = ;
2118	inst->_write_re = 1;
2119	inst->_num_reg_re = SPR_LOGIC_SR_F;
2120	inst->_exception_use = EXCEPTION_USE_NONE;
2121	// inst->_branch_condition = ;
2122	// inst->_branch_stack_write = ;
2123	// inst->_branch_direction = ;
2124	// inst->_address_next = ;
2125	inst->_event_type = EVENT_TYPE_NONE;
2126	}
2127
2128	void instruction_l_sfnei (decod_instruction_t * inst, decod_param_t * param)
2129	{
2130	log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei");
2131
2132	inst->_type = TYPE_TEST;
2133	inst->_operation = OPERATION_TEST_L_SFNE;
2134	inst->_has_immediat = 1;
2135	inst->_immediat = EXTENDS(inst->_instruction,16);
2136	inst->_read_ra = 1;
2137	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2138	inst->_read_rb = 0;
2139	// inst->_num_reg_rb = ;
2140	inst->_read_rc = 0;
2141	// inst->_num_reg_rc = ;
2142	inst->_write_rd = 0;
2143	// inst->_num_reg_rd = ;
2144	inst->_write_re = 1;
2145	inst->_num_reg_re = SPR_LOGIC_SR_F;
2146	inst->_exception_use = EXCEPTION_USE_NONE;
2147	// inst->_branch_condition = ;
2148	// inst->_branch_stack_write = ;
2149	// inst->_branch_direction = ;
2150	// inst->_address_next = ;
2151	inst->_event_type = EVENT_TYPE_NONE;
2152	}
2153
2154	void instruction_l_sh (decod_instruction_t * inst, decod_param_t * param)
2155	{
2156	log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh");
2157
2158	inst->_type = TYPE_MEMORY;
2159	inst->_operation = OPERATION_MEMORY_STORE_16;
2160	inst->_has_immediat = 1;
2161	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
2162	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
2163	inst->_read_ra = 1;
2164	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2165	inst->_read_rb = 1;
2166	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2167	inst->_read_rc = 0;
2168	// inst->_num_reg_rc = ;
2169	inst->_write_rd = 0;
2170	// inst->_num_reg_rd = ;
2171	inst->_write_re = 0;
2172	// inst->_num_reg_re = ;
2173	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
2174	// inst->_branch_condition = ;
2175	// inst->_branch_stack_write = ;
2176	// inst->_branch_direction = ;
2177	// inst->_address_next = ;
2178	inst->_event_type = EVENT_TYPE_NONE;
2179	}
2180
2181	void instruction_l_sll (decod_instruction_t * inst, decod_param_t * param)
2182	{
2183	log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll");
2184
2185	inst->_type = TYPE_SHIFT;
2186	inst->_operation = OPERATION_SHIFT_L_SLL;
2187	inst->_has_immediat = 0;
2188	// inst->_immediat = ;
2189	inst->_read_ra = 1;
2190	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2191	inst->_read_rb = 1;
2192	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2193	inst->_read_rc = 0;
2194	// inst->_num_reg_rc = ;
2195	inst->_write_rd = 1;
2196	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2197	inst->_write_re = 0;
2198	// inst->_num_reg_re = ;
2199	inst->_exception_use = EXCEPTION_USE_NONE;
2200	// inst->_branch_condition = ;
2201	// inst->_branch_stack_write = ;
2202	// inst->_branch_direction = ;
2203	// inst->_address_next = ;
2204	inst->_event_type = EVENT_TYPE_NONE;
2205	}
2206
2207	void instruction_l_slli (decod_instruction_t * inst, decod_param_t * param)
2208	{
2209	log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli");
2210
2211	inst->_type = TYPE_SHIFT;
2212	inst->_operation = OPERATION_SHIFT_L_SLL;
2213	inst->_has_immediat = 1;
2214	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
2215	inst->_read_ra = 1;
2216	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2217	inst->_read_rb = 0;
2218	// inst->_num_reg_rb = ;
2219	inst->_read_rc = 0;
2220	// inst->_num_reg_rc = ;
2221	inst->_write_rd = 1;
2222	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2223	inst->_write_re = 0;
2224	// inst->_num_reg_re = ;
2225	inst->_exception_use = EXCEPTION_USE_NONE;
2226	// inst->_branch_condition = ;
2227	// inst->_branch_stack_write = ;
2228	// inst->_branch_direction = ;
2229	// inst->_address_next = ;
2230	inst->_event_type = EVENT_TYPE_NONE;
2231	}
2232
2233	void instruction_l_sra (decod_instruction_t * inst, decod_param_t * param)
2234	{
2235	log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra");
2236
2237	inst->_type = TYPE_SHIFT;
2238	inst->_operation = OPERATION_SHIFT_L_SRA;
2239	inst->_has_immediat = 0;
2240	// inst->_immediat = ;
2241	inst->_read_ra = 1;
2242	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2243	inst->_read_rb = 1;
2244	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2245	inst->_read_rc = 0;
2246	// inst->_num_reg_rc = ;
2247	inst->_write_rd = 1;
2248	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2249	inst->_write_re = 0;
2250	// inst->_num_reg_re = ;
2251	inst->_exception_use = EXCEPTION_USE_NONE;
2252	// inst->_branch_condition = ;
2253	// inst->_branch_stack_write = ;
2254	// inst->_branch_direction = ;
2255	// inst->_address_next = ;
2256	inst->_event_type = EVENT_TYPE_NONE;
2257	}
2258
2259	void instruction_l_srai (decod_instruction_t * inst, decod_param_t * param)
2260	{
2261	log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai");
2262
2263	inst->_type = TYPE_SHIFT;
2264	inst->_operation = OPERATION_SHIFT_L_SRA;
2265	inst->_has_immediat = 1;
2266	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
2267	inst->_read_ra = 1;
2268	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2269	inst->_read_rb = 0;
2270	// inst->_num_reg_rb = ;
2271	inst->_read_rc = 0;
2272	// inst->_num_reg_rc = ;
2273	inst->_write_rd = 1;
2274	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2275	inst->_write_re = 0;
2276	// inst->_num_reg_re = ;
2277	inst->_exception_use = EXCEPTION_USE_NONE;
2278	// inst->_branch_condition = ;
2279	// inst->_branch_stack_write = ;
2280	// inst->_branch_direction = ;
2281	// inst->_address_next = ;
2282	inst->_event_type = EVENT_TYPE_NONE;
2283	}
2284
2285	void instruction_l_srl (decod_instruction_t * inst, decod_param_t * param)
2286	{
2287	log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl");
2288
2289	inst->_type = TYPE_SHIFT;
2290	inst->_operation = OPERATION_SHIFT_L_SRL;
2291	inst->_has_immediat = 0;
2292	// inst->_immediat = ;
2293	inst->_read_ra = 1;
2294	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2295	inst->_read_rb = 1;
2296	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2297	inst->_read_rc = 0;
2298	// inst->_num_reg_rc = ;
2299	inst->_write_rd = 1;
2300	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2301	inst->_write_re = 0;
2302	// inst->_num_reg_re = ;
2303	inst->_exception_use = EXCEPTION_USE_NONE;
2304	// inst->_branch_condition = ;
2305	// inst->_branch_stack_write = ;
2306	// inst->_branch_direction = ;
2307	// inst->_address_next = ;
2308	inst->_event_type = EVENT_TYPE_NONE;
2309	}
2310
2311	void instruction_l_srli (decod_instruction_t * inst, decod_param_t * param)
2312	{
2313	log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli");
2314
2315	inst->_type = TYPE_SHIFT;
2316	inst->_operation = OPERATION_SHIFT_L_SRL;
2317	inst->_has_immediat = 1;
2318	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
2319	inst->_read_ra = 1;
2320	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2321	inst->_read_rb = 0;
2322	// inst->_num_reg_rb = ;
2323	inst->_read_rc = 0;
2324	// inst->_num_reg_rc = ;
2325	inst->_write_rd = 1;
2326	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2327	inst->_write_re = 0;
2328	// inst->_num_reg_re = ;
2329	inst->_exception_use = EXCEPTION_USE_NONE;
2330	// inst->_branch_condition = ;
2331	// inst->_branch_stack_write = ;
2332	// inst->_branch_direction = ;
2333	// inst->_address_next = ;
2334	inst->_event_type = EVENT_TYPE_NONE;
2335	}
2336
2337	void instruction_l_sub (decod_instruction_t * inst, decod_param_t * param)
2338	{
2339	log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub");
2340
2341	inst->_type = TYPE_ALU;
2342	inst->_operation = OPERATION_ALU_L_SUB;
2343	inst->_has_immediat = 0;
2344	// inst->_immediat = ;
2345	inst->_read_ra = 1;
2346	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2347	inst->_read_rb = 1;
2348	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2349	inst->_read_rc = 0;
2350	// inst->_num_reg_rc = ;
2351	inst->_write_rd = 1;
2352	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2353	inst->_write_re = 1;
2354	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
2355	inst->_exception_use = EXCEPTION_USE_RANGE;
2356	// inst->_branch_condition = ;
2357	// inst->_branch_stack_write = ;
2358	// inst->_branch_direction = ;
2359	// inst->_address_next = ;
2360	inst->_event_type = EVENT_TYPE_NONE;
2361	}
2362
2363	void instruction_l_sw (decod_instruction_t * inst, decod_param_t * param)
2364	{
2365	log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw");
2366
2367	inst->_type = TYPE_MEMORY;
2368	inst->_operation = OPERATION_MEMORY_STORE_32;
2369	inst->_has_immediat = 1;
2370	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
2371	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
2372	inst->_read_ra = 1;
2373	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2374	inst->_read_rb = 1;
2375	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2376	inst->_read_rc = 0;
2377	// inst->_num_reg_rc = ;
2378	inst->_write_rd = 0;
2379	// inst->_num_reg_rd = ;
2380	inst->_write_re = 0;
2381	// inst->_num_reg_re = ;
2382	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
2383	// inst->_branch_condition = ;
2384	// inst->_branch_stack_write = ;
2385	// inst->_branch_direction = ;
2386	// inst->_address_next = ;
2387	inst->_event_type = EVENT_TYPE_NONE;
2388	}
2389
2390	void instruction_l_sys (decod_instruction_t * inst, decod_param_t * param)
2391	{
2392	log_printf(TRACE,Decod,"instruction_l_sys"," * instruction : l.sys");
2393
2394	if (range<uint32_t>(inst->_instruction,22,16) != 0)
2395	{
2396	instruction_illegal (inst, param);
2397	}
2398	else
2399	{
2400	inst->_type = TYPE_SPECIAL;
2401	inst->_operation = OPERATION_SPECIAL_L_SYS;
2402	// inst->_has_immediat = 1;
2403	// inst->_immediat = EXTENDZ(inst->_instruction,16);
2404	inst->_has_immediat = 0;
2405	// inst->_immediat = ;
2406	inst->_read_ra = 0;
2407	// inst->_num_reg_ra = ;
2408	inst->_read_rb = 0;
2409	// inst->_num_reg_rb = ;
2410	inst->_read_rc = 0;
2411	// inst->_num_reg_rc = ;
2412	inst->_write_rd = 0;
2413	// inst->_num_reg_rd = ;
2414	inst->_write_re = 0;
2415	// inst->_num_reg_re = ;
2416	inst->_exception_use = EXCEPTION_USE_SYSCALL;
2417	// inst->_branch_condition = ;
2418	// inst->_branch_stack_write = ;
2419	// inst->_branch_direction = ;
2420
2421	// if (inst->_is_delay_slot)
2422	// inst->_address_next = inst->_address_previous;
2423	// else
2424	// inst->_address_next = inst->_address;
2425
2426
2427	// inst->_address_next = ; // don't change
2428	inst->_event_type = EVENT_TYPE_EXCEPTION;
2429	}
2430	}
2431
2432	void instruction_l_trap (decod_instruction_t * inst, decod_param_t * param)
2433	{
2434	log_printf(TRACE,Decod,"instruction_l_trap"," * instruction : l.trap");
2435
2436	if (range<uint32_t>(inst->_instruction,22,16) != 0)
2437	{
2438	instruction_illegal (inst, param);
2439	}
2440	else
2441	{
2442	inst->_type = TYPE_SPECIAL;
2443	inst->_operation = OPERATION_SPECIAL_L_TRAP;
2444	inst->_has_immediat = 1;
2445	inst->_immediat = EXTENDZ(inst->_instruction,16);
2446	inst->_read_ra = 0;
2447	// inst->_num_reg_ra = ;
2448	inst->_read_rb = 0;
2449	// inst->_num_reg_rb = ;
2450	inst->_read_rc = 0; // read all SR
2451	// inst->_num_reg_rc = ;
2452	inst->_write_rd = 0;
2453	// inst->_num_reg_rd = ;
2454	inst->_write_re = 0;
2455	// inst->_num_reg_re = ;
2456	inst->_exception_use = EXCEPTION_USE_TRAP;
2457	// inst->_branch_condition = ;
2458	// inst->_branch_stack_write = ;
2459	// inst->_branch_direction = ;
2460	// inst->_address_next = ;
2461	inst->_event_type = EVENT_TYPE_NONE;
2462	}
2463	}
2464
2465	void instruction_l_xor (decod_instruction_t * inst, decod_param_t * param)
2466	{
2467	log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor");
2468
2469	inst->_type = TYPE_ALU;
2470	inst->_operation = OPERATION_ALU_L_XOR;
2471	inst->_has_immediat = 0;
2472	// inst->_immediat = ;
2473	inst->_read_ra = 1;
2474	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2475	inst->_read_rb = 1;
2476	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2477	inst->_read_rc = 0;
2478	// inst->_num_reg_rc = ;
2479	inst->_write_rd = 1;
2480	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2481	inst->_write_re = 0;
2482	// inst->_num_reg_re = ;
2483	inst->_exception_use = EXCEPTION_USE_NONE;
2484	// inst->_branch_condition = ;
2485	// inst->_branch_stack_write = ;
2486	// inst->_branch_direction = ;
2487	// inst->_address_next = ;
2488	inst->_event_type = EVENT_TYPE_NONE;
2489	}
2490
2491	void instruction_l_xori (decod_instruction_t * inst, decod_param_t * param)
2492	{
2493	log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori");
2494
2495	inst->_type = TYPE_ALU;
2496	inst->_operation = OPERATION_ALU_L_XOR;
2497	inst->_has_immediat = 1;
2498	inst->_immediat = EXTENDS(inst->_instruction,16);
2499	inst->_read_ra = 1;
2500	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2501	inst->_read_rb = 0;
2502	// inst->_num_reg_rb = ;
2503	inst->_read_rc = 0;
2504	// inst->_num_reg_rc = ;
2505	inst->_write_rd = 1;
2506	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2507	inst->_write_re = 0;
2508	// inst->_num_reg_re = ;
2509	inst->_exception_use = EXCEPTION_USE_NONE;
2510	// inst->_branch_condition = ;
2511	// inst->_branch_stack_write = ;
2512	// inst->_branch_direction = ;
2513	// inst->_address_next = ;
2514	inst->_event_type = EVENT_TYPE_NONE;
2515	}
2516
2517	// // ORFPX
2518	// void instruction_lf_add_d (decod_instruction_t * inst, decod_param_t * param)
2519	// void instruction_lf_add_s (decod_instruction_t * inst, decod_param_t * param)
2520	// void instruction_lf_cust1_d (decod_instruction_t * inst, decod_param_t * param)
2521	// void instruction_lf_cust1_s (decod_instruction_t * inst, decod_param_t * param)
2522	// void instruction_lf_div_d (decod_instruction_t * inst, decod_param_t * param)
2523	// void instruction_lf_div_s (decod_instruction_t * inst, decod_param_t * param)
2524	// void instruction_lf_ftoi_d (decod_instruction_t * inst, decod_param_t * param)
2525	// void instruction_lf_ftoi_s (decod_instruction_t * inst, decod_param_t * param)
2526	// void instruction_lf_itof_d (decod_instruction_t * inst, decod_param_t * param)
2527	// void instruction_lf_itof_s (decod_instruction_t * inst, decod_param_t * param)
2528	// void instruction_lf_madd_d (decod_instruction_t * inst, decod_param_t * param)
2529	// void instruction_lf_madd_s (decod_instruction_t * inst, decod_param_t * param)
2530	// void instruction_lf_mul_d (decod_instruction_t * inst, decod_param_t * param)
2531	// void instruction_lf_mul_s (decod_instruction_t * inst, decod_param_t * param)
2532	// void instruction_lf_rem_d (decod_instruction_t * inst, decod_param_t * param)
2533	// void instruction_lf_rem_s (decod_instruction_t * inst, decod_param_t * param)
2534	// void instruction_lf_sfeq_d (decod_instruction_t * inst, decod_param_t * param)
2535	// void instruction_lf_sfeq_s (decod_instruction_t * inst, decod_param_t * param)
2536	// void instruction_lf_sfge_d (decod_instruction_t * inst, decod_param_t * param)
2537	// void instruction_lf_sfge_s (decod_instruction_t * inst, decod_param_t * param)
2538	// void instruction_lf_sfgt_d (decod_instruction_t * inst, decod_param_t * param)
2539	// void instruction_lf_sfgt_s (decod_instruction_t * inst, decod_param_t * param)
2540	// void instruction_lf_sfle_d (decod_instruction_t * inst, decod_param_t * param)
2541	// void instruction_lf_sfle_s (decod_instruction_t * inst, decod_param_t * param)
2542	// void instruction_lf_sflt_d (decod_instruction_t * inst, decod_param_t * param)
2543	// void instruction_lf_sflt_s (decod_instruction_t * inst, decod_param_t * param)
2544	// void instruction_lf_sfne_d (decod_instruction_t * inst, decod_param_t * param)
2545	// void instruction_lf_sfne_s (decod_instruction_t * inst, decod_param_t * param)
2546	// void instruction_lf_sub_d (decod_instruction_t * inst, decod_param_t * param)
2547	// void instruction_lf_sub_s (decod_instruction_t * inst, decod_param_t * param)
2548
2549	// // ORVDX
2550	// void instruction_lv_add_b (decod_instruction_t * inst, decod_param_t * param)
2551	// void instruction_lv_add_h (decod_instruction_t * inst, decod_param_t * param)
2552	// void instruction_lv_adds_b (decod_instruction_t * inst, decod_param_t * param)
2553	// void instruction_lv_adds_h (decod_instruction_t * inst, decod_param_t * param)
2554	// void instruction_lv_addu_b (decod_instruction_t * inst, decod_param_t * param)
2555	// void instruction_lv_addu_h (decod_instruction_t * inst, decod_param_t * param)
2556	// void instruction_lv_addus_b (decod_instruction_t * inst, decod_param_t * param)
2557	// void instruction_lv_addus_h (decod_instruction_t * inst, decod_param_t * param)
2558	// void instruction_lv_all_eq_b (decod_instruction_t * inst, decod_param_t * param)
2559	// void instruction_lv_all_eq_h (decod_instruction_t * inst, decod_param_t * param)
2560	// void instruction_lv_all_ge_b (decod_instruction_t * inst, decod_param_t * param)
2561	// void instruction_lv_all_ge_h (decod_instruction_t * inst, decod_param_t * param)
2562	// void instruction_lv_all_gt_b (decod_instruction_t * inst, decod_param_t * param)
2563	// void instruction_lv_all_gt_h (decod_instruction_t * inst, decod_param_t * param)
2564	// void instruction_lv_all_le_b (decod_instruction_t * inst, decod_param_t * param)
2565	// void instruction_lv_all_le_h (decod_instruction_t * inst, decod_param_t * param)
2566	// void instruction_lv_all_lt_b (decod_instruction_t * inst, decod_param_t * param)
2567	// void instruction_lv_all_lt_h (decod_instruction_t * inst, decod_param_t * param)
2568	// void instruction_lv_all_ne_b (decod_instruction_t * inst, decod_param_t * param)
2569	// void instruction_lv_all_ne_h (decod_instruction_t * inst, decod_param_t * param)
2570	// void instruction_lv_and (decod_instruction_t * inst, decod_param_t * param)
2571	// void instruction_lv_any_eq_b (decod_instruction_t * inst, decod_param_t * param)
2572	// void instruction_lv_any_eq_h (decod_instruction_t * inst, decod_param_t * param)
2573	// void instruction_lv_any_ge_b (decod_instruction_t * inst, decod_param_t * param)
2574	// void instruction_lv_any_ge_h (decod_instruction_t * inst, decod_param_t * param)
2575	// void instruction_lv_any_gt_b (decod_instruction_t * inst, decod_param_t * param)
2576	// void instruction_lv_any_gt_h (decod_instruction_t * inst, decod_param_t * param)
2577	// void instruction_lv_any_le_b (decod_instruction_t * inst, decod_param_t * param)
2578	// void instruction_lv_any_le_h (decod_instruction_t * inst, decod_param_t * param)
2579	// void instruction_lv_any_lt_b (decod_instruction_t * inst, decod_param_t * param)
2580	// void instruction_lv_any_lt_h (decod_instruction_t * inst, decod_param_t * param)
2581	// void instruction_lv_any_ne_b (decod_instruction_t * inst, decod_param_t * param)
2582	// void instruction_lv_any_ne_h (decod_instruction_t * inst, decod_param_t * param)
2583	// void instruction_lv_avg_b (decod_instruction_t * inst, decod_param_t * param)
2584	// void instruction_lv_avg_h (decod_instruction_t * inst, decod_param_t * param)
2585	// void instruction_lv_cmp_eq_b (decod_instruction_t * inst, decod_param_t * param)
2586	// void instruction_lv_cmp_eq_h (decod_instruction_t * inst, decod_param_t * param)
2587	// void instruction_lv_cmp_ge_b (decod_instruction_t * inst, decod_param_t * param)
2588	// void instruction_lv_cmp_ge_h (decod_instruction_t * inst, decod_param_t * param)
2589	// void instruction_lv_cmp_gt_b (decod_instruction_t * inst, decod_param_t * param)
2590	// void instruction_lv_cmp_gt_h (decod_instruction_t * inst, decod_param_t * param)
2591	// void instruction_lv_cmp_le_b (decod_instruction_t * inst, decod_param_t * param)
2592	// void instruction_lv_cmp_le_h (decod_instruction_t * inst, decod_param_t * param)
2593	// void instruction_lv_cmp_lt_b (decod_instruction_t * inst, decod_param_t * param)
2594	// void instruction_lv_cmp_lt_h (decod_instruction_t * inst, decod_param_t * param)
2595	// void instruction_lv_cmp_ne_b (decod_instruction_t * inst, decod_param_t * param)
2596	// void instruction_lv_cmp_ne_h (decod_instruction_t * inst, decod_param_t * param)
2597	// void instruction_lv_cust1 (decod_instruction_t * inst, decod_param_t * param)
2598	// void instruction_lv_cust2 (decod_instruction_t * inst, decod_param_t * param)
2599	// void instruction_lv_cust3 (decod_instruction_t * inst, decod_param_t * param)
2600	// void instruction_lv_cust4 (decod_instruction_t * inst, decod_param_t * param)
2601	// void instruction_lv_madds_h (decod_instruction_t * inst, decod_param_t * param)
2602	// void instruction_lv_max_b (decod_instruction_t * inst, decod_param_t * param)
2603	// void instruction_lv_max_h (decod_instruction_t * inst, decod_param_t * param)
2604	// void instruction_lv_merge_b (decod_instruction_t * inst, decod_param_t * param)
2605	// void instruction_lv_merge_h (decod_instruction_t * inst, decod_param_t * param)
2606	// void instruction_lv_min_b (decod_instruction_t * inst, decod_param_t * param)
2607	// void instruction_lv_min_h (decod_instruction_t * inst, decod_param_t * param)
2608	// void instruction_lv_msubs_h (decod_instruction_t * inst, decod_param_t * param)
2609	// void instruction_lv_muls_h (decod_instruction_t * inst, decod_param_t * param)
2610	// void instruction_lv_nand (decod_instruction_t * inst, decod_param_t * param)
2611	// void instruction_lv_nor (decod_instruction_t * inst, decod_param_t * param)
2612	// void instruction_lv_or (decod_instruction_t * inst, decod_param_t * param)
2613	// void instruction_lv_pack_b (decod_instruction_t * inst, decod_param_t * param)
2614	// void instruction_lv_pack_h (decod_instruction_t * inst, decod_param_t * param)
2615	// void instruction_lv_packs_b (decod_instruction_t * inst, decod_param_t * param)
2616	// void instruction_lv_packs_h (decod_instruction_t * inst, decod_param_t * param)
2617	// void instruction_lv_packus_b (decod_instruction_t * inst, decod_param_t * param)
2618	// void instruction_lv_packus_h (decod_instruction_t * inst, decod_param_t * param)
2619	// void instruction_lv_perm_n (decod_instruction_t * inst, decod_param_t * param)
2620	// void instruction_lv_rl_b (decod_instruction_t * inst, decod_param_t * param)
2621	// void instruction_lv_rl_h (decod_instruction_t * inst, decod_param_t * param)
2622	// void instruction_lv_sll (decod_instruction_t * inst, decod_param_t * param)
2623	// void instruction_lv_sll_b (decod_instruction_t * inst, decod_param_t * param)
2624	// void instruction_lv_sll_h (decod_instruction_t * inst, decod_param_t * param)
2625	// void instruction_lv_sra_b (decod_instruction_t * inst, decod_param_t * param)
2626	// void instruction_lv_sra_h (decod_instruction_t * inst, decod_param_t * param)
2627	// void instruction_lv_srl (decod_instruction_t * inst, decod_param_t * param)
2628	// void instruction_lv_srl_b (decod_instruction_t * inst, decod_param_t * param)
2629	// void instruction_lv_srl_h (decod_instruction_t * inst, decod_param_t * param)
2630	// void instruction_lv_sub_b (decod_instruction_t * inst, decod_param_t * param)
2631	// void instruction_lv_sub_h (decod_instruction_t * inst, decod_param_t * param)
2632	// void instruction_lv_subs_b (decod_instruction_t * inst, decod_param_t * param)
2633	// void instruction_lv_subs_h (decod_instruction_t * inst, decod_param_t * param)
2634	// void instruction_lv_subu_b (decod_instruction_t * inst, decod_param_t * param)
2635	// void instruction_lv_subu_h (decod_instruction_t * inst, decod_param_t * param)
2636	// void instruction_lv_subus_b (decod_instruction_t * inst, decod_param_t * param)
2637	// void instruction_lv_subus_h (decod_instruction_t * inst, decod_param_t * param)
2638	// void instruction_lv_unpack_b (decod_instruction_t * inst, decod_param_t * param)
2639	// void instruction_lv_unpack_h (decod_instruction_t * inst, decod_param_t * param)
2640	// void instruction_lv_xor (decod_instruction_t * inst, decod_param_t * param)
2641
2642	}; // end namespace decod
2643	}; // end namespace decod_unit
2644	}; // end namespace front_end
2645	}; // end namespace multi_front_end
2646	}; // end namespace core
2647	}; // end namespace behavioural
2648	}; // end namespace morpheo

Note: See TracBrowser for help on using the repository browser.

Download in other formats: