[78] | 1 | /* |
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| 2 | * $Id: test.cpp 101 2009-01-15 17:19:08Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[82] | 9 | #define NB_ITERATION 1 |
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| 10 | #define CYCLE_MAX (2048*NB_ITERATION) |
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| 11 | |
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[78] | 12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h" |
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[87] | 13 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h" |
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[78] | 14 | #include <list> |
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| 15 | #include "Common/include/Test.h" |
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| 16 | #include "Behavioural/include/Allocation.h" |
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| 17 | |
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| 18 | void test (string name, |
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| 19 | morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param) |
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| 20 | { |
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| 21 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 22 | |
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| 23 | #ifdef STATISTICS |
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[88] | 24 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); |
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[78] | 25 | #endif |
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| 26 | |
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[88] | 27 | Tusage_t _usage = USE_ALL; |
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| 28 | |
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| 29 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 30 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 31 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 32 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 33 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 34 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 35 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 36 | |
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[82] | 37 | Decod * _Decod = new Decod |
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| 38 | (name.c_str(), |
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[78] | 39 | #ifdef STATISTICS |
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[82] | 40 | _parameters_statistics, |
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[78] | 41 | #endif |
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[82] | 42 | _param, |
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[88] | 43 | _usage); |
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[78] | 44 | |
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| 45 | #ifdef SYSTEMC |
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| 46 | /********************************************************************* |
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| 47 | * Déclarations des signaux |
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| 48 | *********************************************************************/ |
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| 49 | string rename; |
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| 50 | |
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| 51 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 52 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 53 | |
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[88] | 54 | ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 55 | ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 56 | ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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[78] | 57 | ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); |
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| 58 | ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context); |
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| 59 | // ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context); |
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| 60 | ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); |
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| 61 | ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); |
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| 62 | ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context); |
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[88] | 63 | ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context); |
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| 64 | |
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[78] | 65 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 66 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 67 | ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); |
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| 68 | ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod); |
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| 69 | ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod); |
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| 70 | ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod); |
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[88] | 71 | ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); |
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[78] | 72 | ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 73 | ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 74 | ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 75 | ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 76 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 77 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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| 78 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 79 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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| 80 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 81 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod); |
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| 82 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 83 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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| 84 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 85 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); |
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| 86 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); |
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[88] | 87 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); |
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[78] | 88 | ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 89 | ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 90 | ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); |
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| 91 | ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 92 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod); |
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| 93 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod); |
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| 94 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod); |
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| 95 | // ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 96 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 97 | ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 98 | ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 99 | // ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 100 | ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); |
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[101] | 101 | ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); |
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[78] | 102 | ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); |
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| 103 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); |
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| 104 | ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); |
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| 105 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); |
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[88] | 106 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); |
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[78] | 107 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); |
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| 108 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); |
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| 109 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); |
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| 110 | ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); |
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| 111 | |
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| 112 | /******************************************************** |
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| 113 | * Instanciation |
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| 114 | ********************************************************/ |
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| 115 | |
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| 116 | msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str()); |
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| 117 | |
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| 118 | (*(_Decod->in_CLOCK)) (*(in_CLOCK)); |
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| 119 | (*(_Decod->in_NRESET)) (*(in_NRESET)); |
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| 120 | |
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[88] | 121 | INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 122 | INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 123 | INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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[78] | 124 | if (_param->_have_port_context_id) |
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| 125 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context); |
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| 126 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context); |
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| 127 | // INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); |
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| 128 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context); |
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[88] | 129 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context); |
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| 130 | |
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| 131 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 132 | { |
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| 133 | if (_param->_have_port_inst_ifetch_ptr) |
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| 134 | INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]); |
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| 135 | // if (_param->_have_port_branch_update_prediction_id) |
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| 136 | if (_param->_have_port_depth) |
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| 137 | INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); |
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| 138 | } |
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| 139 | |
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[78] | 140 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod); |
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| 141 | INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod); |
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| 142 | if (_param->_have_port_context_id) |
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| 143 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod); |
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| 144 | if (_param->_have_port_depth) |
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| 145 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod); |
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| 146 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod); |
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| 147 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod); |
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[88] | 148 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); |
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[78] | 149 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); |
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| 150 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod); |
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| 151 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); |
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| 152 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); |
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| 153 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod); |
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| 154 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod); |
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| 155 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod); |
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| 156 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod); |
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| 157 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod); |
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| 158 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod); |
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| 159 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod); |
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| 160 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod); |
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| 161 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod); |
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| 162 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); |
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| 163 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); |
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[88] | 164 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod); |
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[78] | 165 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod); |
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| 166 | INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod); |
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| 167 | if (_param->_have_port_context_id) |
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| 168 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod); |
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| 169 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); |
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| 170 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); |
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[88] | 171 | // if (_param->_have_port_branch_update_prediction_id) |
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| 172 | if (_param->_have_port_depth) |
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[78] | 173 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); |
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| 174 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); |
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| 175 | // INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod); |
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| 176 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod); |
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| 177 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); |
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| 178 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); |
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| 179 | // INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); |
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| 180 | INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); |
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[101] | 181 | INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context); |
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[88] | 182 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 183 | if (_param->_have_port_depth) |
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| 184 | INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]); |
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[78] | 185 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL ); |
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| 186 | INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK ); |
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| 187 | if (_param->_have_port_context_id) |
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| 188 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID ); |
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[88] | 189 | if (_param->_have_port_depth) |
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| 190 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH ); |
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[78] | 191 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE ); |
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| 192 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT ); |
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| 193 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS ); |
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| 194 | INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR ); |
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| 195 | |
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| 196 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 197 | |
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| 198 | Time * _time = new Time(); |
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| 199 | |
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| 200 | /******************************************************** |
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| 201 | * Simulation - Begin |
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| 202 | ********************************************************/ |
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| 203 | |
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| 204 | // Initialisation |
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| 205 | |
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| 206 | const uint32_t seed = 0; |
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| 207 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 208 | |
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| 209 | const int32_t percent_transaction_ifetch = 75; |
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| 210 | const int32_t percent_transaction_decod = 75; |
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| 211 | const int32_t percent_transaction_predict = 75; |
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| 212 | const int32_t percent_transaction_event = 75; |
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| 213 | |
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| 214 | srand(seed); |
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| 215 | |
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| 216 | SC_START(0); |
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| 217 | LABEL("Initialisation"); |
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| 218 | |
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| 219 | LABEL("Reset"); |
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| 220 | in_NRESET->write(0); |
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| 221 | SC_START(5); |
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| 222 | in_NRESET->write(1); |
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| 223 | |
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| 224 | LABEL("Loop of Test"); |
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| 225 | |
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[101] | 226 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 227 | in_CONTEXT_DEPTH_VAL [i]->write(1); |
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| 228 | |
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[78] | 229 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 230 | { |
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| 231 | LABEL("Iteration %d",iteration); |
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| 232 | |
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[87] | 233 | Decod_request request [_param->_nb_context]; |
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[78] | 234 | |
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[87] | 235 | uint32_t nb_request = 0; |
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[78] | 236 | |
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| 237 | uint32_t delay_slot_previous [_param->_nb_context]; |
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| 238 | uint32_t delay_slot_current [_param->_nb_context]; |
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| 239 | uint32_t delay_slot_next [_param->_nb_context]; |
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| 240 | |
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| 241 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 242 | { |
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[87] | 243 | nb_request += request[i].size(); |
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[78] | 244 | delay_slot_current [i] = false; |
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| 245 | delay_slot_next [i] = false; |
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| 246 | } |
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| 247 | |
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| 248 | while (nb_request > 0) |
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| 249 | { |
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| 250 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 251 | { |
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| 252 | delay_slot_previous [i] = false; |
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| 253 | |
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| 254 | in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod); |
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| 255 | |
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| 256 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 257 | in_IFETCH_VAL [i][j]->write(0); |
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| 258 | |
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| 259 | if ((rand()%100)<percent_transaction_ifetch) |
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| 260 | { |
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[87] | 261 | list<entry_t>::iterator it = request[i].begin(); |
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| 262 | |
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[78] | 263 | if (it!=request [i].end()) |
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| 264 | { |
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[86] | 265 | uint32_t lsb = it->_address%_param->_nb_inst_fetch[i]; |
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[78] | 266 | |
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[86] | 267 | in_IFETCH_ADDRESS [i]->write(it->_address-lsb); |
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[78] | 268 | in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE); |
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| 269 | if (_param->_have_port_inst_ifetch_ptr) |
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| 270 | in_IFETCH_INST_IFETCH_PTR [i]->write(0); |
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[88] | 271 | in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE); |
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[78] | 272 | |
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| 273 | // Alignement |
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| 274 | for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++) |
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| 275 | { |
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| 276 | in_IFETCH_VAL [i][j]->write(1); |
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| 277 | in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction); |
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| 278 | // in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next); |
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| 279 | if (it->_type == TYPE_BRANCH) |
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| 280 | in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state); |
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| 281 | in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id); |
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| 282 | |
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| 283 | if ((it->_is_delay_slot) or |
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| 284 | ((++it)==request [i].end())) |
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| 285 | break; |
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| 286 | } |
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| 287 | } |
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| 288 | } |
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| 289 | } |
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| 290 | |
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| 291 | { |
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| 292 | bool previous_ack = true; |
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| 293 | |
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| 294 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 295 | { |
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| 296 | bool ack = previous_ack and ((rand()%100)<percent_transaction_decod); |
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| 297 | in_DECOD_ACK [i]->write(ack); |
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| 298 | |
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| 299 | previous_ack = ack; |
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| 300 | |
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| 301 | in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict); |
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| 302 | // in_PREDICT_CAN_CONTINUE [i]->write(0); |
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| 303 | } |
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| 304 | } |
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| 305 | |
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| 306 | in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event); |
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| 307 | |
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| 308 | SC_START(0); |
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| 309 | |
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| 310 | |
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| 311 | uint32_t nb_inst_ifetch = 0; |
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| 312 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 313 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 314 | if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read()) |
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| 315 | { |
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| 316 | LABEL("IFETCH [%d][%d] : transaction",i,j); |
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| 317 | nb_inst_ifetch ++; |
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| 318 | } |
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| 319 | |
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| 320 | uint32_t nb_inst_decod = 0; |
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| 321 | uint32_t find_event = false; |
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| 322 | |
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| 323 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 324 | if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read()) |
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| 325 | { |
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| 326 | Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0; |
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| 327 | |
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| 328 | LABEL("DECOD [%d] : transaction",i ); |
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| 329 | LABEL(" * context : %d",context); |
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[86] | 330 | LABEL(" * instruction : 0x%x",request [context].front()._instruction); |
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[78] | 331 | |
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| 332 | if (_param->_have_port_depth) |
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| 333 | TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth ); |
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| 334 | TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type ); |
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| 335 | TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation ); |
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| 336 | TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot); |
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| 337 | TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot); |
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| 338 | TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), request [context].front()._address ); |
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| 339 | TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat ); |
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| 340 | if (request [context].front()._has_immediat) |
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| 341 | TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat ); |
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| 342 | TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra ); |
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| 343 | if (request [context].front()._read_ra) |
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| 344 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra ); |
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| 345 | TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb ); |
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| 346 | if (request [context].front()._read_rb) |
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| 347 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb ); |
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| 348 | TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc ); |
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| 349 | if (request [context].front()._read_rc) |
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| 350 | TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc ); |
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| 351 | TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd ); |
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| 352 | if (request [context].front()._write_rd) |
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| 353 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd ); |
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| 354 | TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re ); |
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| 355 | if (request [context].front()._write_re) |
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| 356 | TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re ); |
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| 357 | TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use); |
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| 358 | |
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| 359 | if (request [context].front()._type == TYPE_BRANCH) |
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| 360 | { |
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| 361 | delay_slot_next [context] = true; |
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| 362 | |
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| 363 | TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true); |
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| 364 | TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true); |
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| 365 | |
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| 366 | LABEL("PREDICT [%d] : transaction",i ); |
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| 367 | |
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| 368 | if (_param->_have_port_context_id) |
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| 369 | TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context); |
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[86] | 370 | TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0); |
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[78] | 371 | TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state ); |
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[88] | 372 | // if (_param->_have_port_branch_update_prediction_id) |
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| 373 | if (_param->_have_port_depth) |
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[78] | 374 | TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id); |
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| 375 | TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition ); |
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| 376 | // TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write ); |
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| 377 | TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction ); |
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| 378 | TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address ); |
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| 379 | TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest ); |
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| 380 | } |
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| 381 | else |
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| 382 | { |
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| 383 | TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false); |
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| 384 | } |
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| 385 | |
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| 386 | TEST(bool, find_event, false); // can continue decod after event |
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| 387 | if (request [context].front()._context_event_type != EVENT_TYPE_NONE) |
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| 388 | { |
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| 389 | find_event = true; |
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| 390 | |
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| 391 | LABEL("CONTEXT_EVENT : transaction"); |
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| 392 | |
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| 393 | if (_param->_have_port_context_id) |
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| 394 | TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context); |
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[88] | 395 | if (_param->_have_port_depth ) |
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| 396 | TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth ); |
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[78] | 397 | TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type); |
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| 398 | TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot); |
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| 399 | TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address ); |
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| 400 | TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next ); |
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| 401 | |
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| 402 | } |
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| 403 | |
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| 404 | TEST(bool, delay_slot_previous [context], false); // can't continue |
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| 405 | delay_slot_previous [context] = delay_slot_current [context]; |
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| 406 | delay_slot_current [context] = delay_slot_next [context]; |
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| 407 | delay_slot_next [context] = false; |
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| 408 | |
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| 409 | request [context].pop_front(); |
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| 410 | nb_inst_decod ++; |
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| 411 | nb_request --; |
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| 412 | } |
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| 413 | |
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| 414 | TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event); |
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| 415 | TEST(uint32_t, nb_inst_decod, nb_inst_ifetch); |
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| 416 | |
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| 417 | SC_START(1); |
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| 418 | } |
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| 419 | } |
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| 420 | |
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| 421 | /******************************************************** |
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| 422 | * Simulation - End |
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| 423 | ********************************************************/ |
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| 424 | |
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| 425 | TEST_OK ("End of Simulation"); |
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| 426 | delete _time; |
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| 427 | |
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| 428 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 429 | |
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| 430 | delete in_CLOCK; |
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| 431 | delete in_NRESET; |
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| 432 | |
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| 433 | delete [] in_IFETCH_VAL ; |
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| 434 | delete [] out_IFETCH_ACK ; |
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| 435 | delete [] in_IFETCH_INSTRUCTION ; |
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| 436 | delete [] in_IFETCH_CONTEXT_ID ; |
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| 437 | delete [] in_IFETCH_ADDRESS ; |
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| 438 | // delete [] in_IFETCH_ADDRESS_NEXT ; |
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| 439 | delete [] in_IFETCH_INST_IFETCH_PTR ; |
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| 440 | delete [] in_IFETCH_BRANCH_STATE ; |
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| 441 | delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ; |
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[88] | 442 | delete [] in_IFETCH_EXCEPTION ; |
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[78] | 443 | |
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| 444 | delete [] out_DECOD_VAL ; |
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| 445 | delete [] in_DECOD_ACK ; |
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| 446 | delete [] out_DECOD_CONTEXT_ID ; |
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| 447 | delete [] out_DECOD_DEPTH ; |
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| 448 | delete [] out_DECOD_TYPE ; |
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| 449 | delete [] out_DECOD_OPERATION ; |
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[88] | 450 | delete [] out_DECOD_NO_EXECUTE ; |
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[78] | 451 | delete [] out_DECOD_IS_DELAY_SLOT ; |
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| 452 | delete [] out_DECOD_ADDRESS ; |
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| 453 | delete [] out_DECOD_HAS_IMMEDIAT ; |
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| 454 | delete [] out_DECOD_IMMEDIAT ; |
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| 455 | delete [] out_DECOD_READ_RA ; |
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| 456 | delete [] out_DECOD_NUM_REG_RA ; |
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| 457 | delete [] out_DECOD_READ_RB ; |
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| 458 | delete [] out_DECOD_NUM_REG_RB ; |
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| 459 | delete [] out_DECOD_READ_RC ; |
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| 460 | delete [] out_DECOD_NUM_REG_RC ; |
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| 461 | delete [] out_DECOD_WRITE_RD ; |
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| 462 | delete [] out_DECOD_NUM_REG_RD ; |
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| 463 | delete [] out_DECOD_WRITE_RE ; |
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| 464 | delete [] out_DECOD_NUM_REG_RE ; |
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| 465 | delete [] out_DECOD_EXCEPTION_USE ; |
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[88] | 466 | delete [] out_DECOD_EXCEPTION ; |
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[78] | 467 | |
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| 468 | delete [] out_PREDICT_VAL ; |
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| 469 | delete [] in_PREDICT_ACK ; |
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| 470 | delete [] out_PREDICT_CONTEXT_ID ; |
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| 471 | delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ; |
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| 472 | delete [] out_PREDICT_BRANCH_STATE ; |
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| 473 | delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID; |
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| 474 | delete [] out_PREDICT_BRANCH_CONDITION ; |
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[87] | 475 | //delete [] out_PREDICT_BRANCH_STACK_WRITE ; |
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[78] | 476 | delete [] out_PREDICT_BRANCH_DIRECTION ; |
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| 477 | delete [] out_PREDICT_ADDRESS_SRC ; |
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| 478 | delete [] out_PREDICT_ADDRESS_DEST ; |
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[87] | 479 | //delete [] in_PREDICT_CAN_CONTINUE ; |
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[78] | 480 | |
---|
| 481 | delete [] in_CONTEXT_DECOD_ENABLE ; |
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[101] | 482 | delete [] in_CONTEXT_DEPTH_VAL ; |
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[78] | 483 | delete [] in_CONTEXT_DEPTH ; |
---|
| 484 | |
---|
| 485 | delete out_CONTEXT_EVENT_VAL ; |
---|
| 486 | delete in_CONTEXT_EVENT_ACK ; |
---|
| 487 | delete out_CONTEXT_EVENT_CONTEXT_ID ; |
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[88] | 488 | delete out_CONTEXT_EVENT_DEPTH ; |
---|
[78] | 489 | delete out_CONTEXT_EVENT_TYPE ; |
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| 490 | delete out_CONTEXT_EVENT_IS_DELAY_SLOT ; |
---|
| 491 | delete out_CONTEXT_EVENT_ADDRESS ; |
---|
| 492 | delete out_CONTEXT_EVENT_ADDRESS_EPCR ; |
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| 493 | #endif |
---|
| 494 | |
---|
| 495 | delete _Decod; |
---|
| 496 | #ifdef STATISTICS |
---|
| 497 | delete _parameters_statistics; |
---|
| 498 | #endif |
---|
| 499 | } |
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