[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Decod_genMealy.cpp 108 2009-02-12 11:55:06Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace decod_unit { |
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| 17 | namespace decod { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Decod::genMealy" |
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| 22 | void Decod::genMealy (void) |
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| 23 | { |
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[88] | 24 | log_begin(Decod,FUNCTION); |
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| 25 | log_function(Decod,FUNCTION,_name.c_str()); |
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[78] | 26 | |
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| 27 | //----------------------------------- |
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| 28 | // Initialization |
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| 29 | //----------------------------------- |
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[86] | 30 | Tcontrol_t context_event_val = false; |
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[78] | 31 | Tcontrol_t ifetch_ack [_param->_nb_context][_param->_max_nb_inst_fetch]; |
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| 32 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 33 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 34 | ifetch_ack [i][j] = false; |
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| 35 | |
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| 36 | Tcontrol_t predict_val [_param->_nb_inst_decod]; |
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| 37 | Tcontrol_t decod_val [_param->_nb_inst_decod]; |
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| 38 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 39 | { |
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| 40 | decod_val [i] = false; |
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[88] | 41 | predict_val [i] = false; |
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[78] | 42 | } |
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| 43 | |
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| 44 | Tcontrol_t can_continue [_param->_nb_context]; |
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[108] | 45 | // Tcontrol_t can_continue_next [_param->_nb_context]; |
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| 46 | // Tcontrol_t have_decod_branch [_param->_nb_context]; |
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[78] | 47 | |
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| 48 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 49 | { |
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| 50 | internal_CONTEXT_HAVE_TRANSACTION [i] = false; |
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| 51 | internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i]; |
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| 52 | internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i]; |
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[87] | 53 | |
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[78] | 54 | can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); |
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[108] | 55 | // can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); |
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| 56 | // have_decod_branch [i] = false; |
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[78] | 57 | } |
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| 58 | |
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| 59 | //----------------------------------- |
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| 60 | // Loop of decod |
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| 61 | //----------------------------------- |
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| 62 | // scan all decod "slot_out" |
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[88] | 63 | std::list<generic::priority::select_t> * select = _priority->select(); |
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| 64 | std::list<generic::priority::select_t>::iterator it=select->begin(); |
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[78] | 65 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 66 | { |
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[88] | 67 | while ((it != select->end()) and // have a no scanned "slot_in" ? |
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[78] | 68 | (decod_val [i] == false) and // have not a previous selected entry? |
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| 69 | (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) |
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| 70 | { |
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[107] | 71 | // predict_val [i] = false; |
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[78] | 72 | |
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[88] | 73 | Tcontext_t x = it->grp; |
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| 74 | uint32_t y = it->elt; |
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[78] | 75 | |
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| 76 | // Test if this instruction is valid |
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| 77 | if ((PORT_READ(in_IFETCH_VAL [x][y]) == 1) and // entry is valid |
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| 78 | (can_continue [x] == 1)) // context can decod instruction (have not a previous event) |
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| 79 | { |
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[88] | 80 | log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); |
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[101] | 81 | log_printf(TRACE,Decod,FUNCTION," * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i])); |
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[78] | 82 | |
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[108] | 83 | // can_continue [x] = can_continue_next [x]; |
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[88] | 84 | |
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[78] | 85 | decod_val [i] = true; // fetch_val and decod_enable |
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| 86 | ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack |
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| 87 | |
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[86] | 88 | Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x])+y; |
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[78] | 89 | |
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| 90 | _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); |
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| 91 | _decod_instruction->_context_id = x; |
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| 92 | _decod_instruction->_address_previous = internal_CONTEXT_ADDRESS_PREVIOUS [x]; |
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| 93 | _decod_instruction->_address = addr; //Compute the current address |
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[86] | 94 | _decod_instruction->_address_next = addr+1; |
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[78] | 95 | _decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x]; |
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| 96 | |
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[88] | 97 | // Test IFetch exception |
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| 98 | Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x]); |
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[86] | 99 | |
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[88] | 100 | if (ifetch_exception == EXCEPTION_IFETCH_NONE) |
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| 101 | { |
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| 102 | // Decod ! |
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| 103 | log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i); |
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| 104 | log_printf(TRACE,Decod,FUNCTION," * context : %d",x); |
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| 105 | log_printf(TRACE,Decod,FUNCTION," * fetch : %d",y); |
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| 106 | log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2)); |
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| 107 | log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); |
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| 108 | |
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| 109 | instruction_decod (_decod_instruction, _decod_param[x]); |
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[107] | 110 | |
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| 111 | log_printf(TRACE,Decod,FUNCTION," * address_next : %.8x (%.8x)",_decod_instruction->_address_next,(_decod_instruction->_address_next<<2)); |
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[88] | 112 | } |
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| 113 | else |
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| 114 | { |
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| 115 | // No decod : nop |
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| 116 | instruction_l_nop (_decod_instruction, _decod_param[x]); |
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[78] | 117 | |
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[88] | 118 | _decod_instruction->_exception_use = EXCEPTION_USE_NONE; |
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| 119 | _decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception); |
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| 120 | |
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| 121 | // INSTRUCTION_TLB |
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| 122 | // INSTRUCTION_PAGE |
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| 123 | // BUS_ERROR |
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| 124 | if (_decod_instruction->_is_delay_slot) |
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| 125 | _decod_instruction->_address_next = _decod_instruction->_address_previous; |
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| 126 | else |
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| 127 | _decod_instruction->_address_next = _decod_instruction->_address; |
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| 128 | |
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| 129 | _decod_instruction->_event_type = EVENT_TYPE_EXCEPTION; |
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| 130 | } |
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[78] | 131 | |
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[105] | 132 | Ttype_t type = _decod_instruction->_type; |
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| 133 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT |
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[88] | 134 | |
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[78] | 135 | if (_param->_have_port_context_id) |
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| 136 | PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); |
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| 137 | if (_param->_have_port_depth) |
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[88] | 138 | PORT_WRITE(out_DECOD_DEPTH [i], depth); |
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[78] | 139 | PORT_WRITE(out_DECOD_TYPE [i], type); |
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| 140 | PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); |
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[88] | 141 | PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); |
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[78] | 142 | PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); |
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[108] | 143 | #ifdef DEBUG |
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| 144 | PORT_WRITE(out_DECOD_ADDRESS [i], addr); |
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| 145 | #endif |
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[105] | 146 | // if ((type == TYPE_BRANCH) and |
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| 147 | // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or |
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| 148 | // (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET))) |
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| 149 | // PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address+2); |
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| 150 | // else |
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| 151 | PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next ); |
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[78] | 152 | PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); |
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| 153 | PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat ); |
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| 154 | PORT_WRITE(out_DECOD_READ_RA [i], _decod_instruction->_read_ra ); |
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| 155 | PORT_WRITE(out_DECOD_NUM_REG_RA [i], _decod_instruction->_num_reg_ra ); |
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| 156 | PORT_WRITE(out_DECOD_READ_RB [i], _decod_instruction->_read_rb ); |
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| 157 | PORT_WRITE(out_DECOD_NUM_REG_RB [i], _decod_instruction->_num_reg_rb ); |
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| 158 | PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); |
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| 159 | PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); |
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[101] | 160 | PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); |
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[78] | 161 | PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); |
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| 162 | PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); |
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| 163 | PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re ); |
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| 164 | PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use ); |
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[88] | 165 | // PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception ); |
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[78] | 166 | |
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[101] | 167 | // Branch predictor can accept : the depth is valid |
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| 168 | log_printf(TRACE,Decod,FUNCTION," * context_depth_val : %d",PORT_READ(in_CONTEXT_DEPTH_VAL [x])); |
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| 169 | decod_val [i] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); |
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| 170 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); |
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| 171 | |
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[78] | 172 | if (type == TYPE_BRANCH) |
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| 173 | { |
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[88] | 174 | log_printf(TRACE,Decod,FUNCTION," * type is branch"); |
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[107] | 175 | log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]); |
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[101] | 176 | log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); |
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| 177 | |
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[88] | 178 | log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); |
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| 179 | log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); |
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[107] | 180 | |
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[78] | 181 | predict_val [i] = ifetch_ack [x][y] // and decod_val [i] |
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| 182 | ; |
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[101] | 183 | decod_val [i] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable |
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| 184 | ifetch_ack [x][y] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack |
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| 185 | |
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[78] | 186 | if (_param->_have_port_context_id) |
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| 187 | PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); |
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| 188 | PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); |
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| 189 | PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x])); |
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[88] | 190 | if (_param->_have_port_depth) |
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| 191 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x])); |
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[78] | 192 | PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition ); |
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| 193 | // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); |
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| 194 | PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); |
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| 195 | PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address ); |
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| 196 | PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next ); |
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| 197 | |
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| 198 | //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order) |
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[108] | 199 | can_continue [x] = false; // one branch per context, the DS don't execute |
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| 200 | // can_continue_next [x] = false; // one branch per context, the DS don't execute |
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| 201 | // have_decod_branch [x] = true; |
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[78] | 202 | } |
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| 203 | |
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| 204 | Tevent_type_t event_type = _decod_instruction->_event_type; |
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| 205 | if (event_type != EVENT_TYPE_NONE) |
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| 206 | { |
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| 207 | // speculative jump at the exception handler |
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| 208 | // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE |
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| 209 | context_event_val = ifetch_ack [x][y] // and decod_val [i] |
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| 210 | ; |
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| 211 | decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable |
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| 212 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack |
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| 213 | |
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| 214 | if (_param->_have_port_context_id) |
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| 215 | PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , x); |
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[88] | 216 | if (_param->_have_port_depth) |
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| 217 | PORT_WRITE(out_CONTEXT_EVENT_DEPTH , depth); |
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[78] | 218 | PORT_WRITE(out_CONTEXT_EVENT_TYPE , _decod_instruction->_event_type ); |
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| 219 | PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, _decod_instruction->_is_delay_slot ); |
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| 220 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , _decod_instruction->_address ); |
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| 221 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , _decod_instruction->_address_next ); |
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| 222 | } |
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| 223 | |
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| 224 | // fetch_ack = |
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| 225 | // ((event_type == EVENT_TYPE_NONE) or ((event_type != EVENT_TYPE_NONE) and context_event_ack)) and |
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| 226 | // ((type == TYPE_BRANCH ) or ((type != TYPE_BRANCH ) and predict_ack )) and |
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| 227 | // fetch_val and decod_ack and decod_enable and true (is decod_val) |
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| 228 | |
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| 229 | // To compute the "next previous" address |
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| 230 | Tcontrol_t have_transaction = ifetch_ack [x][y]; |
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| 231 | |
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| 232 | internal_CONTEXT_HAVE_TRANSACTION [x] |= have_transaction; |
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| 233 | if (have_transaction) |
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| 234 | { |
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| 235 | internal_CONTEXT_ADDRESS_PREVIOUS [x] = addr; |
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| 236 | internal_CONTEXT_IS_DELAY_SLOT [x] = (type == TYPE_BRANCH); // next is a delay slot if current have branch type |
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| 237 | } |
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| 238 | |
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| 239 | can_continue [x] &= have_transaction; // to have a in order decod !!! if a previous instruction can decod, also next instruction can't decod. |
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| 240 | } |
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[87] | 241 | |
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[88] | 242 | log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y); |
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| 243 | log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]); |
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| 244 | log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val ); |
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| 245 | log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] ); |
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| 246 | log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] ); |
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[78] | 247 | |
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| 248 | it ++; |
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| 249 | } |
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| 250 | } |
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| 251 | //----------------------------------- |
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| 252 | // Write output |
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| 253 | //----------------------------------- |
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| 254 | |
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| 255 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 256 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 257 | PORT_WRITE(out_IFETCH_ACK [i][j], ifetch_ack [i][j]); |
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| 258 | |
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| 259 | PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val); |
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| 260 | |
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| 261 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 262 | { |
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| 263 | PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]); |
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| 264 | PORT_WRITE(out_DECOD_VAL [i], decod_val [i]); |
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[88] | 265 | |
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| 266 | #ifdef STATISTICS |
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| 267 | internal_DECOD_VAL [i] = decod_val [i]; |
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| 268 | #endif |
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[78] | 269 | } |
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| 270 | |
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[88] | 271 | log_end(Decod,FUNCTION); |
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[78] | 272 | }; |
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| 273 | |
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| 274 | }; // end namespace decod |
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| 275 | }; // end namespace decod_unit |
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| 276 | }; // end namespace front_end |
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| 277 | }; // end namespace multi_front_end |
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| 278 | }; // end namespace core |
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| 279 | |
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| 280 | }; // end namespace behavioural |
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| 281 | }; // end namespace morpheo |
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| 282 | #endif |
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