1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Decod_genMealy.cpp 124 2009-06-17 12:11:25Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace decod_unit { |
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17 | namespace decod { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Decod::genMealy" |
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22 | void Decod::genMealy (void) |
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23 | { |
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24 | log_begin(Decod,FUNCTION); |
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25 | log_function(Decod,FUNCTION,_name.c_str()); |
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26 | |
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27 | if (PORT_READ(in_NRESET)) |
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28 | { |
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29 | //----------------------------------- |
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30 | // Initialization |
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31 | //----------------------------------- |
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32 | Tcontrol_t context_event_val = false; |
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33 | Tcontrol_t ifetch_ack [_param->_nb_context][_param->_max_nb_inst_fetch]; |
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34 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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35 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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36 | ifetch_ack [i][j] = false; |
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37 | |
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38 | Tcontrol_t predict_val [_param->_nb_inst_decod]; |
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39 | Tcontrol_t decod_val [_param->_nb_inst_decod]; |
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40 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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41 | { |
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42 | decod_val [i] = false; |
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43 | predict_val [i] = false; |
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44 | } |
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45 | |
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46 | Tcontrol_t can_continue [_param->_nb_context]; |
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47 | Tcontrol_t have_decod_branch [_param->_nb_context]; |
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48 | |
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49 | Tcontext_t CONTEXT_EVENT_CONTEXT_ID = 0; |
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50 | Tdepth_t CONTEXT_EVENT_DEPTH = 0; |
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51 | Tevent_type_t CONTEXT_EVENT_TYPE = 0; |
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52 | Tcontrol_t CONTEXT_EVENT_IS_DELAY_SLOT = 0; |
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53 | Tgeneral_data_t CONTEXT_EVENT_ADDRESS = 0; |
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54 | Tgeneral_data_t CONTEXT_EVENT_ADDRESS_EPCR = 0; |
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55 | |
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56 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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57 | { |
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58 | internal_CONTEXT_HAVE_TRANSACTION [i] = false; |
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59 | internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i]; |
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60 | internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i]; |
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61 | |
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62 | can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); |
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63 | have_decod_branch [i] = false; |
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64 | } |
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65 | |
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66 | //----------------------------------- |
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67 | // Loop of decod |
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68 | //----------------------------------- |
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69 | // scan all decod "slot_out" |
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70 | std::list<generic::priority::select_t> * select = _priority->select(); |
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71 | std::list<generic::priority::select_t>::iterator it=select->begin(); |
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72 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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73 | { |
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74 | log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i); |
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75 | |
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76 | bool ifetch_val = false; |
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77 | while ((it != select->end()) and // have a no scanned "slot_in" ? |
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78 | // (decod_val [i] == false) and // have not a previous selected entry? |
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79 | (ifetch_val == false) and // not find ifetch instruction valid |
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80 | (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) |
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81 | { |
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82 | // predict_val [i] = false; |
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83 | |
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84 | Tcontext_t x = it->grp; |
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85 | uint32_t y = it->elt; |
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86 | |
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87 | log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); |
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88 | log_printf(TRACE,Decod,FUNCTION," * in_IFETCH_VAL : %d",PORT_READ(in_IFETCH_VAL [x][y])); |
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89 | log_printf(TRACE,Decod,FUNCTION," * can_continue : %d",can_continue [x] ); |
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90 | |
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91 | // Test if this instruction is valid |
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92 | if ((PORT_READ(in_IFETCH_VAL [x][y]) == 1) and // entry is valid |
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93 | (can_continue [x] == 1)) // context can decod instruction (have not a previous event) |
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94 | { |
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95 | log_printf(TRACE,Decod,FUNCTION," * decod_ack : %d",PORT_READ(in_DECOD_ACK [i])); |
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96 | |
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97 | ifetch_val = true; |
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98 | decod_val [i] = true; // fetch_val and decod_enable |
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99 | ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack |
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100 | |
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101 | Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x])+y; |
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102 | |
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103 | _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); |
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104 | _decod_instruction->_context_id = x; |
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105 | _decod_instruction->_address_previous = internal_CONTEXT_ADDRESS_PREVIOUS [x]; |
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106 | _decod_instruction->_address = addr; //Compute the current address |
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107 | _decod_instruction->_address_next = addr+1; |
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108 | _decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x]; |
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109 | |
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110 | // Test IFetch exception |
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111 | Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x]); |
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112 | |
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113 | if (ifetch_exception == EXCEPTION_IFETCH_NONE) |
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114 | { |
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115 | // Decod ! |
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116 | log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2)); |
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117 | log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); |
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118 | |
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119 | instruction_decod (_decod_instruction, _decod_param[x]); |
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120 | |
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121 | log_printf(TRACE,Decod,FUNCTION," * address_next : %.8x (%.8x)",_decod_instruction->_address_next,(_decod_instruction->_address_next<<2)); |
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122 | } |
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123 | else |
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124 | { |
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125 | // No decod : nop |
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126 | instruction_l_nop (_decod_instruction, _decod_param[x]); |
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127 | |
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128 | _decod_instruction->_exception_use = EXCEPTION_USE_NONE; |
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129 | _decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception); |
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130 | |
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131 | // INSTRUCTION_TLB |
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132 | // INSTRUCTION_PAGE |
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133 | // BUS_ERROR |
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134 | if (_decod_instruction->_is_delay_slot) |
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135 | _decod_instruction->_address_next = _decod_instruction->_address_previous; |
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136 | else |
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137 | _decod_instruction->_address_next = _decod_instruction->_address; |
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138 | |
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139 | _decod_instruction->_event_type = EVENT_TYPE_EXCEPTION; |
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140 | } |
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141 | |
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142 | Ttype_t type = _decod_instruction->_type; |
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143 | // Depth current. If have decod a branch and i can continue : depth = depth_next |
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144 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; |
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145 | |
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146 | if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x]) |
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147 | depth = (depth+1)%_param->_nb_branch_speculated[x]; |
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148 | |
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149 | if (_param->_have_port_context_id) |
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150 | PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); |
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151 | if (_param->_have_port_depth) |
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152 | PORT_WRITE(out_DECOD_DEPTH [i], depth); |
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153 | PORT_WRITE(out_DECOD_TYPE [i], type); |
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154 | PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); |
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155 | PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); |
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156 | PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); |
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157 | #ifdef DEBUG |
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158 | PORT_WRITE(out_DECOD_ADDRESS [i], addr); |
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159 | #endif |
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160 | // if ((type == TYPE_BRANCH) and |
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161 | // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or |
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162 | // (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET))) |
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163 | // PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address+2); |
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164 | // else |
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165 | PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next ); |
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166 | PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); |
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167 | PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat ); |
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168 | PORT_WRITE(out_DECOD_READ_RA [i], _decod_instruction->_read_ra ); |
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169 | PORT_WRITE(out_DECOD_NUM_REG_RA [i], _decod_instruction->_num_reg_ra ); |
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170 | PORT_WRITE(out_DECOD_READ_RB [i], _decod_instruction->_read_rb ); |
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171 | PORT_WRITE(out_DECOD_NUM_REG_RB [i], _decod_instruction->_num_reg_rb ); |
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172 | PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); |
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173 | PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); |
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174 | PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); |
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175 | PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); |
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176 | PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); |
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177 | PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re ); |
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178 | PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use ); |
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179 | // PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception ); |
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180 | |
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181 | // Branch predictor can accept : the depth is valid |
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182 | log_printf(TRACE,Decod,FUNCTION," * context_depth_val : %d",PORT_READ(in_CONTEXT_DEPTH_VAL [x])); |
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183 | decod_val [i] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); |
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184 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); |
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185 | |
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186 | if (type == TYPE_BRANCH) |
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187 | { |
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188 | log_printf(TRACE,Decod,FUNCTION," * Instruction is branch"); |
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189 | log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]); |
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190 | log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); |
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191 | |
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192 | log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); |
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193 | log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); |
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194 | |
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195 | // test if have already decod an branch : one branch per context |
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196 | predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y] // and decod_val [i] |
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197 | ; |
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198 | decod_val [i] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable |
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199 | ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack |
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200 | |
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201 | // can continue is set if direction is "not take" (also, continue is sequential order) |
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202 | |
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203 | // can_continue [x] = false; // one branch per context, the DS don't execute |
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204 | can_continue [x]&= PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // one branch per context, the DS don't execute |
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205 | have_decod_branch [x] = true; |
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206 | |
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207 | log_printf(TRACE,Decod,FUNCTION," * predict_can_continue : %d",PORT_READ(in_PREDICT_CAN_CONTINUE [i])); |
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208 | } |
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209 | |
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210 | if (_param->_have_port_context_id) |
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211 | PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); |
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212 | PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); |
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213 | PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x])); |
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214 | if (_param->_have_port_depth) |
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215 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x])); |
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216 | PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition ); |
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217 | // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); |
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218 | PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); |
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219 | PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address ); |
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220 | PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next ); |
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221 | |
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222 | Tevent_type_t event_type = _decod_instruction->_event_type; |
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223 | if (event_type != EVENT_TYPE_NONE) |
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224 | { |
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225 | log_printf(TRACE,Decod,FUNCTION," * Instruction make an EVENT (%s)",toString(event_type).c_str()); |
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226 | log_printf(TRACE,Decod,FUNCTION," * context_event_ack : %d",PORT_READ(in_CONTEXT_EVENT_ACK)); |
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227 | |
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228 | // speculative jump at the exception handler |
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229 | // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE |
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230 | context_event_val = ifetch_ack [x][y] // and decod_val [i] |
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231 | ; |
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232 | decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable |
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233 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack |
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234 | |
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235 | CONTEXT_EVENT_CONTEXT_ID = x; |
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236 | CONTEXT_EVENT_DEPTH = depth; |
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237 | CONTEXT_EVENT_TYPE = _decod_instruction->_event_type; |
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238 | CONTEXT_EVENT_IS_DELAY_SLOT = _decod_instruction->_is_delay_slot; |
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239 | CONTEXT_EVENT_ADDRESS = _decod_instruction->_address; |
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240 | CONTEXT_EVENT_ADDRESS_EPCR = _decod_instruction->_address_next ; |
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241 | |
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242 | } |
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243 | |
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244 | // fetch_ack = |
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245 | // ((event_type == EVENT_TYPE_NONE) or ((event_type != EVENT_TYPE_NONE) and context_event_ack)) and |
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246 | // ((type == TYPE_BRANCH ) or ((type != TYPE_BRANCH ) and predict_ack )) and |
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247 | // fetch_val and decod_ack and decod_enable and true (is decod_val) |
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248 | |
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249 | // To compute the "next previous" address |
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250 | Tcontrol_t have_transaction = ifetch_ack [x][y]; |
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251 | |
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252 | internal_CONTEXT_HAVE_TRANSACTION [x] |= have_transaction; |
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253 | if (have_transaction) |
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254 | { |
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255 | internal_CONTEXT_ADDRESS_PREVIOUS [x] = addr; |
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256 | internal_CONTEXT_IS_DELAY_SLOT [x] = (type == TYPE_BRANCH); // next is a delay slot if current have branch type |
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257 | } |
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258 | |
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259 | can_continue [x] &= have_transaction; // to have a in order decod !!! if a previous instruction can decod, also next instruction can't decod. |
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260 | |
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261 | log_printf(TRACE,Decod,FUNCTION," * have_transaction : %d",have_transaction); |
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262 | |
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263 | } |
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264 | |
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265 | log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y); |
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266 | log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]); |
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267 | log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val ); |
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268 | log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] ); |
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269 | log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] ); |
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270 | |
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271 | it ++; |
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272 | } |
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273 | } |
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274 | |
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275 | //----------------------------------- |
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276 | // Write output |
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277 | //----------------------------------- |
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278 | |
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279 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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280 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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281 | PORT_WRITE(out_IFETCH_ACK [i][j], ifetch_ack [i][j]); |
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282 | |
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283 | PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val); |
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284 | if (_param->_have_port_context_id) |
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285 | PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , CONTEXT_EVENT_CONTEXT_ID ); |
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286 | if (_param->_have_port_depth) |
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287 | PORT_WRITE(out_CONTEXT_EVENT_DEPTH , CONTEXT_EVENT_DEPTH ); |
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288 | PORT_WRITE(out_CONTEXT_EVENT_TYPE , CONTEXT_EVENT_TYPE ); |
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289 | PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, CONTEXT_EVENT_IS_DELAY_SLOT); |
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290 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , CONTEXT_EVENT_ADDRESS ); |
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291 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , CONTEXT_EVENT_ADDRESS_EPCR ); |
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292 | |
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293 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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294 | { |
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295 | PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]); |
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296 | PORT_WRITE(out_DECOD_VAL [i], decod_val [i]); |
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297 | |
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298 | #ifdef STATISTICS |
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299 | internal_DECOD_VAL [i] = decod_val [i]; |
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300 | #endif |
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301 | } |
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302 | } |
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303 | else |
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304 | { |
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305 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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306 | { |
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307 | internal_CONTEXT_HAVE_TRANSACTION [i] = false; |
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308 | // internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i]; |
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309 | // internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i]; |
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310 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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311 | PORT_WRITE(out_IFETCH_ACK [i][j], 0); |
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312 | } |
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313 | |
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314 | PORT_WRITE(out_CONTEXT_EVENT_VAL, 0); |
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315 | |
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316 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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317 | { |
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318 | PORT_WRITE(out_PREDICT_VAL [i], 0); |
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319 | PORT_WRITE(out_DECOD_VAL [i], 0); |
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320 | |
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321 | #ifdef STATISTICS |
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322 | internal_DECOD_VAL [i] = 0; |
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323 | #endif |
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324 | } |
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325 | } |
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326 | |
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327 | log_end(Decod,FUNCTION); |
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328 | }; |
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329 | |
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330 | }; // end namespace decod |
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331 | }; // end namespace decod_unit |
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332 | }; // end namespace front_end |
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333 | }; // end namespace multi_front_end |
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334 | }; // end namespace core |
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335 | |
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336 | }; // end namespace behavioural |
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337 | }; // end namespace morpheo |
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338 | #endif |
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