Changeset 124 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
- Timestamp:
- Jun 17, 2009, 2:11:25 PM (15 years ago)
- File:
-
- 1 edited
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- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r123 r124 47 47 Tcontrol_t have_decod_branch [_param->_nb_context]; 48 48 49 Tcontext_t CONTEXT_EVENT_CONTEXT_ID = 0; 50 Tdepth_t CONTEXT_EVENT_DEPTH = 0; 51 Tevent_type_t CONTEXT_EVENT_TYPE = 0; 52 Tcontrol_t CONTEXT_EVENT_IS_DELAY_SLOT = 0; 53 Tgeneral_data_t CONTEXT_EVENT_ADDRESS = 0; 54 Tgeneral_data_t CONTEXT_EVENT_ADDRESS_EPCR = 0; 55 49 56 for (uint32_t i=0; i<_param->_nb_context; i++) 50 57 { … … 67 74 log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i); 68 75 76 bool ifetch_val = false; 69 77 while ((it != select->end()) and // have a no scanned "slot_in" ? 70 (decod_val [i] == false) and // have not a previous selected entry? 78 // (decod_val [i] == false) and // have not a previous selected entry? 79 (ifetch_val == false) and // not find ifetch instruction valid 71 80 (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) 72 81 { … … 86 95 log_printf(TRACE,Decod,FUNCTION," * decod_ack : %d",PORT_READ(in_DECOD_ACK [i])); 87 96 97 ifetch_val = true; 88 98 decod_val [i] = true; // fetch_val and decod_enable 89 99 ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack … … 189 199 ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack 190 200 191 if (_param->_have_port_context_id)192 PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x);193 PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0));194 PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x]));195 if (_param->_have_port_depth)196 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x]));197 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition );198 // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write);199 PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction );200 PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address );201 PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next );202 203 201 // can continue is set if direction is "not take" (also, continue is sequential order) 204 202 … … 209 207 log_printf(TRACE,Decod,FUNCTION," * predict_can_continue : %d",PORT_READ(in_PREDICT_CAN_CONTINUE [i])); 210 208 } 209 210 if (_param->_have_port_context_id) 211 PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); 212 PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); 213 PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x])); 214 if (_param->_have_port_depth) 215 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x])); 216 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition ); 217 // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); 218 PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); 219 PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address ); 220 PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next ); 211 221 212 222 Tevent_type_t event_type = _decod_instruction->_event_type; … … 223 233 ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack 224 234 225 if (_param->_have_port_context_id) 226 PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , x); 227 if (_param->_have_port_depth) 228 PORT_WRITE(out_CONTEXT_EVENT_DEPTH , depth); 229 PORT_WRITE(out_CONTEXT_EVENT_TYPE , _decod_instruction->_event_type ); 230 PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, _decod_instruction->_is_delay_slot ); 231 PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , _decod_instruction->_address ); 232 PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , _decod_instruction->_address_next ); 235 CONTEXT_EVENT_CONTEXT_ID = x; 236 CONTEXT_EVENT_DEPTH = depth; 237 CONTEXT_EVENT_TYPE = _decod_instruction->_event_type; 238 CONTEXT_EVENT_IS_DELAY_SLOT = _decod_instruction->_is_delay_slot; 239 CONTEXT_EVENT_ADDRESS = _decod_instruction->_address; 240 CONTEXT_EVENT_ADDRESS_EPCR = _decod_instruction->_address_next ; 241 233 242 } 234 243 … … 263 272 } 264 273 } 274 265 275 //----------------------------------- 266 276 // Write output … … 272 282 273 283 PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val); 284 if (_param->_have_port_context_id) 285 PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , CONTEXT_EVENT_CONTEXT_ID ); 286 if (_param->_have_port_depth) 287 PORT_WRITE(out_CONTEXT_EVENT_DEPTH , CONTEXT_EVENT_DEPTH ); 288 PORT_WRITE(out_CONTEXT_EVENT_TYPE , CONTEXT_EVENT_TYPE ); 289 PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, CONTEXT_EVENT_IS_DELAY_SLOT); 290 PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , CONTEXT_EVENT_ADDRESS ); 291 PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , CONTEXT_EVENT_ADDRESS_EPCR ); 274 292 275 293 for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
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