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Decod_genMealy.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago
1) add test with SPECINT2K 2) new config of Selftest 3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table) 4) add Function_pointer but need fix
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1	#ifdef SYSTEMC
2	/*
3	* $Id: Decod_genMealy.cpp 145 2010-10-13 18:15:51Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace decod_unit {
17	namespace decod {
18
19
20	#undef FUNCTION
21	#define FUNCTION "Decod::genMealy"
22	void Decod::genMealy (void)
23	{
24	log_begin(Decod,FUNCTION);
25	log_function(Decod,FUNCTION,_name.c_str());
26
27	if (PORT_READ(in_NRESET))
28	{
29	//-----------------------------------
30	// Initialization
31	//-----------------------------------
32	Tcontrol_t context_event_val = false;
33	Tcontrol_t ifetch_ack [_param->_nb_context][_param->_max_nb_inst_fetch];
34	for (uint32_t i=0; i<_param->_nb_context; i++)
35	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
36	ifetch_ack [i][j] = false;
37
38	Tcontrol_t predict_val [_param->_nb_inst_decod];
39	Tcontrol_t decod_val [_param->_nb_inst_decod];
40	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
41	{
42	decod_val [i] = false;
43	predict_val [i] = false;
44	}
45
46	Tcontrol_t can_continue [_param->_nb_context];
47	Tcontrol_t have_decod_branch [_param->_nb_context];
48
49	Tcontext_t CONTEXT_EVENT_CONTEXT_ID = 0;
50	Tdepth_t CONTEXT_EVENT_DEPTH = 0;
51	Tevent_type_t CONTEXT_EVENT_TYPE = 0;
52	Tcontrol_t CONTEXT_EVENT_IS_DELAY_SLOT = 0;
53	Tgeneral_data_t CONTEXT_EVENT_ADDRESS = 0;
54	Tgeneral_data_t CONTEXT_EVENT_ADDRESS_EPCR = 0;
55
56	for (uint32_t i=0; i<_param->_nb_context; i++)
57	{
58	internal_CONTEXT_HAVE_TRANSACTION [i] = false;
59	internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i];
60	internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i];
61	// internal_CONTEXT_SAVE_RAT [i] = reg_CONTEXT_SAVE_RAT [i];
62
63	can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]);
64	have_decod_branch [i] = false;
65	}
66
67	//-----------------------------------
68	// Loop of decod
69	//-----------------------------------
70	// scan all decod "slot_out"
71	std::list<generic::priority::select_t> * select = _priority->select();
72	std::list<generic::priority::select_t>::iterator it=select->begin();
73
74	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
75	{
76	log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i);
77
78	bool ifetch_val = false;
79
80	while ((it != select->end()) and // have a no scanned instruction from ifetch_unit ?
81	// (decod_val [i] == false) and // have not a previous selected entry?
82	(ifetch_val == false) and // not find ifetch instruction valid
83	(context_event_val == false)) // Have not a context_event (spr_access, exception, ...) (ONCE CONTEXT PER CYCLE (context state moore easy))
84	{
85	// predict_val [i] = false;
86
87	Tcontext_t x = it->grp; // num_front_end
88	uint32_t y = it->elt; // num_instruction
89
90	log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y);
91	log_printf(TRACE,Decod,FUNCTION," * in_IFETCH_VAL : %d",PORT_READ(in_IFETCH_VAL [x][y]));
92	log_printf(TRACE,Decod,FUNCTION," * can_continue : %d",can_continue [x] );
93
94	// Test if this instruction is valid
95	if ((PORT_READ(in_IFETCH_VAL [x][y]) == 1) and // entry is valid
96	(can_continue [x] == 1)) // context can decod instruction (have not a previous event)
97	{
98	log_printf(TRACE,Decod,FUNCTION," * decod_ack : %d",PORT_READ(in_DECOD_ACK [i]));
99
100	ifetch_val = true;
101	decod_val [i] = true; // fetch_val and decod_enable
102	ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack
103
104	Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]);
105
106	// Read instruction and set default value
107	_decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]);
108	_decod_instruction->_context_id = x;
109	_decod_instruction->_address_previous = internal_CONTEXT_ADDRESS_PREVIOUS [x];
110	_decod_instruction->_address = addr; //Compute the current address
111	_decod_instruction->_address_next = addr+1;
112	_decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x];
113	#ifdef STATISTICS
114	_decod_instruction->_opcod = -1; // not necessary
115	#endif
116	_decod_instruction->_type = 0; // not necessary
117	_decod_instruction->_operation = 0; // not necessary
118	_decod_instruction->_no_execute = 0; // not necessary
119	_decod_instruction->_has_immediat = 0; // not necessary
120	_decod_instruction->_immediat = 0; // not necessary
121	_decod_instruction->_read_ra = 0; // not necessary
122	_decod_instruction->_num_reg_ra = 0; // not necessary
123	_decod_instruction->_read_rb = 0; // not necessary
124	_decod_instruction->_num_reg_rb = 0; // not necessary
125	_decod_instruction->_read_rc = 0; // not necessary
126	_decod_instruction->_num_reg_rc = 0; // not necessary
127	_decod_instruction->_write_rd = 0; // not necessary
128	_decod_instruction->_num_reg_rd = 0; // not necessary
129	_decod_instruction->_write_re = 0; // not necessary
130	_decod_instruction->_num_reg_re = 0; // not necessary
131	_decod_instruction->_exception_use = EXCEPTION_USE_NONE; // not necessary
132	_decod_instruction->_exception = EXCEPTION_DECOD_NONE; // not necessary
133	_decod_instruction->_branch_condition = 0; // not necessary
134	// _decod_instruction->_branch_stack_write = 0; // not necessary
135	_decod_instruction->_branch_direction = 0; // not necessary
136	_decod_instruction->_event_type = EVENT_TYPE_NONE; // not necessary
137
138	// Test if ifetch_unit have an exception (per example : IBERR)
139	Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]);
140
141	if (ifetch_exception == EXCEPTION_IFETCH_NONE)
142	{
143	// No exception, can Decod !
144	log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2));
145	log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]);
146
147	instruction_decod (_decod_instruction, _decod_param[x]);
148
149	log_printf(TRACE,Decod,FUNCTION," * address_next : %.8x (%.8x)",_decod_instruction->_address_next,(_decod_instruction->_address_next<<2));
150	}
151	else
152	{
153	// Exception : transform this instruction in a nop
154	// * INSTRUCTION_TLB
155	// * INSTRUCTION_PAGE
156	// * BUS_ERROR
157
158	log_printf(TRACE,Decod,FUNCTION," * exception -> change instruction in a l.nop");
159
160	instruction_l_nop (_decod_instruction, _decod_param[x]);
161
162	_decod_instruction->_exception_use = EXCEPTION_USE_NONE;
163	_decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception);
164
165	if (_decod_instruction->_is_delay_slot)
166	_decod_instruction->_address_next = _decod_instruction->_address_previous;
167	else
168	_decod_instruction->_address_next = _decod_instruction->_address;
169
170	_decod_instruction->_event_type = EVENT_TYPE_EXCEPTION;
171	}
172
173	Ttype_t type = _decod_instruction->_type;
174	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0;
175	Tbranch_condition_t branch_condition = _decod_instruction->_branch_condition;
176
177	// Save RAT if instruction is a branch and is conditionnal (not l.j and not l.jal)
178
179	//Tcontrol_t save_rat = internal_CONTEXT_SAVE_RAT [x];
180	// Tcontrol_t save_rat = ((type == TYPE_BRANCH) and
181	// not ((branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK) or
182	// (branch_condition==BRANCH_CONDITION_NONE_WITH_WRITE_STACK)));
183
184	Tcontrol_t save_rat = ((type == TYPE_BRANCH) and
185	not (branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK));
186
187	// FIXME : depth+1 valid ???????
188	if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x])
189	depth = (depth+1)%_param->_nb_branch_speculated[x];
190
191	// Write output
192	if (_param->_have_port_context_id)
193	PORT_WRITE(out_DECOD_CONTEXT_ID [i], x);
194	if (_param->_have_port_depth)
195	PORT_WRITE(out_DECOD_DEPTH [i], depth);
196	#ifdef STATISTICS
197	PORT_WRITE(out_DECOD_INSTRUCTION [i], _decod_instruction->_opcod );
198	#endif
199	PORT_WRITE(out_DECOD_TYPE [i], type);
200	PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation );
201	PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute );
202	PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot );
203	PORT_WRITE(out_DECOD_SAVE_RAT [i], save_rat);
204	#ifdef DEBUG
205	PORT_WRITE(out_DECOD_ADDRESS [i], addr);
206	#endif
207	PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next );
208	PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat );
209	PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat );
210	PORT_WRITE(out_DECOD_READ_RA [i], _decod_instruction->_read_ra );
211	PORT_WRITE(out_DECOD_NUM_REG_RA [i], _decod_instruction->_num_reg_ra );
212	PORT_WRITE(out_DECOD_READ_RB [i], _decod_instruction->_read_rb );
213	PORT_WRITE(out_DECOD_NUM_REG_RB [i], _decod_instruction->_num_reg_rb );
214	PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc );
215	PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc );
216	PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); // don't write in RD if RD=0
217	PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd );
218	PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re );
219	PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re );
220	PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use );
221	PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception );
222
223	// Branch predictor can accept : the depth is valid
224	log_printf(TRACE,Decod,FUNCTION," * context_depth_val : %d",PORT_READ(in_CONTEXT_DEPTH_VAL [x]));
225
226	decod_val [i] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]);
227	ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]);
228
229	if (type == TYPE_BRANCH)
230	{
231	log_printf(TRACE,Decod,FUNCTION," * Instruction is branch");
232	log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]);
233	log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i]));
234	log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2);
235	log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2);
236
237	// test if have already decod an branch : ONCE BRANCH PER CONTEXT
238	predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y]; // and decod_val [i]
239	decod_val [i] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable
240	ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack
241
242	// can continue is set if direction is "not take" (also, continue is sequential order)
243
244	// can_continue [x] = false; // one branch per context, the DS don't execute
245	can_continue [x]&= PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // one branch per context, the DS don't execute
246	have_decod_branch [x] = true;
247
248	log_printf(TRACE,Decod,FUNCTION," * predict_can_continue : %d",PORT_READ(in_PREDICT_CAN_CONTINUE [i]));
249	}
250
251	Tbranch_state_t ifetch_branch_state = PORT_READ(in_IFETCH_BRANCH_STATE [x][y]);
252	if (_param->_have_port_context_id)
253	PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x);
254	// PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0));
255	PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],ifetch_branch_state != BRANCH_STATE_NONE);
256
257	PORT_WRITE(out_PREDICT_BRANCH_STATE [i],ifetch_branch_state);
258	if (_param->_have_port_depth)
259	PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y]));
260	PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],branch_condition);
261	// PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write);
262	PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction );
263	PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address );
264	PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next );
265
266	Tevent_type_t event_type = _decod_instruction->_event_type;
267	if (event_type != EVENT_TYPE_NONE)
268	{
269	log_printf(TRACE,Decod,FUNCTION," * Instruction make an EVENT (%s)",toString(event_type).c_str());
270	log_printf(TRACE,Decod,FUNCTION," * context_event_ack : %d",PORT_READ(in_CONTEXT_EVENT_ACK));
271
272	// speculative jump at the exception handler
273	// if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE
274	context_event_val = ifetch_ack [x][y]; // and decod_val [i]
275	decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable
276	ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack
277
278	CONTEXT_EVENT_CONTEXT_ID = x;
279	CONTEXT_EVENT_DEPTH = depth;
280	CONTEXT_EVENT_TYPE = _decod_instruction->_event_type;
281	CONTEXT_EVENT_IS_DELAY_SLOT = _decod_instruction->_is_delay_slot;
282	CONTEXT_EVENT_ADDRESS = _decod_instruction->_address;
283	CONTEXT_EVENT_ADDRESS_EPCR = _decod_instruction->_address_next ;
284	}
285
286	// fetch_ack =
287	// ((event_type == EVENT_TYPE_NONE) or ((event_type != EVENT_TYPE_NONE) and context_event_ack)) and
288	// ((type == TYPE_BRANCH ) or ((type != TYPE_BRANCH ) and predict_ack )) and
289	// fetch_val and decod_ack and decod_enable and true (is decod_val)
290
291	// To compute the "next previous" address
292	Tcontrol_t have_transaction = ifetch_ack [x][y];
293
294	internal_CONTEXT_HAVE_TRANSACTION [x] \|= have_transaction;
295	if (have_transaction)
296	{
297	internal_CONTEXT_ADDRESS_PREVIOUS [x] = addr;
298	internal_CONTEXT_IS_DELAY_SLOT [x] = (type == TYPE_BRANCH); // next is a delay slot if current have branch type
299	// internal_CONTEXT_SAVE_RAT [x] = ((type == TYPE_BRANCH) and not no_execute);
300	}
301
302	can_continue [x] &= have_transaction; // to have a in order decod !!! if a previous instruction can decod, also next instruction can't decod.
303
304	log_printf(TRACE,Decod,FUNCTION," * have_transaction : %d",have_transaction);
305
306	}
307
308	log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y);
309	log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]);
310	log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val );
311	log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] );
312	log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] );
313
314	it ++;
315	}
316	}
317
318	//-----------------------------------
319	// Write output
320	//-----------------------------------
321
322	for (uint32_t i=0; i<_param->_nb_context; i++)
323	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
324	PORT_WRITE(out_IFETCH_ACK [i][j], ifetch_ack [i][j]);
325
326	PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val);
327	if (_param->_have_port_context_id)
328	PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , CONTEXT_EVENT_CONTEXT_ID );
329	if (_param->_have_port_depth)
330	PORT_WRITE(out_CONTEXT_EVENT_DEPTH , CONTEXT_EVENT_DEPTH );
331	PORT_WRITE(out_CONTEXT_EVENT_TYPE , CONTEXT_EVENT_TYPE );
332	PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, CONTEXT_EVENT_IS_DELAY_SLOT);
333	PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , CONTEXT_EVENT_ADDRESS );
334	PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , CONTEXT_EVENT_ADDRESS_EPCR );
335
336	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
337	{
338	PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]);
339	PORT_WRITE(out_DECOD_VAL [i], decod_val [i]);
340
341	#ifdef STATISTICS
342	internal_DECOD_VAL [i] = decod_val [i];
343	#endif
344	}
345	}
346	else
347	{
348	for (uint32_t i=0; i<_param->_nb_context; i++)
349	{
350	internal_CONTEXT_HAVE_TRANSACTION [i] = false;
351	// internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i];
352	// internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i];
353	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
354	PORT_WRITE(out_IFETCH_ACK [i][j], 0);
355	}
356
357	PORT_WRITE(out_CONTEXT_EVENT_VAL, 0);
358
359	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
360	{
361	PORT_WRITE(out_PREDICT_VAL [i], 0);
362	PORT_WRITE(out_DECOD_VAL [i], 0);
363
364	#ifdef STATISTICS
365	internal_DECOD_VAL [i] = 0;
366	#endif
367	}
368	}
369
370	log_end(Decod,FUNCTION);
371	};
372
373	}; // end namespace decod
374	}; // end namespace decod_unit
375	}; // end namespace front_end
376	}; // end namespace multi_front_end
377	}; // end namespace core
378
379	}; // end namespace behavioural
380	}; // end namespace morpheo
381	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp @ 145

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