Changeset 145 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
- Timestamp:
- Oct 13, 2010, 8:15:51 PM (14 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r139 r145 71 71 std::list<generic::priority::select_t> * select = _priority->select(); 72 72 std::list<generic::priority::select_t>::iterator it=select->begin(); 73 73 74 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 74 75 { … … 76 77 77 78 bool ifetch_val = false; 78 while ((it != select->end()) and // have a no scanned "slot_in" ? 79 80 while ((it != select->end()) and // have a no scanned instruction from ifetch_unit ? 79 81 // (decod_val [i] == false) and // have not a previous selected entry? 80 82 (ifetch_val == false) and // not find ifetch instruction valid 81 (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) 83 (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) (ONCE CONTEXT PER CYCLE (context state moore easy)) 82 84 { 83 85 // predict_val [i] = false; 84 86 85 Tcontext_t x = it->grp; 86 uint32_t y = it->elt; 87 Tcontext_t x = it->grp; // num_front_end 88 uint32_t y = it->elt; // num_instruction 87 89 88 90 log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); … … 102 104 Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]); 103 105 106 // Read instruction and set default value 104 107 _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); 105 108 _decod_instruction->_context_id = x; … … 132 135 _decod_instruction->_branch_direction = 0; // not necessary 133 136 _decod_instruction->_event_type = EVENT_TYPE_NONE; // not necessary 134 135 136 137 // Test IFetch exception 137 138 // Test if ifetch_unit have an exception (per example : IBERR) 138 139 Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]); 139 140 140 141 if (ifetch_exception == EXCEPTION_IFETCH_NONE) 141 142 { 142 // Decod !143 // No exception, can Decod ! 143 144 log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2)); 144 145 log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); … … 150 151 else 151 152 { 152 // No decod : nop 153 // Exception : transform this instruction in a nop 154 // * INSTRUCTION_TLB 155 // * INSTRUCTION_PAGE 156 // * BUS_ERROR 157 158 log_printf(TRACE,Decod,FUNCTION," * exception -> change instruction in a l.nop"); 159 153 160 instruction_l_nop (_decod_instruction, _decod_param[x]); 154 161 … … 156 163 _decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception); 157 164 158 // INSTRUCTION_TLB159 // INSTRUCTION_PAGE160 // BUS_ERROR161 165 if (_decod_instruction->_is_delay_slot) 162 166 _decod_instruction->_address_next = _decod_instruction->_address_previous; … … 167 171 } 168 172 169 Ttype_t type = _decod_instruction->_type; 170 // Depth current. If have decod a branch and i can continue : depth = depth_next 171 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; 172 // Tcontrol_t save_rat = internal_CONTEXT_SAVE_RAT [x]; 173 Tcontrol_t no_execute = _decod_instruction->_no_execute; 174 173 Ttype_t type = _decod_instruction->_type; 174 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; 175 Tbranch_condition_t branch_condition = _decod_instruction->_branch_condition; 176 177 // Save RAT if instruction is a branch and is conditionnal (not l.j and not l.jal) 178 179 //Tcontrol_t save_rat = internal_CONTEXT_SAVE_RAT [x]; 180 // Tcontrol_t save_rat = ((type == TYPE_BRANCH) and 181 // not ((branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK) or 182 // (branch_condition==BRANCH_CONDITION_NONE_WITH_WRITE_STACK))); 183 184 Tcontrol_t save_rat = ((type == TYPE_BRANCH) and 185 not (branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK)); 186 187 // FIXME : depth+1 valid ??????? 175 188 if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x]) 176 189 depth = (depth+1)%_param->_nb_branch_speculated[x]; 177 190 191 // Write output 178 192 if (_param->_have_port_context_id) 179 193 PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); … … 185 199 PORT_WRITE(out_DECOD_TYPE [i], type); 186 200 PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); 187 PORT_WRITE(out_DECOD_NO_EXECUTE [i], no_execute);201 PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); 188 202 PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); 189 // PORT_WRITE(out_DECOD_SAVE_RAT [i], save_rat); 190 PORT_WRITE(out_DECOD_SAVE_RAT [i], ((type == TYPE_BRANCH) and not no_execute)); 203 PORT_WRITE(out_DECOD_SAVE_RAT [i], save_rat); 191 204 #ifdef DEBUG 192 205 PORT_WRITE(out_DECOD_ADDRESS [i], addr); 193 206 #endif 194 // if ((type == TYPE_BRANCH) and195 // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or196 // (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET)))197 // PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address+2);198 // else199 207 PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next ); 200 208 PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); … … 206 214 PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); 207 215 PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); 208 PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); 216 PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); // don't write in RD if RD=0 209 217 PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); 210 218 PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); … … 224 232 log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]); 225 233 log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); 226 227 234 log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); 228 235 log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); 229 236 230 // test if have already decod an branch : one branch per context 231 predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y] // and decod_val [i] 232 ; 237 // test if have already decod an branch : ONCE BRANCH PER CONTEXT 238 predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y]; // and decod_val [i] 233 239 decod_val [i] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable 234 240 ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack … … 252 258 if (_param->_have_port_depth) 253 259 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y])); 254 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i], _decod_instruction->_branch_condition);260 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],branch_condition); 255 261 // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); 256 262 PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); … … 266 272 // speculative jump at the exception handler 267 273 // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE 268 context_event_val = ifetch_ack [x][y] // and decod_val [i] 269 ; 274 context_event_val = ifetch_ack [x][y]; // and decod_val [i] 270 275 decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable 271 276 ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack … … 277 282 CONTEXT_EVENT_ADDRESS = _decod_instruction->_address; 278 283 CONTEXT_EVENT_ADDRESS_EPCR = _decod_instruction->_address_next ; 279 280 284 } 281 285
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