[83] | 1 | /* |
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| 2 | * $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #define NB_ITERATION 1 |
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[87] | 10 | #define CYCLE_MAX (10240*NB_ITERATION) |
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[83] | 11 | |
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| 12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/include/test.h" |
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[87] | 13 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h" |
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[83] | 14 | #include "Common/include/Test.h" |
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| 15 | #include "Behavioural/include/Allocation.h" |
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| 16 | |
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| 17 | void test (string name, |
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| 18 | morpheo::behavioural::core::multi_front_end::front_end::decod_unit::Parameters * _param) |
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| 19 | { |
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| 20 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 21 | |
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| 22 | #ifdef STATISTICS |
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[87] | 23 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); |
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[83] | 24 | #endif |
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| 25 | |
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| 26 | Tusage_t _usage = USE_ALL; |
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| 27 | |
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| 28 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 29 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 30 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 31 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 32 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 33 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 34 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 35 | |
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| 36 | Decod_unit * _Decod_unit = new Decod_unit |
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| 37 | (name.c_str(), |
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| 38 | #ifdef STATISTICS |
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| 39 | _parameters_statistics, |
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| 40 | #endif |
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| 41 | _param, |
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| 42 | _usage); |
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| 43 | |
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| 44 | #ifdef SYSTEMC |
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| 45 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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| 46 | { |
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| 47 | /********************************************************************* |
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| 48 | * Déclarations des signaux |
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| 49 | *********************************************************************/ |
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| 50 | string rename; |
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| 51 | |
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| 52 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 53 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 54 | |
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[88] | 55 | ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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| 56 | ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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| 57 | ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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[83] | 58 | |
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| 59 | ALLOC1_SC_SIGNAL(in_IFETCH_CONTEXT_ID ,"in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); |
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| 60 | ALLOC1_SC_SIGNAL(in_IFETCH_ADDRESS ,"in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context); |
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| 61 | //ALLOC1_SC_SIGNAL(in_IFETCH_ADDRESS_NEXT ,"in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context); |
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| 62 | ALLOC1_SC_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,"in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); |
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| 63 | ALLOC1_SC_SIGNAL(in_IFETCH_BRANCH_STATE ,"in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); |
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| 64 | ALLOC1_SC_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,"in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context); |
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[88] | 65 | ALLOC1_SC_SIGNAL(in_IFETCH_EXCEPTION ,"in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context); |
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[83] | 66 | |
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| 67 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 68 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 69 | ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); |
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| 70 | ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod); |
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| 71 | ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod); |
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| 72 | ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod); |
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[88] | 73 | ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); |
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[83] | 74 | ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 75 | ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 76 | ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 77 | ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 78 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 79 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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| 80 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 81 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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| 82 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 83 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod); |
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| 84 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 85 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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| 86 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 87 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); |
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| 88 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); |
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[88] | 89 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); |
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[83] | 90 | |
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| 91 | ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 92 | ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 93 | ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); |
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| 94 | ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 95 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod); |
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| 96 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod); |
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| 97 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod); |
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| 98 | //ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 99 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 100 | ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 101 | ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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| 102 | //ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); |
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| 103 | |
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[88] | 104 | ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); |
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| 105 | ALLOC1_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); |
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[83] | 106 | |
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| 107 | ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context); |
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| 108 | |
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| 109 | ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); |
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| 110 | ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); |
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| 111 | |
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| 112 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); |
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| 113 | ALLOC_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); |
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| 114 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); |
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[88] | 115 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); |
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[83] | 116 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); |
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| 117 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); |
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| 118 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); |
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| 119 | ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); |
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| 120 | |
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| 121 | /******************************************************** |
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| 122 | * Instanciation |
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| 123 | ********************************************************/ |
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| 124 | |
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| 125 | msg(_("<%s> : Instanciation of _Decod_unit.\n"),name.c_str()); |
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| 126 | |
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| 127 | (*(_Decod_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 128 | (*(_Decod_unit->in_NRESET)) (*(in_NRESET)); |
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| 129 | |
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[88] | 130 | INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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| 131 | INSTANCE2_SC_SIGNAL(_Decod_unit,out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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| 132 | INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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[83] | 133 | if (_param->_have_port_context_id) |
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| 134 | INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_CONTEXT_ID ,_param->_nb_context); |
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| 135 | INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_ADDRESS ,_param->_nb_context); |
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| 136 | //INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); |
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[88] | 137 | |
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| 138 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 139 | { |
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| 140 | if (_param->_have_port_inst_ifetch_ptr) |
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| 141 | INSTANCE_SC_SIGNAL(_Decod_unit,in_IFETCH_INST_IFETCH_PTR[i]); |
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| 142 | if (_param->_have_port_depth) |
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| 143 | INSTANCE_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); |
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| 144 | } |
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| 145 | |
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[83] | 146 | INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_STATE ,_param->_nb_context); |
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[88] | 147 | INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_EXCEPTION ,_param->_nb_context); |
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[83] | 148 | |
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| 149 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_VAL ,_param->_nb_inst_decod); |
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| 150 | INSTANCE1_SC_SIGNAL(_Decod_unit, in_DECOD_ACK ,_param->_nb_inst_decod); |
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| 151 | if (_param->_have_port_context_id) |
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| 152 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod); |
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| 153 | if (_param->_have_port_depth) |
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| 154 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_DEPTH ,_param->_nb_inst_decod); |
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| 155 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_TYPE ,_param->_nb_inst_decod); |
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| 156 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_OPERATION ,_param->_nb_inst_decod); |
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[88] | 157 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); |
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[83] | 158 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); |
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| 159 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS ,_param->_nb_inst_decod); |
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| 160 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); |
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| 161 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); |
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| 162 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_READ_RA ,_param->_nb_inst_decod); |
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| 163 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod); |
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| 164 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_READ_RB ,_param->_nb_inst_decod); |
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| 165 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod); |
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| 166 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_READ_RC ,_param->_nb_inst_decod); |
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| 167 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod); |
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| 168 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_WRITE_RD ,_param->_nb_inst_decod); |
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| 169 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod); |
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| 170 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_WRITE_RE ,_param->_nb_inst_decod); |
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| 171 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); |
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| 172 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); |
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[88] | 173 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_EXCEPTION ,_param->_nb_inst_decod); |
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[83] | 174 | |
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| 175 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_VAL ,_param->_nb_inst_decod); |
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| 176 | INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_ACK ,_param->_nb_inst_decod); |
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| 177 | if (_param->_have_port_context_id) |
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| 178 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod); |
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| 179 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); |
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| 180 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); |
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[88] | 181 | if (_param->_have_port_depth) |
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[83] | 182 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); |
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| 183 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); |
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| 184 | //INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod); |
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| 185 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod); |
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| 186 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); |
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| 187 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); |
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| 188 | //INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); |
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| 189 | |
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[88] | 190 | INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_MAX ,_param->_nb_context); |
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[83] | 191 | |
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| 192 | INSTANCE1_SC_SIGNAL(_Decod_unit,out_NB_INST_DECOD_ALL ,_param->_nb_context); |
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| 193 | |
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| 194 | INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); |
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| 195 | |
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[88] | 196 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 197 | if (_param->_have_port_depth) |
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| 198 | { |
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| 199 | INSTANCE_SC_SIGNAL(_Decod_unit, in_DEPTH_MIN [i]); |
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| 200 | INSTANCE_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH [i]); |
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| 201 | } |
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| 202 | |
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[83] | 203 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_VAL ); |
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| 204 | INSTANCE_SC_SIGNAL( _Decod_unit, in_CONTEXT_EVENT_ACK ); |
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| 205 | if (_param->_have_port_context_id) |
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| 206 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_CONTEXT_ID ); |
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[88] | 207 | if (_param->_have_port_depth) |
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| 208 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_DEPTH ); |
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[83] | 209 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_TYPE ); |
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| 210 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_IS_DELAY_SLOT ); |
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| 211 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS ); |
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| 212 | INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS_EPCR ); |
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| 213 | |
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| 214 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 215 | |
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| 216 | Time * _time = new Time(); |
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| 217 | |
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| 218 | /******************************************************** |
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| 219 | * Simulation - Begin |
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| 220 | ********************************************************/ |
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| 221 | |
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| 222 | // Initialisation |
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| 223 | |
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| 224 | const uint32_t seed = 0; |
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| 225 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 226 | |
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[87] | 227 | const int32_t percent_transaction_ifetch = 100; |
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| 228 | const int32_t percent_transaction_decod = 100; |
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| 229 | const int32_t percent_transaction_predict = 100; |
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| 230 | const int32_t percent_transaction_event = 100; |
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| 231 | |
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[83] | 232 | srand(seed); |
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| 233 | |
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| 234 | SC_START(0); |
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| 235 | LABEL("Initialisation"); |
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| 236 | |
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| 237 | LABEL("Reset"); |
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| 238 | in_NRESET->write(0); |
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| 239 | SC_START(5); |
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| 240 | in_NRESET->write(1); |
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| 241 | |
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| 242 | LABEL("Loop of Test"); |
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| 243 | |
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| 244 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 245 | { |
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| 246 | LABEL("Iteration %d",iteration); |
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| 247 | |
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[87] | 248 | Decod_request request [_param->_nb_context]; |
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| 249 | list<entry_t> respons [_param->_nb_context]; |
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| 250 | |
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| 251 | uint32_t nb_request = 0; |
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| 252 | |
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| 253 | uint32_t delay_slot_previous [_param->_nb_context]; |
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| 254 | uint32_t delay_slot_current [_param->_nb_context]; |
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| 255 | uint32_t delay_slot_next [_param->_nb_context]; |
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| 256 | |
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| 257 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 258 | { |
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| 259 | nb_request += request[i].size(); |
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| 260 | delay_slot_current [i] = false; |
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| 261 | delay_slot_next [i] = false; |
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| 262 | |
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[88] | 263 | in_DEPTH_MIN [i]->write(0); |
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| 264 | in_DEPTH_MAX [i]->write(0); |
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[87] | 265 | in_CONTEXT_DEPTH [i]->write(0); |
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| 266 | } |
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| 267 | |
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| 268 | while (nb_request > 0) |
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| 269 | { |
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| 270 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 271 | { |
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| 272 | delay_slot_previous [i] = false; |
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| 273 | |
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| 274 | in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod); |
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| 275 | |
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| 276 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 277 | in_IFETCH_VAL [i][j]->write(0); |
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| 278 | |
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| 279 | if ((rand()%100)<percent_transaction_ifetch) |
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| 280 | { |
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| 281 | list<entry_t>::iterator it = request[i].begin(); |
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| 282 | |
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| 283 | if (it!=request [i].end()) |
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| 284 | { |
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| 285 | uint32_t lsb = it->_address%_param->_nb_inst_fetch[i]; |
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| 286 | |
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| 287 | in_IFETCH_ADDRESS [i]->write(it->_address-lsb); |
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| 288 | in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE); |
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| 289 | if (_param->_have_port_inst_ifetch_ptr) |
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| 290 | in_IFETCH_INST_IFETCH_PTR [i]->write(0); |
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| 291 | |
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| 292 | // Alignement |
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| 293 | for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++) |
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| 294 | { |
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| 295 | in_IFETCH_VAL [i][j]->write(1); |
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| 296 | in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction); |
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| 297 | // in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next); |
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| 298 | if (it->_type == TYPE_BRANCH) |
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| 299 | in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state); |
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| 300 | in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id); |
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[88] | 301 | in_IFETCH_EXCEPTION [i]->write(it->_exception_ifetch); |
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[87] | 302 | |
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| 303 | if ((it->_is_delay_slot) or |
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| 304 | ((++it)==request [i].end())) |
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| 305 | break; |
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| 306 | } |
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| 307 | } |
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| 308 | } |
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| 309 | } |
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| 310 | |
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| 311 | { |
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| 312 | bool previous_ack = true; |
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| 313 | |
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| 314 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 315 | { |
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| 316 | bool ack = previous_ack and ((rand()%100)<percent_transaction_decod); |
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| 317 | in_DECOD_ACK [i]->write(ack); |
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| 318 | |
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| 319 | previous_ack = ack; |
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| 320 | |
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| 321 | in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict); |
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| 322 | // in_PREDICT_CAN_CONTINUE [i]->write(0); |
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| 323 | } |
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| 324 | } |
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| 325 | |
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| 326 | in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event); |
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| 327 | |
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| 328 | SC_START(0); |
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| 329 | |
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| 330 | uint32_t find_event = false; |
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| 331 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 332 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 333 | if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read()) |
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| 334 | { |
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| 335 | LABEL("IFETCH [%d][%d] : transaction",i,j); |
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| 336 | |
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| 337 | entry_t entry = request [i].front(); |
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| 338 | LABEL(" * address 0x%x",entry._address); |
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| 339 | |
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| 340 | respons [i].push_back(entry); |
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| 341 | request [i].pop_front(); |
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| 342 | |
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| 343 | if (entry._type == TYPE_BRANCH) |
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| 344 | { |
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| 345 | delay_slot_next [i] = true; |
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| 346 | |
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| 347 | // find good decod |
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| 348 | uint32_t x; |
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| 349 | |
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| 350 | for (x=0; x<=_param->_nb_inst_decod; x++) |
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| 351 | { |
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| 352 | if (x==_param->_nb_inst_decod) |
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| 353 | TEST_KO("No find predict transaction"); |
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| 354 | |
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| 355 | Tcontext_t ctxt = (_param->_have_port_context_id)?out_PREDICT_CONTEXT_ID[x]->read():0; |
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| 356 | |
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| 357 | if ((ctxt == i) and |
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| 358 | (out_PREDICT_VAL [x]->read() and in_PREDICT_ACK [x]->read())) |
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| 359 | break; |
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| 360 | } |
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| 361 | |
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| 362 | LABEL("PREDICT [%d] : transaction",x ); |
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| 363 | |
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| 364 | |
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| 365 | TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [x]->read(),((entry._address)%_param->_nb_inst_fetch[i]) == 0); |
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| 366 | TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [x]->read(), entry._branch_state ); |
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[88] | 367 | if (_param->_have_port_depth) |
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[87] | 368 | TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x]->read(), entry._branch_update_prediction_id); |
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| 369 | TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [x]->read(), entry._branch_condition ); |
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| 370 | // TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [x]->read(), entry._branch_stack_write ); |
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| 371 | TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [x]->read(), entry._branch_direction ); |
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| 372 | TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [x]->read(), entry._address ); |
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| 373 | TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [x]->read(), entry._branch_address_dest ); |
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| 374 | } |
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| 375 | |
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| 376 | // TEST(bool, find_event, false); // can continue decod after event |
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| 377 | if (entry._context_event_type != EVENT_TYPE_NONE) |
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| 378 | { |
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| 379 | find_event = true; |
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| 380 | |
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| 381 | LABEL("CONTEXT_EVENT : transaction"); |
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| 382 | |
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| 383 | if (_param->_have_port_context_id) |
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[88] | 384 | TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), i); |
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| 385 | if (_param->_have_port_depth) |
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| 386 | TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), entry._depth); |
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[87] | 387 | TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), entry._context_event_type); |
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| 388 | TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), entry._is_delay_slot); |
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| 389 | TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), entry._address ); |
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| 390 | TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), entry._address_next ); |
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| 391 | } |
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| 392 | |
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| 393 | TEST(bool, delay_slot_previous [i], false); // can't continue |
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| 394 | delay_slot_previous [i] = delay_slot_current [i]; |
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| 395 | delay_slot_current [i] = delay_slot_next [i]; |
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| 396 | delay_slot_next [i] = false; |
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| 397 | } |
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| 398 | |
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| 399 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 400 | if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read()) |
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| 401 | { |
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| 402 | Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0; |
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| 403 | |
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| 404 | LABEL("DECOD [%d] : transaction",i ); |
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| 405 | |
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| 406 | TEST(bool ,respons [context].empty(), false); |
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| 407 | |
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| 408 | LABEL(" * context : %d",context); |
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| 409 | LABEL(" * instruction : 0x%x",respons [context].front()._instruction); |
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| 410 | |
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| 411 | if (_param->_have_port_depth) |
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| 412 | TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), respons [context].front()._depth ); |
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| 413 | TEST(Ttype_t , out_DECOD_TYPE [i]->read(), respons [context].front()._type ); |
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| 414 | TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), respons [context].front()._operation ); |
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[88] | 415 | // TEST(Tcontrol_t , out_DECOD_NO_EXECUTE [i]->read(), respons [context].front()._no_execute ); |
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[87] | 416 | TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), respons [context].front()._is_delay_slot); |
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| 417 | TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), respons [context].front()._address ); |
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| 418 | TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), respons [context].front()._has_immediat ); |
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| 419 | if (respons [context].front()._has_immediat) |
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| 420 | TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), respons [context].front()._immediat ); |
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| 421 | TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), respons [context].front()._read_ra ); |
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| 422 | if (respons [context].front()._read_ra) |
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| 423 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), respons [context].front()._num_reg_ra ); |
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| 424 | TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), respons [context].front()._read_rb ); |
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| 425 | if (respons [context].front()._read_rb) |
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| 426 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), respons [context].front()._num_reg_rb ); |
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| 427 | TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), respons [context].front()._read_rc ); |
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| 428 | if (respons [context].front()._read_rc) |
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| 429 | TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), respons [context].front()._num_reg_rc ); |
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| 430 | TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), respons [context].front()._write_rd ); |
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| 431 | if (respons [context].front()._write_rd) |
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| 432 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), respons [context].front()._num_reg_rd ); |
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| 433 | TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), respons [context].front()._write_re ); |
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| 434 | if (respons [context].front()._write_re) |
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| 435 | TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), respons [context].front()._num_reg_re ); |
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| 436 | TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), respons [context].front()._exception_use); |
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[88] | 437 | // TEST(Texception_t , out_DECOD_EXCEPTION [i]->read(), respons [context].front()._exception ); |
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[87] | 438 | |
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| 439 | respons [context].pop_front(); |
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| 440 | nb_request --; |
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| 441 | } |
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| 442 | |
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| 443 | TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event); |
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| 444 | |
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| 445 | SC_START(1); |
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| 446 | } |
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| 447 | |
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| 448 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 449 | { |
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| 450 | TEST(Tcounter_t,out_NB_INST_DECOD_ALL [i]->read(), respons[i].size()); |
---|
| 451 | |
---|
| 452 | } |
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[83] | 453 | } |
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| 454 | |
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| 455 | /******************************************************** |
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| 456 | * Simulation - End |
---|
| 457 | ********************************************************/ |
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| 458 | |
---|
| 459 | TEST_OK ("End of Simulation"); |
---|
| 460 | delete _time; |
---|
| 461 | |
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| 462 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 463 | |
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| 464 | delete in_CLOCK; |
---|
| 465 | delete in_NRESET; |
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| 466 | |
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[88] | 467 | DELETE2_SC_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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| 468 | DELETE2_SC_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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| 469 | DELETE2_SC_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1]); |
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[83] | 470 | DELETE1_SC_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context); |
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| 471 | DELETE1_SC_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context); |
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| 472 | //DELETE1_SC_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); |
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| 473 | DELETE1_SC_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context); |
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| 474 | DELETE1_SC_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context); |
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| 475 | DELETE1_SC_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context); |
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[88] | 476 | DELETE1_SC_SIGNAL(in_IFETCH_EXCEPTION ,_param->_nb_context); |
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[83] | 477 | |
---|
| 478 | DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod); |
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| 479 | DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_nb_inst_decod); |
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| 480 | DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod); |
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| 481 | DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_nb_inst_decod); |
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| 482 | DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_nb_inst_decod); |
---|
| 483 | DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_nb_inst_decod); |
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[88] | 484 | DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); |
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[83] | 485 | DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); |
---|
| 486 | DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod); |
---|
| 487 | DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); |
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| 488 | DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); |
---|
| 489 | DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_nb_inst_decod); |
---|
| 490 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod); |
---|
| 491 | DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_nb_inst_decod); |
---|
| 492 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod); |
---|
| 493 | DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_nb_inst_decod); |
---|
| 494 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod); |
---|
| 495 | DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_nb_inst_decod); |
---|
| 496 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod); |
---|
| 497 | DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_nb_inst_decod); |
---|
| 498 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); |
---|
| 499 | DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); |
---|
[88] | 500 | DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_inst_decod); |
---|
[83] | 501 | |
---|
| 502 | DELETE1_SC_SIGNAL(out_PREDICT_VAL ,_param->_nb_inst_decod); |
---|
| 503 | DELETE1_SC_SIGNAL( in_PREDICT_ACK ,_param->_nb_inst_decod); |
---|
| 504 | DELETE1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod); |
---|
| 505 | DELETE1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); |
---|
| 506 | DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); |
---|
| 507 | DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); |
---|
| 508 | DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); |
---|
| 509 | //DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod); |
---|
| 510 | DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod); |
---|
| 511 | DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); |
---|
| 512 | DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); |
---|
| 513 | //DELETE1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); |
---|
| 514 | |
---|
[88] | 515 | DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context); |
---|
| 516 | DELETE1_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_context); |
---|
[83] | 517 | |
---|
| 518 | DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); |
---|
| 519 | |
---|
| 520 | DELETE1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); |
---|
| 521 | DELETE1_SC_SIGNAL( in_CONTEXT_DEPTH ,_param->_nb_context); |
---|
| 522 | |
---|
| 523 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_VAL ); |
---|
| 524 | DELETE_SC_SIGNAL( in_CONTEXT_EVENT_ACK ); |
---|
| 525 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ); |
---|
[88] | 526 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ); |
---|
[83] | 527 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ); |
---|
| 528 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ); |
---|
| 529 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS ); |
---|
| 530 | DELETE_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS_EPCR ); |
---|
| 531 | } |
---|
| 532 | #endif |
---|
| 533 | |
---|
| 534 | delete _Decod_unit; |
---|
| 535 | #ifdef STATISTICS |
---|
| 536 | delete _parameters_statistics; |
---|
| 537 | #endif |
---|
| 538 | } |
---|