[78] | 1 | /* |
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| 2 | * $Id: test.cpp 131 2009-07-08 18:40:08Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | |
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| 10 | #define NB_ITERATION 1024 |
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| 11 | #define CYCLE_MAX (128*NB_ITERATION) |
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| 12 | |
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[82] | 13 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h" |
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| 14 | #include "Common/include/Test.h" |
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| 15 | #include "Behavioural/include/Allocation.h" |
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[78] | 16 | |
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| 17 | void test (string name, |
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| 18 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param) |
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| 19 | { |
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| 20 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 21 | |
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| 22 | #ifdef STATISTICS |
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| 23 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 24 | #endif |
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| 25 | |
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[131] | 26 | _model.set_model(MODEL_SYSTEMC, true); |
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| 27 | |
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[88] | 28 | Tusage_t _usage = USE_ALL; |
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| 29 | |
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| 30 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 31 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 32 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 33 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 34 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 35 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 36 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 37 | |
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[82] | 38 | Address_management * _Address_management = new Address_management |
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| 39 | (name.c_str(), |
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[78] | 40 | #ifdef STATISTICS |
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[82] | 41 | _parameters_statistics, |
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[78] | 42 | #endif |
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[82] | 43 | _param, |
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[88] | 44 | _usage); |
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[78] | 45 | |
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| 46 | #ifdef SYSTEMC |
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| 47 | /********************************************************************* |
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| 48 | * Déclarations des signaux |
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| 49 | *********************************************************************/ |
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| 50 | string rename; |
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| 51 | |
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| 52 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 53 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 54 | |
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[113] | 55 | sc_signal<Tcontrol_t > * out_ADDRESS_VAL ; |
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| 56 | sc_signal<Tcontrol_t > * in_ADDRESS_ACK ; //icache_req_ack and ifetch_queue_ack |
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| 57 | sc_signal<Tgeneral_address_t> * out_ADDRESS_INSTRUCTION_ADDRESS ; |
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| 58 | sc_signal<Tcontrol_t > ** out_ADDRESS_INSTRUCTION_ENABLE ; //[nb_instruction] |
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| 59 | sc_signal<Tinst_ifetch_ptr_t> * out_ADDRESS_INST_IFETCH_PTR ; |
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| 60 | sc_signal<Tbranch_state_t > * out_ADDRESS_BRANCH_STATE ; |
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| 61 | sc_signal<Tprediction_ptr_t > * out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ; |
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| 62 | sc_signal<Tcontrol_t > * out_PREDICT_VAL ; |
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| 63 | sc_signal<Tcontrol_t > * in_PREDICT_ACK ; |
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| 64 | sc_signal<Tgeneral_address_t> * out_PREDICT_PC_PREVIOUS ; |
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| 65 | sc_signal<Tgeneral_address_t> * out_PREDICT_PC_CURRENT ; |
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| 66 | sc_signal<Tcontrol_t > * out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
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| 67 | sc_signal<Tgeneral_address_t> * in_PREDICT_PC_NEXT ; |
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| 68 | sc_signal<Tcontrol_t > * in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
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| 69 | sc_signal<Tcontrol_t > ** in_PREDICT_INSTRUCTION_ENABLE ; //[nb_instruction] |
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| 70 | //sc_signal<Tcontrol_t > * in_PREDICT_BRANCH_IS_CURRENT ; |
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| 71 | sc_signal<Tbranch_state_t > * in_PREDICT_BRANCH_STATE ; |
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| 72 | sc_signal<Tprediction_ptr_t > * in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; |
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| 73 | sc_signal<Tinst_ifetch_ptr_t> * in_PREDICT_INST_IFETCH_PTR ; |
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| 74 | sc_signal<Tcontrol_t > * in_EVENT_VAL ; |
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| 75 | sc_signal<Tcontrol_t > * out_EVENT_ACK ; |
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| 76 | sc_signal<Tgeneral_address_t> * in_EVENT_ADDRESS ; |
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| 77 | sc_signal<Tgeneral_address_t> * in_EVENT_ADDRESS_NEXT ; |
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| 78 | sc_signal<Tcontrol_t > * in_EVENT_ADDRESS_NEXT_VAL ; |
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| 79 | sc_signal<Tcontrol_t > * in_EVENT_IS_DS_TAKE ; |
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| 80 | |
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[112] | 81 | ALLOC0_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); |
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| 82 | ALLOC0_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); |
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| 83 | ALLOC0_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); |
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[78] | 84 | ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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[112] | 85 | ALLOC0_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
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| 86 | ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); |
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| 87 | ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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| 88 | ALLOC0_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
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| 89 | ALLOC0_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
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| 90 | ALLOC0_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); |
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| 91 | ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); |
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| 92 | ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
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| 93 | ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); |
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| 94 | ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
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[78] | 95 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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[112] | 96 | ALLOC0_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
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| 97 | //ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); |
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| 98 | ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
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| 99 | ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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| 100 | ALLOC0_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
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| 101 | ALLOC0_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
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| 102 | ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); |
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| 103 | ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t); |
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| 104 | ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); |
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| 105 | ALLOC0_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); |
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[78] | 106 | |
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| 107 | /******************************************************** |
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| 108 | * Instanciation |
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| 109 | ********************************************************/ |
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| 110 | |
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| 111 | msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str()); |
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| 112 | |
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| 113 | (*(_Address_management->in_CLOCK)) (*(in_CLOCK)); |
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| 114 | (*(_Address_management->in_NRESET)) (*(in_NRESET)); |
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| 115 | |
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[112] | 116 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); |
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| 117 | INSTANCE0_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); |
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| 118 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); |
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[78] | 119 | INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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[88] | 120 | if (_param->_have_port_inst_ifetch_ptr) |
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[112] | 121 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); |
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| 122 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); |
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[88] | 123 | if (_param->_have_port_depth) |
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[112] | 124 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); |
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| 125 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); |
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| 126 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); |
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| 127 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); |
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| 128 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); |
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| 129 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
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| 130 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); |
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| 131 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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[78] | 132 | INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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[88] | 133 | if (_param->_have_port_inst_ifetch_ptr) |
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[112] | 134 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); |
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| 135 | //INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); |
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| 136 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); |
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[88] | 137 | if (_param->_have_port_depth) |
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[112] | 138 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 139 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_VAL ); |
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| 140 | INSTANCE0_SC_SIGNAL (_Address_management,out_EVENT_ACK ); |
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| 141 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); |
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| 142 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT ); |
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| 143 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL ); |
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| 144 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE ); |
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[78] | 145 | |
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| 146 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 147 | |
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| 148 | Time * _time = new Time(); |
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| 149 | |
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| 150 | /******************************************************** |
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| 151 | * Simulation - Begin |
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| 152 | ********************************************************/ |
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| 153 | |
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| 154 | // Initialisation |
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| 155 | |
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| 156 | const uint32_t seed = 0; |
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| 157 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 158 | |
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| 159 | srand(seed); |
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| 160 | |
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[101] | 161 | const int32_t percent_transaction_address = 100; |
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| 162 | const int32_t percent_transaction_predict = 100; |
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| 163 | const int32_t percent_transaction_event = 0; |
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[78] | 164 | |
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| 165 | SC_START(0); |
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| 166 | LABEL("Initialisation"); |
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| 167 | |
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| 168 | LABEL("Reset"); |
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| 169 | |
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| 170 | in_ADDRESS_ACK->write(0); |
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| 171 | out_PREDICT_VAL->write(0); |
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| 172 | in_EVENT_VAL ->write(0); |
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| 173 | |
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| 174 | in_NRESET->write(0); |
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| 175 | SC_START(5); |
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| 176 | in_NRESET->write(1); |
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| 177 | |
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| 178 | LABEL("Test Reset"); |
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| 179 | |
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| 180 | TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false); |
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| 181 | TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction |
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| 182 | TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event |
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| 183 | |
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[131] | 184 | #ifdef SELFTEST |
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[84] | 185 | uint32_t jump = 7 ;// packet |
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| 186 | uint32_t nb_packet = 1; |
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[78] | 187 | |
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[101] | 188 | Tcontrol_t a_val = false; |
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[84] | 189 | Tcontrol_t c_val = false; |
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[101] | 190 | Tcontrol_t n_val = true ; |
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[84] | 191 | Tcontrol_t nn_val = false; |
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| 192 | |
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[101] | 193 | Tgeneral_data_t a_addr = 0x100>>2; |
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[88] | 194 | Tgeneral_data_t c_addr = 0x100>>2; |
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| 195 | Tgeneral_data_t n_addr = 0x100>>2; |
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| 196 | Tgeneral_data_t nn_addr = 0x100>>2; |
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[84] | 197 | |
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[101] | 198 | Tcontrol_t a_enable [_param->_nb_instruction]; |
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[78] | 199 | Tcontrol_t c_enable [_param->_nb_instruction]; |
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| 200 | Tcontrol_t n_enable [_param->_nb_instruction]; |
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| 201 | |
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[101] | 202 | Tcontrol_t a_is_ds_take = 0; |
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[84] | 203 | Tcontrol_t c_is_ds_take = 0; |
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| 204 | Tcontrol_t n_is_ds_take = 0; |
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| 205 | Tcontrol_t nn_is_ds_take = 0; |
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[78] | 206 | |
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[101] | 207 | n_enable [0] = 1; |
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[78] | 208 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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[101] | 209 | n_enable [i] = 0; |
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[78] | 210 | |
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| 211 | LABEL("Send Reset"); |
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[88] | 212 | // do |
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| 213 | // { |
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| 214 | // in_EVENT_VAL ->write(1); |
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| 215 | // in_EVENT_ADDRESS ->write(n_addr); |
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| 216 | // in_EVENT_ADDRESS_NEXT ->write(nn_addr); |
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| 217 | // in_EVENT_ADDRESS_NEXT_VAL->write(0); |
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| 218 | // in_EVENT_IS_DS_TAKE ->write(0); |
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| 219 | // SC_START(1); |
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| 220 | // } while (out_EVENT_ACK->read() == false); |
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| 221 | // in_EVENT_VAL ->write(0); |
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[78] | 222 | |
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[84] | 223 | n_val = 1; |
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| 224 | |
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[78] | 225 | LABEL("Loop of Test"); |
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| 226 | |
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| 227 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 228 | { |
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| 229 | LABEL("Iteration %d",iteration); |
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| 230 | |
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[84] | 231 | // PREDICT |
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| 232 | { |
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| 233 | in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); |
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| 234 | |
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| 235 | SC_START(0); |
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[78] | 236 | |
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[84] | 237 | Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); |
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[78] | 238 | |
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[84] | 239 | uint32_t begin = addr%_param->_nb_instruction; |
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| 240 | uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); |
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| 241 | Tcontrol_t take = (nb_packet%jump)==0; |
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| 242 | |
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| 243 | if (take) |
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| 244 | addr += 0x100; |
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| 245 | else |
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| 246 | addr += end-begin+1; |
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[78] | 247 | |
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[84] | 248 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 249 | in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); |
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| 250 | in_PREDICT_PC_NEXT ->write(addr); |
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| 251 | in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); |
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| 252 | in_PREDICT_INST_IFETCH_PTR ->write(0); |
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[101] | 253 | // in_PREDICT_BRANCH_IS_CURRENT ->write(0); |
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[84] | 254 | in_PREDICT_BRANCH_STATE ->write(0); |
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| 255 | in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); |
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| 256 | } |
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| 257 | |
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| 258 | // ADDRESS |
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| 259 | { |
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| 260 | in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); |
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| 261 | } |
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| 262 | |
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[88] | 263 | in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); |
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| 264 | in_EVENT_ADDRESS ->write(0x77); |
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| 265 | in_EVENT_ADDRESS_NEXT ->write(0x171); |
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| 266 | Tcontrol_t next_val = rand()%2; |
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| 267 | in_EVENT_ADDRESS_NEXT_VAL->write(next_val); |
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| 268 | in_EVENT_IS_DS_TAKE ->write(next_val); |
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[84] | 269 | |
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| 270 | //------------------------------------------------- |
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[78] | 271 | SC_START(0); |
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[84] | 272 | //------------------------------------------------- |
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[78] | 273 | |
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| 274 | if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) |
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| 275 | { |
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| 276 | LABEL("PREDICT : Transaction accepted"); |
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| 277 | |
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[84] | 278 | if (c_val) |
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| 279 | TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); |
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| 280 | TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); |
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| 281 | TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); |
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| 282 | |
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| 283 | nn_val = true; |
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| 284 | nn_addr = in_PREDICT_PC_NEXT ->read(); |
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| 285 | nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); |
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| 286 | |
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| 287 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 288 | n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); |
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[101] | 289 | |
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| 290 | LABEL(" * nn_addr : %.8x",nn_addr); |
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[78] | 291 | } |
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[84] | 292 | |
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[78] | 293 | if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) |
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| 294 | { |
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| 295 | LABEL("ADDRESS : Transaction accepted"); |
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[101] | 296 | LABEL(" * address wait : %.8x",a_addr); |
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[78] | 297 | |
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[107] | 298 | TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr-a_addr%_param->_nb_instruction); |
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[78] | 299 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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[101] | 300 | TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]); |
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[88] | 301 | if (_param->_have_port_inst_ifetch_ptr) |
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[84] | 302 | TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); |
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| 303 | TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0); |
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[88] | 304 | if (_param->_have_port_depth) |
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[84] | 305 | TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); |
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[78] | 306 | |
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[101] | 307 | a_val = 0; |
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[84] | 308 | nb_packet ++; |
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| 309 | } |
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[78] | 310 | |
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[101] | 311 | { |
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| 312 | string str_a_enable = ""; |
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| 313 | string str_c_enable = ""; |
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| 314 | string str_n_enable = ""; |
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[78] | 315 | |
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[101] | 316 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 317 | { |
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| 318 | str_a_enable += " " + toString(a_enable [i]); |
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| 319 | str_c_enable += " " + toString(c_enable [i]); |
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| 320 | str_n_enable += " " + toString(n_enable [i]); |
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| 321 | } |
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| 322 | |
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| 323 | LABEL("----[ Before ]---------------------"); |
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| 324 | LABEL(" * nb_packet : %d",nb_packet); |
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| 325 | LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); |
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| 326 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); |
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| 327 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); |
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| 328 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); |
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| 329 | LABEL("-----------------------------------"); |
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| 330 | } |
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| 331 | |
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| 332 | if (not a_val) |
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[84] | 333 | { |
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[101] | 334 | if (c_val and n_val and nn_val) |
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| 335 | { |
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| 336 | a_val = 1; |
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| 337 | c_val = 0; |
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| 338 | a_addr = c_addr; |
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| 339 | a_is_ds_take = c_is_ds_take; |
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[78] | 340 | |
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| 341 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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[101] | 342 | a_enable [i] = c_enable [i]; |
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| 343 | } |
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| 344 | } |
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[78] | 345 | |
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[101] | 346 | if (not c_val) |
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| 347 | { |
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| 348 | c_val = n_val; |
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| 349 | if (n_val) |
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| 350 | { |
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| 351 | c_addr = n_addr; |
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| 352 | c_is_ds_take = n_is_ds_take; |
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| 353 | |
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| 354 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 355 | c_enable [i] = n_enable [i]; |
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| 356 | } |
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| 357 | n_val = 0; |
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| 358 | } |
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| 359 | |
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| 360 | if (not n_val) |
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| 361 | { |
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| 362 | n_val = nn_val; |
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| 363 | if (nn_val) |
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| 364 | { |
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| 365 | n_addr = nn_addr; |
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| 366 | n_is_ds_take = nn_is_ds_take; |
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| 367 | |
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| 368 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 369 | // n_enable [i] = nn_enable [i]; |
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| 370 | } |
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| 371 | nn_val = 0; |
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| 372 | } |
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| 373 | |
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[84] | 374 | if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) |
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[78] | 375 | { |
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[84] | 376 | LABEL("EVENT : Transaction accepted"); |
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[78] | 377 | |
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[101] | 378 | a_val = false; |
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[88] | 379 | c_val = false; |
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| 380 | n_val = true; |
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| 381 | n_addr = in_EVENT_ADDRESS ->read(); |
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| 382 | n_is_ds_take = in_EVENT_IS_DS_TAKE ->read(); |
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| 383 | nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); |
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| 384 | nn_addr = in_EVENT_ADDRESS_NEXT ->read(); |
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| 385 | nn_is_ds_take= false; |
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| 386 | // nn_val = false; |
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| 387 | // n_is_ds_take = 0; |
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[78] | 388 | |
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[84] | 389 | n_enable [0] = 1; |
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[88] | 390 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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| 391 | n_enable [i] = 0; |
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[78] | 392 | } |
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| 393 | |
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[84] | 394 | |
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| 395 | { |
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[101] | 396 | string str_a_enable = ""; |
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[84] | 397 | string str_c_enable = ""; |
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| 398 | string str_n_enable = ""; |
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[78] | 399 | |
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[84] | 400 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 401 | { |
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[101] | 402 | str_a_enable += " " + toString(a_enable [i]); |
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[84] | 403 | str_c_enable += " " + toString(c_enable [i]); |
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| 404 | str_n_enable += " " + toString(n_enable [i]); |
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| 405 | } |
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[78] | 406 | |
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[101] | 407 | LABEL("----[ After ]----------------------"); |
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[84] | 408 | LABEL(" * nb_packet : %d",nb_packet); |
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[101] | 409 | LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); |
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| 410 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); |
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| 411 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); |
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| 412 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); |
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[84] | 413 | LABEL("-----------------------------------"); |
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| 414 | } |
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[78] | 415 | |
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| 416 | SC_START(1); |
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| 417 | } |
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[131] | 418 | #else |
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| 419 | SC_START(100); |
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| 420 | #endif // SELFTEST |
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[78] | 421 | |
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| 422 | /******************************************************** |
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| 423 | * Simulation - End |
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| 424 | ********************************************************/ |
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| 425 | |
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| 426 | TEST_OK ("End of Simulation"); |
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| 427 | delete _time; |
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| 428 | |
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| 429 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 430 | |
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| 431 | delete in_CLOCK; |
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| 432 | delete in_NRESET; |
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| 433 | |
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| 434 | delete out_ADDRESS_VAL ; |
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| 435 | delete in_ADDRESS_ACK ; |
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| 436 | delete out_ADDRESS_INSTRUCTION_ADDRESS ; |
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| 437 | delete [] out_ADDRESS_INSTRUCTION_ENABLE ; |
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| 438 | delete out_ADDRESS_INST_IFETCH_PTR ; |
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| 439 | delete out_ADDRESS_BRANCH_STATE ; |
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| 440 | delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; |
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| 441 | delete out_PREDICT_VAL ; |
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| 442 | delete in_PREDICT_ACK ; |
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| 443 | delete out_PREDICT_PC_PREVIOUS ; |
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| 444 | delete out_PREDICT_PC_CURRENT ; |
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| 445 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
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| 446 | delete in_PREDICT_PC_NEXT ; |
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| 447 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
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| 448 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
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| 449 | delete in_PREDICT_INST_IFETCH_PTR ; |
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[101] | 450 | //delete in_PREDICT_BRANCH_IS_CURRENT ; |
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[78] | 451 | delete in_PREDICT_BRANCH_STATE ; |
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| 452 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; |
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| 453 | delete in_EVENT_VAL ; |
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| 454 | delete out_EVENT_ACK ; |
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| 455 | delete in_EVENT_ADDRESS ; |
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[88] | 456 | delete in_EVENT_ADDRESS_NEXT ; |
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| 457 | delete in_EVENT_ADDRESS_NEXT_VAL ; |
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| 458 | delete in_EVENT_IS_DS_TAKE ; |
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[78] | 459 | #endif |
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| 460 | |
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| 461 | delete _Address_management; |
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| 462 | #ifdef STATISTICS |
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| 463 | delete _parameters_statistics; |
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| 464 | #endif |
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| 465 | } |
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