1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Address_management_transition.cpp 111 2009-02-27 18:37:40Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace address_management { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Address_management::transition" |
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22 | void Address_management::transition (void) |
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23 | { |
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24 | log_begin(Address_management,FUNCTION); |
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25 | log_function(Address_management,FUNCTION,_name.c_str()); |
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26 | |
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27 | if (PORT_READ(in_NRESET) == 0) |
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28 | { |
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29 | // nothing is valid |
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30 | reg_PC_ACCESS_VAL = 0; |
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31 | |
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32 | reg_PC_CURRENT_VAL = 0; |
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33 | |
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34 | reg_PC_NEXT_VAL = 1; |
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35 | reg_PC_NEXT = 0x100>>2; |
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36 | reg_PC_NEXT_IS_DS_TAKE = 0; |
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37 | uint32_t index = reg_PC_NEXT % _param->_nb_instruction; |
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38 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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39 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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40 | reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; |
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41 | reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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42 | reg_PC_NEXT_BRANCH_STATE = 0; |
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43 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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44 | |
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45 | |
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46 | reg_PC_NEXT_NEXT_VAL = 0; |
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47 | } |
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48 | else |
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49 | { |
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50 | // ========================================= |
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51 | // ===== PREDICT =========================== |
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52 | // ========================================= |
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53 | if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) |
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54 | { |
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55 | log_printf(TRACE,Address_management,FUNCTION," * PREDICT"); |
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56 | |
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57 | bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; |
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58 | if (branch_is_current) |
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59 | { |
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60 | if (_param->_have_port_inst_ifetch_ptr) |
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61 | reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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62 | reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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63 | if (_param->_have_port_depth) |
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64 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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65 | } |
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66 | else |
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67 | { |
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68 | if (_param->_have_port_inst_ifetch_ptr) |
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69 | reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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70 | reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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71 | if (_param->_have_port_depth) |
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72 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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73 | } |
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74 | |
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75 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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76 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); |
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77 | |
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78 | reg_PC_NEXT_NEXT_VAL = 1; // address is valid |
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79 | reg_PC_NEXT_NEXT = PORT_READ(in_PREDICT_PC_NEXT ); |
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80 | reg_PC_NEXT_NEXT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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81 | |
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82 | #ifdef STATISTICS |
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83 | if (usage_is_set(_usage,USE_STATISTICS)) |
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84 | (*_stat_nb_transaction_predict) ++; |
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85 | #endif |
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86 | } |
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87 | |
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88 | // ========================================= |
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89 | // ===== ADDRESS =========================== |
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90 | // ========================================= |
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91 | // transaction with icache |
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92 | if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) |
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93 | { |
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94 | |
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95 | reg_PC_ACCESS_VAL = 0; |
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96 | #ifdef STATISTICS |
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97 | if (usage_is_set(_usage,USE_STATISTICS)) |
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98 | { |
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99 | (*_stat_nb_transaction_address) ++; |
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100 | |
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101 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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102 | if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true) |
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103 | (*_stat_sum_packet_size) ++; |
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104 | } |
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105 | #endif |
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106 | } |
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107 | |
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108 | // ========================================= |
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109 | // ===== Shift Register ==================== |
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110 | // ========================================= |
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111 | |
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112 | // Shift register |
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113 | if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and reg_PC_CURRENT_VAL and not reg_PC_ACCESS_VAL) |
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114 | { |
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115 | log_printf(TRACE,Address_management,FUNCTION," * New PC_ACCESS"); |
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116 | |
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117 | reg_PC_ACCESS_VAL = 1; // new request |
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118 | reg_PC_CURRENT_VAL = 0; // invalid current |
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119 | |
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120 | reg_PC_ACCESS = reg_PC_CURRENT ; |
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121 | reg_PC_ACCESS_IS_DS_TAKE = reg_PC_CURRENT_IS_DS_TAKE ; |
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122 | reg_PC_ACCESS_INST_IFETCH_PTR = reg_PC_CURRENT_INST_IFETCH_PTR ; |
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123 | reg_PC_ACCESS_BRANCH_STATE = reg_PC_CURRENT_BRANCH_STATE ; |
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124 | reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID; |
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125 | |
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126 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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127 | reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i]; |
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128 | } |
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129 | |
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130 | // if (not reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL) |
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131 | if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and not reg_PC_CURRENT_VAL) |
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132 | { |
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133 | log_printf(TRACE,Address_management,FUNCTION," * New PC_CURRENT"); |
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134 | |
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135 | reg_PC_CURRENT_VAL = 1; // new PC_CURRENT if PC_NEXT is valid |
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136 | reg_PC_NEXT_VAL = 0; // invalid next |
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137 | |
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138 | reg_PC_CURRENT = reg_PC_NEXT ; |
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139 | reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; |
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140 | reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; |
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141 | reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; |
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142 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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143 | |
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144 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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145 | reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; |
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146 | } |
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147 | |
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148 | // if (not reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL) |
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149 | if (reg_PC_NEXT_NEXT_VAL and not reg_PC_NEXT_VAL) |
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150 | { |
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151 | log_printf(TRACE,Address_management,FUNCTION," * New PC_NEXT"); |
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152 | |
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153 | reg_PC_NEXT_VAL = 1; // new PC_NEXT if PC_NEXT_NEXT is valid |
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154 | reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next |
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155 | |
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156 | reg_PC_NEXT = reg_PC_NEXT_NEXT ; |
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157 | reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE ; |
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158 | // reg_PC_NEXT_INST_IFETCH_PTR = reg_PC_NEXT_NEXT_INST_IFETCH_PTR ; |
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159 | // reg_PC_NEXT_BRANCH_STATE = reg_PC_NEXT_NEXT_BRANCH_STATE ; |
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160 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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161 | |
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162 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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163 | // reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i]; |
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164 | } |
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165 | |
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166 | // ========================================= |
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167 | // ===== EVENT ============================= |
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168 | // ========================================= |
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169 | |
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170 | // Event is after shift register : because, it's to write in pc_next and in not pc_current |
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171 | |
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172 | if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK) |
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173 | { |
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174 | log_printf(TRACE,Address_management,FUNCTION," * EVENT : Transaction"); |
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175 | log_printf(TRACE,Address_management,FUNCTION," * IS_DS_TAKE : %d" ,PORT_READ(in_EVENT_IS_DS_TAKE )); |
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176 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS ),PORT_READ(in_EVENT_ADDRESS )<<2); |
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177 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT ),PORT_READ(in_EVENT_ADDRESS_NEXT )<<2); |
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178 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT_VAL : %d" ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL)); |
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179 | |
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180 | reg_PC_ACCESS_VAL = 0; |
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181 | reg_PC_CURRENT_VAL = 0; |
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182 | reg_PC_NEXT_VAL = 1; |
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183 | reg_PC_NEXT = PORT_READ(in_EVENT_ADDRESS); |
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184 | // Event is never is ds_take : |
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185 | // * branch miss speculation : can't be place a branch in delay slot |
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186 | // * load miss speculation : the load is execute, the event_address is the next address (also the destination of branch) |
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187 | // * exception : goto the first instruction of exception handler (also is not in delay slot). |
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188 | |
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189 | reg_PC_NEXT_IS_DS_TAKE = PORT_READ(in_EVENT_IS_DS_TAKE); |
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190 | // reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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191 | // reg_PC_NEXT_BRANCH_STATE = BRANCH_STATE_NONE; |
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192 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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193 | |
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194 | // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. |
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195 | uint32_t index = reg_PC_NEXT % _param->_nb_instruction; |
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196 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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197 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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198 | reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; |
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199 | |
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200 | reg_PC_NEXT_NEXT_VAL = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL); |
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201 | reg_PC_NEXT_NEXT = PORT_READ(in_EVENT_ADDRESS_NEXT); |
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202 | reg_PC_NEXT_NEXT_IS_DS_TAKE = 0;//?? |
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203 | |
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204 | // Note : is_ds_take = address_next_val |
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205 | // Because, is not ds take, can continue in sequence |
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206 | |
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207 | // #ifdef DEBUG_TEST |
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208 | // if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) |
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209 | // throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); |
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210 | // #endif |
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211 | |
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212 | #ifdef STATISTICS |
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213 | if (usage_is_set(_usage,USE_STATISTICS)) |
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214 | (*_stat_nb_transaction_event) ++; |
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215 | #endif |
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216 | } |
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217 | } |
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218 | |
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219 | #if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE) |
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220 | log_printf(TRACE,Address_management,FUNCTION," * Dump PC"); |
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221 | { |
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222 | std::string instruction_enable; |
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223 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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224 | instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " "; |
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225 | |
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226 | log_printf(TRACE,Address_management,FUNCTION," * Access : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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227 | reg_PC_ACCESS_VAL, |
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228 | reg_PC_ACCESS_IS_DS_TAKE, |
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229 | reg_PC_ACCESS, |
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230 | reg_PC_ACCESS<<2, |
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231 | reg_PC_ACCESS_BRANCH_STATE, |
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232 | reg_PC_ACCESS_INST_IFETCH_PTR, |
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233 | reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID, |
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234 | instruction_enable.c_str() |
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235 | ); |
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236 | } |
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237 | { |
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238 | std::string instruction_enable; |
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239 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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240 | instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " "; |
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241 | |
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242 | log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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243 | reg_PC_CURRENT_VAL, |
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244 | reg_PC_CURRENT_IS_DS_TAKE, |
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245 | reg_PC_CURRENT, |
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246 | reg_PC_CURRENT<<2, |
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247 | reg_PC_CURRENT_BRANCH_STATE, |
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248 | reg_PC_CURRENT_INST_IFETCH_PTR, |
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249 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID, |
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250 | instruction_enable.c_str() |
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251 | ); |
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252 | } |
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253 | { |
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254 | std::string instruction_enable; |
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255 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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256 | instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " "; |
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257 | |
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258 | log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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259 | reg_PC_NEXT_VAL, |
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260 | reg_PC_NEXT_IS_DS_TAKE, |
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261 | reg_PC_NEXT, |
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262 | reg_PC_NEXT<<2, |
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263 | reg_PC_NEXT_BRANCH_STATE, |
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264 | reg_PC_NEXT_INST_IFETCH_PTR, |
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265 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID, |
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266 | instruction_enable.c_str()); |
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267 | } |
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268 | log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)", |
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269 | reg_PC_NEXT_NEXT_VAL, |
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270 | reg_PC_NEXT_NEXT_IS_DS_TAKE, |
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271 | reg_PC_NEXT_NEXT, |
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272 | reg_PC_NEXT_NEXT<<2); |
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273 | #endif |
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274 | |
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275 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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276 | end_cycle (); |
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277 | #endif |
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278 | |
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279 | log_end(Address_management,FUNCTION); |
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280 | }; |
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281 | |
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282 | }; // end namespace address_management |
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283 | }; // end namespace ifetch_unit |
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284 | }; // end namespace front_end |
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285 | }; // end namespace multi_front_end |
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286 | }; // end namespace core |
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287 | |
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288 | }; // end namespace behavioural |
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289 | }; // end namespace morpheo |
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290 | #endif |
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