Changeset 111 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

Timestamp:

Feb 27, 2009, 7:37:40 PM (15 years ago)

Author:

rosiere

Message:

1) Decod_queue : multi implementation (one_fifo, multi_fifo)
2) Issue_queue : multi implementation (in_order, out_of_order)
3) Direction : Add Meta predictor
4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative)
5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction
6) UPT : Fix bug in multi event
7) Prediction_glue : in read_stack case, insert in UPT pc_next
8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

@@ -53 +53 @@
         if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
           {
+            log_printf(TRACE,Address_management,FUNCTION,"  * PREDICT");
+
             bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE;
             if (branch_is_current)
@@ -90 +92 @@
         if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
           {
+
             reg_PC_ACCESS_VAL = 0;
 #ifdef STATISTICS
@@ -102 +105 @@
 #endif
           }
+
+        // =========================================
+        // ===== Shift Register ====================
+        // =========================================
         
         // Shift register
-
-        if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)
-          {
+        if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and reg_PC_CURRENT_VAL and not reg_PC_ACCESS_VAL)
+          {
+            log_printf(TRACE,Address_management,FUNCTION,"  * New PC_ACCESS");
+
             reg_PC_ACCESS_VAL  = 1; // new request
             reg_PC_CURRENT_VAL = 0; // invalid current
@@ -120 +128 @@
           }
         
-        if (not reg_PC_CURRENT_VAL)
-          {
-            bool val = reg_PC_NEXT_VAL;
-            reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid
-            reg_PC_NEXT_VAL    = 0;   // invalid next
-
-            if (val)
-              {
-                reg_PC_CURRENT                             = reg_PC_NEXT                            ;
-                reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
-                reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
-                reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
-                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-                
-                for (uint32_t i=0; i<_param->_nb_instruction; i++)
-                  reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
-              }
-          }
-
-        if (not reg_PC_NEXT_VAL)
-          {
-            bool val = reg_PC_NEXT_NEXT_VAL;
-            reg_PC_NEXT_VAL      = val; // new PC_NEXT if PC_NEXT_NEXT is valid
-            reg_PC_NEXT_NEXT_VAL = 0;   // invalid next_next
-            
-            if (val)
-              {
-                reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
-                reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
-//              reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
-//              reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
-//              reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-             
-//              for (uint32_t i=0; i<_param->_nb_instruction; i++)
-//                reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
-              }
+//      if (not reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL)
+        if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and not reg_PC_CURRENT_VAL)
+          {
+            log_printf(TRACE,Address_management,FUNCTION,"  * New PC_CURRENT");
+
+            reg_PC_CURRENT_VAL = 1; // new PC_CURRENT if PC_NEXT is valid
+            reg_PC_NEXT_VAL    = 0; // invalid next
+
+            reg_PC_CURRENT                             = reg_PC_NEXT                            ;
+            reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
+            reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
+            reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
+            reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+            
+            for (uint32_t i=0; i<_param->_nb_instruction; i++)
+              reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
+          }
+
+//      if (not reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)
+        if (reg_PC_NEXT_NEXT_VAL and not reg_PC_NEXT_VAL)
+          {
+            log_printf(TRACE,Address_management,FUNCTION,"  * New PC_NEXT");
+
+            reg_PC_NEXT_VAL      = 1; // new PC_NEXT if PC_NEXT_NEXT is valid
+            reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next
+            
+            reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
+            reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
+//          reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
+//          reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
+//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+            
+//          for (uint32_t i=0; i<_param->_nb_instruction; i++)
+//            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
           }
 
@@ -161 +167 @@
         // ===== EVENT =============================
         // =========================================
+
+        // Event is after shift register : because, it's to write in pc_next and in not pc_current
+
         if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
           {