1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Address_management_transition.cpp 84 2008-05-13 18:04:50Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace address_management { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Address_management::transition" |
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22 | void Address_management::transition (void) |
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23 | { |
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24 | log_printf(FUNC,Address_management,FUNCTION,"Begin"); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | // nothing is valid |
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29 | reg_PC_CURRENT_VAL = 0; |
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30 | reg_PC_NEXT_VAL = 0; |
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31 | reg_PC_NEXT_NEXT_VAL = 0; |
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32 | } |
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33 | else |
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34 | { |
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35 | // ========================================= |
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36 | // ===== PREDICT =========================== |
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37 | // ========================================= |
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38 | if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) |
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39 | { |
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40 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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41 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); |
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42 | if (_param->_have_port_instruction_ptr) |
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43 | reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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44 | reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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45 | if (_param->_have_port_branch_update_prediction_id) |
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46 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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47 | |
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48 | reg_PC_NEXT_NEXT_VAL = 1; // address is valid |
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49 | reg_PC_NEXT_NEXT = PORT_READ(in_PREDICT_PC_NEXT ); |
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50 | reg_PC_NEXT_NEXT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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51 | |
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52 | #ifdef STATISTICS |
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53 | (*_stat_nb_transaction_predict) ++; |
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54 | #endif |
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55 | } |
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56 | |
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57 | // ========================================= |
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58 | // ===== ADDRESS =========================== |
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59 | // ========================================= |
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60 | // transaction with icache |
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61 | if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL) |
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62 | { |
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63 | #ifdef STATISTICS |
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64 | if (reg_PC_CURRENT_VAL) |
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65 | { |
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66 | (*_stat_nb_transaction_address) ++; |
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67 | |
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68 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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69 | if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true) |
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70 | (*_stat_sum_packet_size) ++; |
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71 | } |
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72 | #endif |
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73 | |
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74 | |
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75 | Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL; |
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76 | |
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77 | // next pc became current pc |
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78 | reg_PC_CURRENT_VAL = pc_next_val; |
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79 | |
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80 | // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next) |
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81 | if (pc_next_val) |
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82 | { |
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83 | reg_PC_CURRENT = reg_PC_NEXT ; |
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84 | reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; |
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85 | reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; |
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86 | reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; |
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87 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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88 | |
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89 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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90 | reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; |
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91 | |
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92 | reg_PC_NEXT_VAL = reg_PC_NEXT_NEXT_VAL ; |
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93 | // if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next) |
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94 | if (reg_PC_NEXT_NEXT_VAL) |
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95 | { |
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96 | reg_PC_NEXT = reg_PC_NEXT_NEXT ; |
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97 | reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE; |
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98 | } |
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99 | |
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100 | // invalid next next pc |
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101 | reg_PC_NEXT_NEXT_VAL = 0; |
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102 | } |
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103 | |
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104 | } |
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105 | |
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106 | |
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107 | // ========================================= |
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108 | // ===== EVENT ============================= |
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109 | // ========================================= |
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110 | if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK) |
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111 | { |
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112 | log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction"); |
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113 | reg_PC_CURRENT_VAL = 0; |
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114 | reg_PC_NEXT_VAL = 1; |
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115 | reg_PC_NEXT = PORT_READ(in_EVENT_ADDRESS); |
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116 | // Event is never is ds_take : |
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117 | // * branch miss speculation : can't be place a branch in delay slot |
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118 | // * load miss speculation : the load is execute, the event_address is the next address (also the destination of branch) |
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119 | // * exception : goto the first instruction of exception handler (also is not in delay slot). |
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120 | reg_PC_NEXT_IS_DS_TAKE = 0; |
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121 | // reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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122 | // reg_PC_NEXT_BRANCH_STATE = BRANCH_STATE_NONE; |
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123 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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124 | |
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125 | // reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. |
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126 | // for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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127 | // reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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128 | |
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129 | reg_PC_NEXT_NEXT_VAL = 0; // cancel all prediction (event is send at the predict unit) |
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130 | |
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131 | #ifdef STATISTICS |
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132 | (*_stat_nb_transaction_event) ++; |
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133 | #endif |
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134 | } |
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135 | } |
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136 | |
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137 | #if DEBUG >= DEBUG_TRACE |
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138 | log_printf(TRACE,Address_management,FUNCTION,"Address_Management : "); |
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139 | log_printf(TRACE,Address_management,FUNCTION,"Current : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT); |
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140 | log_printf(TRACE,Address_management,FUNCTION,"Next : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT); |
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141 | log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT); |
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142 | #endif |
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143 | |
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144 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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145 | end_cycle (); |
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146 | #endif |
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147 | |
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148 | log_printf(FUNC,Address_management,FUNCTION,"End"); |
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149 | }; |
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150 | |
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151 | }; // end namespace address_management |
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152 | }; // end namespace ifetch_unit |
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153 | }; // end namespace front_end |
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154 | }; // end namespace multi_front_end |
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155 | }; // end namespace core |
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156 | |
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157 | }; // end namespace behavioural |
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158 | }; // end namespace morpheo |
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159 | #endif |
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