Ignore:
Timestamp:
May 13, 2008, 8:04:50 PM (16 years ago)
Author:
rosiere
Message:

Change Address_manager :

  • before : pc_previous, pc_current, pc_next
  • now : pc_current, pc_next, pc_next_next.

pc_next is send at the prediction_unit, it return the instruction_enable and pc_next_next

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

    r82 r84  
    2626    if (PORT_READ(in_NRESET) == 0)
    2727      {
    28         reg_PC_PREVIOUS_VAL = 0;
    29         reg_PC_CURRENT_VAL  = 0;
    30         reg_PC_NEXT_VAL     = 0;       
     28        // nothing is valid
     29        reg_PC_CURRENT_VAL   = 0;
     30        reg_PC_NEXT_VAL      = 0;
     31        reg_PC_NEXT_NEXT_VAL = 0;
    3132      }
    3233    else
    3334      {
    3435        // =========================================
     36        // ===== PREDICT ===========================
     37        // =========================================
     38        if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
     39          {
     40            for (uint32_t i=0; i<_param->_nb_instruction; i++)
     41            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
     42            if (_param->_have_port_instruction_ptr)
     43            reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
     44            reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
     45            if (_param->_have_port_branch_update_prediction_id)
     46            reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
     47           
     48            reg_PC_NEXT_NEXT_VAL                    = 1; // address is valid
     49            reg_PC_NEXT_NEXT                        = PORT_READ(in_PREDICT_PC_NEXT                    );
     50            reg_PC_NEXT_NEXT_IS_DS_TAKE             = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
     51
     52#ifdef STATISTICS
     53            (*_stat_nb_transaction_predict) ++;
     54#endif
     55          }
     56
     57        // =========================================
    3558        // ===== ADDRESS ===========================
    3659        // =========================================
    3760        // transaction with icache
    38         if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
     61        if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL)
    3962          {
    40             // current pc became previous pc
    41             reg_PC_PREVIOUS_VAL                        = 1;
    42             reg_PC_PREVIOUS                            = reg_PC_CURRENT    ;
    43            
    44             // next    pc became next     pc
    45             reg_PC_CURRENT_VAL                         = reg_PC_NEXT_VAL; // can be not valid
     63#ifdef STATISTICS
     64            if (reg_PC_CURRENT_VAL)
     65              {
     66                (*_stat_nb_transaction_address) ++;
     67
     68                for (uint32_t i=0; i<_param->_nb_instruction; i++)
     69                  if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
     70                    (*_stat_sum_packet_size) ++;
     71              }
     72#endif
     73
     74
     75            Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL;
     76
     77            // next pc became current pc
     78            reg_PC_CURRENT_VAL                             = pc_next_val;
    4679
    4780            // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
    48             if (reg_PC_NEXT_VAL)
     81            if (pc_next_val)
    4982              {
    50             reg_PC_CURRENT                             = reg_PC_NEXT    ;
    51             reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
     83                reg_PC_CURRENT                             = reg_PC_NEXT                            ;
     84                reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
     85                reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
     86                reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
     87                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
     88
     89                for (uint32_t i=0; i<_param->_nb_instruction; i++)
     90                reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
     91           
     92                reg_PC_NEXT_VAL                            = reg_PC_NEXT_NEXT_VAL       ;
     93                // if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
     94                if (reg_PC_NEXT_NEXT_VAL)
     95                  {
     96                    reg_PC_NEXT                            = reg_PC_NEXT_NEXT           ;
     97                    reg_PC_NEXT_IS_DS_TAKE                 = reg_PC_NEXT_NEXT_IS_DS_TAKE;
     98                  }
     99               
     100                // invalid next next pc
     101                reg_PC_NEXT_NEXT_VAL                       = 0;
    52102              }
    53103
    54             reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
    55             reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
    56             reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
    57 
    58             for (uint32_t i=0; i<_param->_nb_instruction; i++)
    59               reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
    60 
    61             // have not next pc
    62             reg_PC_NEXT_VAL                            = 0;
    63104          }
    64105       
    65         // =========================================
    66         // ===== PREDICT ===========================
    67         // =========================================
    68         bool new_pc_current = not reg_PC_CURRENT_VAL;
    69         if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
    70           if (new_pc_current)
    71             {
    72               reg_PC_CURRENT_VAL                         = 1;
    73               reg_PC_CURRENT                             = PORT_READ(in_PREDICT_PC_NEXT                    );
    74               reg_PC_CURRENT_IS_DS_TAKE                  = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
    75               if (_param->_have_port_instruction_ptr)
    76               reg_PC_CURRENT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
    77               reg_PC_CURRENT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
    78               if (_param->_have_port_branch_update_prediction_id)
    79               reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    80 
    81 // #error "INSTRUCTION_ENABLE : ERROR implémentation, remplacer PC_PREVIOUS par PC_NEXT_NEXT"
    82 
    83               for (uint32_t i=0; i<_param->_nb_instruction; i++)
    84                 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
    85             }
    86           else
    87             {
    88               reg_PC_NEXT_VAL                         = 1;
    89               reg_PC_NEXT                             = PORT_READ(in_PREDICT_PC_NEXT                    );
    90               reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
    91               if (_param->_have_port_instruction_ptr)
    92               reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
    93               reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
    94               if (_param->_have_port_branch_update_prediction_id)
    95               reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    96 
    97               for (uint32_t i=0; i<_param->_nb_instruction; i++)
    98                 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
    99             }
    100106
    101107        // =========================================
    … …  
    104110        if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
    105111          {
    106             reg_PC_CURRENT_VAL                         = 1;
    107             reg_PC_CURRENT                             = PORT_READ(in_EVENT_ADDRESS);
     112            log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction");
     113            reg_PC_CURRENT_VAL                      = 0;
     114            reg_PC_NEXT_VAL                         = 1;
     115            reg_PC_NEXT                             = PORT_READ(in_EVENT_ADDRESS);
    108116            // Event is never is ds_take :
    109117            //  * branch miss speculation : can't be place a branch in delay slot
    110118            //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
    111119            //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
    112             reg_PC_CURRENT_IS_DS_TAKE                  = 0;
    113             reg_PC_CURRENT_INST_IFETCH_PTR             = 0;
    114             reg_PC_CURRENT_BRANCH_STATE                = BRANCH_STATE_NONE;
    115             reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = 0;
     120            reg_PC_NEXT_IS_DS_TAKE                  = 0;
     121//          reg_PC_NEXT_INST_IFETCH_PTR             = 0;
     122//          reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
     123//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
    116124           
    117             reg_PC_CURRENT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
    118             for (uint32_t i=1; i<_param->_nb_instruction; i++)
    119               reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = 0;
     125//          reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
     126//          for (uint32_t i=1; i<_param->_nb_instruction; i++)
     127//            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
    120128
    121             reg_PC_NEXT_VAL                            = 0; // cancel all prediction (event is send at the predict unit)
     129            reg_PC_NEXT_NEXT_VAL                    = 0; // cancel all prediction (event is send at the predict unit)
     130
     131#ifdef STATISTICS
     132            (*_stat_nb_transaction_event) ++;
     133#endif
    122134          }
    123135      }
     136
     137#if DEBUG >= DEBUG_TRACE
     138    log_printf(TRACE,Address_management,FUNCTION,"Address_Management : ");
     139    log_printf(TRACE,Address_management,FUNCTION,"Current   : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT);
     140    log_printf(TRACE,Address_management,FUNCTION,"Next      : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT);   
     141    log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT);   
     142#endif
    124143
    125144#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
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