source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone
  • Property svn:keywords set to Id
File size: 6.0 KB
Line 
1/*
2 * $Id: Ifetch_queue_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace ifetch_unit {
17namespace ifetch_queue {
18
19
20
21#undef  FUNCTION
22#define FUNCTION "Ifetch_queue::allocation"
23  void Ifetch_queue::allocation (
24#ifdef STATISTICS
25                               morpheo::behavioural::Parameters_Statistics * param_statistics
26#else
27                               void
28#endif
29                               )
30  {
31    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
32
33    _component   = new Component (_usage);
34
35    Entity * entity = _component->set_entity (_name       
36                                              ,"Ifetch_queue"
37#ifdef POSITION
38                                              ,COMBINATORY
39#endif
40                                              );
41
42    _interfaces = entity->set_interfaces();
43
44    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45    {
46      Interface * interface = _interfaces->set_interface(""
47#ifdef POSITION
48                                                         ,IN
49                                                         ,SOUTH,
50                                                         _("Generalist interface")
51#endif
52                                                         );
53     
54      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
55      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56    }
57
58    // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
59    {
60      ALLOC0_INTERFACE_BEGIN("address", IN, NORTH, "Transaction with PC management.");
61
62      ALLOC0_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
63      ALLOC0_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
64      ALLOC0_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
65      ALLOC0_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
66      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
67      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
68      ALLOC0_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
69
70      ALLOC0_INTERFACE_END();
71    }
72    {
73      ALLOC1_INTERFACE_BEGIN("address", IN, NORTH, _("Transaction with PC management."),_param->_nb_instruction);
74
75      ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t         ,1);
76
77      ALLOC1_INTERFACE_END(_param->_nb_instruction);
78    }
79
80    // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
81    {
82      ALLOC1_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."),_param->_nb_instruction);
83     
84      ALLOC1_VALACK_OUT(out_DECOD_VAL        ,VAL);
85      ALLOC1_VALACK_IN ( in_DECOD_ACK        ,ACK);
86      ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction);
87
88      ALLOC1_INTERFACE_END(_param->_nb_instruction);
89    }
90    {
91      ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));
92     
93      ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
94      ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
95      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
96      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
97      ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
98
99      ALLOC0_INTERFACE_END();
100    }
101
102    // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
103    {
104      ALLOC0_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."));
105     
106      ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
107      ALLOC0_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
108      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
109      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
110
111      ALLOC0_INTERFACE_END();
112    }
113    {
114      ALLOC1_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."),_param->_nb_instruction);
115     
116      ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction);
117
118      ALLOC1_INTERFACE_END(_param->_nb_instruction);
119    }
120
121    // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
122    {
123      ALLOC0_INTERFACE_BEGIN("event_reset", IN, NORTH, _("An event occure and reset queue."));
124
125      ALLOC0_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
126      ALLOC0_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
127
128      ALLOC0_INTERFACE_END();
129    }
130
131    // ~~~~~[ Internal ] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
132    if (usage_is_set(_usage,USE_SYSTEMC))
133      {
134        ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction);
135       
136        _queue = new ifetch_queue_entry_t * [_param->_size_queue];
137        for (uint32_t i=0;i<_param->_size_queue; i++)
138          _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction);
139      }
140
141    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
142
143#ifdef POSITION
144     if (usage_is_set(_usage,USE_POSITION))
145       _component->generate_file();
146#endif
147
148    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
149  };
150
151}; // end namespace ifetch_queue
152}; // end namespace ifetch_unit
153}; // end namespace front_end
154}; // end namespace multi_front_end
155}; // end namespace core
156
157}; // end namespace behavioural
158}; // end namespace morpheo             
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