Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp
- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp
r88 r112 48 48 ,IN 49 49 ,SOUTH, 50 "Generalist interface"50 _("Generalist interface") 51 51 #endif 52 52 ); … … 58 58 // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC _INTERFACE("address", IN, NORTH, "Transaction with PC management.");60 ALLOC0_INTERFACE_BEGIN("address", IN, NORTH, "Transaction with PC management."); 61 61 62 ALLOC _VALACK_IN ( in_ADDRESS_VAL ,VAL);63 ALLOC _VALACK_OUT(out_ADDRESS_ACK ,ACK);64 ALLOC _SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_instruction_address );65 ALLOC _SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);66 ALLOC _SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state );67 ALLOC _SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth );68 ALLOC _SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);62 ALLOC0_VALACK_IN ( in_ADDRESS_VAL ,VAL); 63 ALLOC0_VALACK_OUT(out_ADDRESS_ACK ,ACK); 64 ALLOC0_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_instruction_address ); 65 ALLOC0_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); 66 ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); 67 ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); 68 ALLOC0_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr); 69 69 70 ALLOC0_INTERFACE_END(); 70 71 } 71 72 { 72 ALLOC1_INTERFACE ("address", IN, NORTH, "Transaction with PC management.",_param->_nb_instruction);73 ALLOC1_INTERFACE_BEGIN("address", IN, NORTH, _("Transaction with PC management."),_param->_nb_instruction); 73 74 74 75 ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); 76 77 ALLOC1_INTERFACE_END(_param->_nb_instruction); 75 78 } 76 79 77 80 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 78 81 { 79 ALLOC1_INTERFACE ("decod",OUT, EAST, "Send instruction bundle to the decod's stage.",_param->_nb_instruction);82 ALLOC1_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."),_param->_nb_instruction); 80 83 81 84 ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); 82 85 ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); 83 86 ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction); 87 88 ALLOC1_INTERFACE_END(_param->_nb_instruction); 84 89 } 85 90 { 86 ALLOC _INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.");91 ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage.")); 87 92 88 ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); 89 ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); 90 ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); 91 ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); 92 ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 93 ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); 94 ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); 95 ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); 96 ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); 97 ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 98 99 ALLOC0_INTERFACE_END(); 93 100 } 94 101 95 102 // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 96 103 { 97 ALLOC _INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.");104 ALLOC0_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache.")); 98 105 99 ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); 100 ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); 101 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr); 102 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t,_param->_size_icache_error); 106 ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); 107 ALLOC0_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); 108 ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr); 109 ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t,_param->_size_icache_error); 110 111 ALLOC0_INTERFACE_END(); 103 112 } 104 113 { 105 ALLOC1_INTERFACE ("icache_rsp", IN, WEST, "Respons from Instruction Cache.",_param->_nb_instruction);114 ALLOC1_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."),_param->_nb_instruction); 106 115 107 116 ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction); 117 118 ALLOC1_INTERFACE_END(_param->_nb_instruction); 108 119 } 109 120 110 121 // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 111 122 { 112 ALLOC _INTERFACE("event_reset", IN, NORTH, "An event occure and reset queue.");123 ALLOC0_INTERFACE_BEGIN("event_reset", IN, NORTH, _("An event occure and reset queue.")); 113 124 114 ALLOC_VALACK_IN ( in_EVENT_RESET_VAL,VAL); 115 ALLOC_VALACK_OUT(out_EVENT_RESET_ACK,ACK); 125 ALLOC0_VALACK_IN ( in_EVENT_RESET_VAL,VAL); 126 ALLOC0_VALACK_OUT(out_EVENT_RESET_ACK,ACK); 127 128 ALLOC0_INTERFACE_END(); 116 129 } 117 130 … … 119 132 if (usage_is_set(_usage,USE_SYSTEMC)) 120 133 { 121 internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];134 ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction); 122 135 123 136 _queue = new ifetch_queue_entry_t * [_param->_size_queue];
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