1 | /* |
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2 | * $Id: Ifetch_queue_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
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9 | #include "Behavioural/include/Allocation.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace ifetch_queue { |
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18 | |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Ifetch_queue::allocation" |
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23 | void Ifetch_queue::allocation ( |
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24 | #ifdef STATISTICS |
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25 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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26 | #else |
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27 | void |
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28 | #endif |
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29 | ) |
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30 | { |
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31 | log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); |
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32 | |
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33 | _component = new Component (_usage); |
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34 | |
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35 | Entity * entity = _component->set_entity (_name |
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36 | ,"Ifetch_queue" |
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37 | #ifdef POSITION |
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38 | ,COMBINATORY |
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39 | #endif |
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40 | ); |
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41 | |
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42 | _interfaces = entity->set_interfaces(); |
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43 | |
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44 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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45 | { |
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46 | Interface * interface = _interfaces->set_interface("" |
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47 | #ifdef POSITION |
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48 | ,IN |
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49 | ,SOUTH, |
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50 | "Generalist interface" |
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51 | #endif |
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52 | ); |
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53 | |
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54 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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55 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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56 | } |
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57 | |
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58 | // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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59 | { |
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60 | ALLOC_INTERFACE("address", IN, NORTH, "Transaction with PC management."); |
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61 | |
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62 | ALLOC_VALACK_IN ( in_ADDRESS_VAL ,VAL); |
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63 | ALLOC_VALACK_OUT(out_ADDRESS_ACK ,ACK); |
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64 | ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_instruction_address ); |
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65 | ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); |
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66 | ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); |
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67 | ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); |
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68 | ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr); |
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69 | |
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70 | } |
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71 | { |
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72 | ALLOC1_INTERFACE("address", IN, NORTH, "Transaction with PC management.",_param->_nb_instruction); |
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73 | |
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74 | ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); |
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75 | } |
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76 | |
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77 | // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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78 | { |
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79 | ALLOC1_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.",_param->_nb_instruction); |
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80 | |
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81 | ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); |
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82 | ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); |
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83 | ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction); |
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84 | } |
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85 | { |
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86 | ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage."); |
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87 | |
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88 | ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); |
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89 | ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); |
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90 | ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); |
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91 | ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); |
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92 | ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); |
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93 | } |
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94 | |
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95 | // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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96 | { |
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97 | ALLOC_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache."); |
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98 | |
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99 | ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); |
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100 | ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); |
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101 | ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr); |
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102 | ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t,_param->_size_icache_error); |
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103 | } |
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104 | { |
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105 | ALLOC1_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.",_param->_nb_instruction); |
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106 | |
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107 | ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction); |
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108 | } |
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109 | |
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110 | // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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111 | { |
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112 | ALLOC_INTERFACE("event_reset", IN, NORTH, "An event occure and reset queue."); |
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113 | |
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114 | ALLOC_VALACK_IN ( in_EVENT_RESET_VAL,VAL); |
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115 | ALLOC_VALACK_OUT(out_EVENT_RESET_ACK,ACK); |
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116 | } |
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117 | |
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118 | // ~~~~~[ Internal ] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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119 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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120 | { |
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121 | internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction]; |
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122 | |
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123 | _queue = new ifetch_queue_entry_t * [_param->_size_queue]; |
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124 | for (uint32_t i=0;i<_param->_size_queue; i++) |
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125 | _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction); |
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126 | } |
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127 | |
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128 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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129 | |
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130 | #ifdef POSITION |
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131 | if (usage_is_set(_usage,USE_POSITION)) |
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132 | _component->generate_file(); |
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133 | #endif |
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134 | |
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135 | log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); |
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136 | }; |
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137 | |
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138 | }; // end namespace ifetch_queue |
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139 | }; // end namespace ifetch_unit |
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140 | }; // end namespace front_end |
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141 | }; // end namespace multi_front_end |
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142 | }; // end namespace core |
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143 | |
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144 | }; // end namespace behavioural |
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145 | }; // end namespace morpheo |
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