[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Ifetch_queue_genMoore.cpp 123 2009-06-08 20:43:30Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | namespace ifetch_queue { |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Ifetch_queue::genMoore" |
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| 21 | void Ifetch_queue::genMoore (void) |
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| 22 | { |
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| 23 | log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); |
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| 24 | |
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[123] | 25 | if (PORT_READ(in_NRESET)) |
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| 26 | { |
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[78] | 27 | // ========================================================== |
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| 28 | // =====[ ADDRESS ]========================================== |
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| 29 | // ========================================================== |
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[119] | 30 | { |
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| 31 | internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY); |
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| 32 | |
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| 33 | if (_param->_have_port_ifetch_queue_ptr) |
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| 34 | PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE); |
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| 35 | } |
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[78] | 36 | |
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| 37 | // ========================================================== |
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| 38 | // =====[ DECOD ]============================================ |
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| 39 | // ========================================================== |
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[119] | 40 | { |
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| 41 | bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP); |
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| 42 | |
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| 43 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 44 | { |
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| 45 | internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i]; |
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| 46 | PORT_WRITE(out_DECOD_INSTRUCTION [i], _queue[reg_PTR_READ]->_instruction [i]); |
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| 47 | } |
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| 48 | |
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| 49 | PORT_WRITE(out_DECOD_ADDRESS , _queue[reg_PTR_READ]->_address ); |
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| 50 | if (_param->_have_port_inst_ifetch_ptr) |
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| 51 | PORT_WRITE(out_DECOD_INST_IFETCH_PTR , _queue[reg_PTR_READ]->_inst_ifetch_ptr ); |
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| 52 | PORT_WRITE(out_DECOD_BRANCH_STATE , _queue[reg_PTR_READ]->_branch_state ); |
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| 53 | if (_param->_have_port_depth) |
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| 54 | PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id); |
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| 55 | PORT_WRITE(out_DECOD_EXCEPTION , _queue[reg_PTR_READ]->_exception ); |
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| 56 | } |
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[123] | 57 | } |
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| 58 | else |
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| 59 | { |
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| 60 | // Reset |
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| 61 | internal_ADDRESS_ACK = 0; |
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| 62 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 63 | internal_DECOD_VAL [i] = 0; |
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| 64 | |
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| 65 | } |
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[78] | 66 | |
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[123] | 67 | // Write Output |
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| 68 | PORT_WRITE(out_ADDRESS_ACK , internal_ADDRESS_ACK); |
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| 69 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 70 | PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]); |
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| 71 | |
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[78] | 72 | log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); |
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| 73 | }; |
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| 74 | |
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| 75 | }; // end namespace ifetch_queue |
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| 76 | }; // end namespace ifetch_unit |
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| 77 | }; // end namespace front_end |
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| 78 | }; // end namespace multi_front_end |
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| 79 | }; // end namespace core |
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| 80 | }; // end namespace behavioural |
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| 81 | }; // end namespace morpheo |
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| 82 | #endif |
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