Changeset 119 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp
- Timestamp:
- May 25, 2009, 7:40:26 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp
r88 r119 26 26 // =====[ ADDRESS ]========================================== 27 27 // ========================================================== 28 internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY); 29 30 PORT_WRITE(out_ADDRESS_ACK , internal_ADDRESS_ACK); 31 if (_param->_have_port_ifetch_queue_ptr) 32 PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE); 28 { 29 internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY); 30 31 PORT_WRITE(out_ADDRESS_ACK , internal_ADDRESS_ACK); 32 if (_param->_have_port_ifetch_queue_ptr) 33 PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE); 34 } 33 35 34 36 // ========================================================== 35 37 // =====[ DECOD ]============================================ 36 38 // ========================================================== 37 bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP); 38 39 for (uint32_t i=0; i<_param->_nb_instruction; i++) 40 { 41 internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i]; 42 PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]); 43 PORT_WRITE(out_DECOD_INSTRUCTION [i], _queue[reg_PTR_READ]->_instruction [i]); 44 } 45 46 PORT_WRITE(out_DECOD_ADDRESS , _queue[reg_PTR_READ]->_address ); 47 if (_param->_have_port_inst_ifetch_ptr) 48 PORT_WRITE(out_DECOD_INST_IFETCH_PTR , _queue[reg_PTR_READ]->_inst_ifetch_ptr ); 49 PORT_WRITE(out_DECOD_BRANCH_STATE , _queue[reg_PTR_READ]->_branch_state ); 50 if (_param->_have_port_depth) 51 PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id); 52 PORT_WRITE(out_DECOD_EXCEPTION , _queue[reg_PTR_READ]->_exception ); 39 { 40 bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP); 41 42 for (uint32_t i=0; i<_param->_nb_instruction; i++) 43 { 44 internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i]; 45 PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]); 46 PORT_WRITE(out_DECOD_INSTRUCTION [i], _queue[reg_PTR_READ]->_instruction [i]); 47 } 48 49 PORT_WRITE(out_DECOD_ADDRESS , _queue[reg_PTR_READ]->_address ); 50 if (_param->_have_port_inst_ifetch_ptr) 51 PORT_WRITE(out_DECOD_INST_IFETCH_PTR , _queue[reg_PTR_READ]->_inst_ifetch_ptr ); 52 PORT_WRITE(out_DECOD_BRANCH_STATE , _queue[reg_PTR_READ]->_branch_state ); 53 if (_param->_have_port_depth) 54 PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id); 55 PORT_WRITE(out_DECOD_EXCEPTION , _queue[reg_PTR_READ]->_exception ); 56 } 53 57 54 58 log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
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