[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Ifetch_queue_transition.cpp 101 2009-01-15 17:19:08Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | namespace ifetch_queue { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Ifetch_queue::transition" |
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| 22 | void Ifetch_queue::transition (void) |
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| 23 | { |
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[88] | 24 | log_begin(Ifetch_queue,FUNCTION); |
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[78] | 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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| 28 | reg_PTR_READ = 0; |
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| 29 | reg_PTR_WRITE = 0; |
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| 30 | |
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| 31 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 32 | _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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| 33 | } |
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| 34 | else |
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| 35 | { |
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| 36 | // ========================================================== |
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| 37 | // =====[ ADDRESS ]========================================== |
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| 38 | // ========================================================== |
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| 39 | if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK) |
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| 40 | { |
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| 41 | // New slot in ifetch_queue is allocated |
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| 42 | |
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[101] | 43 | _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; |
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[78] | 44 | |
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| 45 | #ifdef STATISTICS |
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[88] | 46 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 47 | (*_sum_transaction_address) ++; |
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[78] | 48 | #endif |
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| 49 | |
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| 50 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 51 | { |
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| 52 | Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); |
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| 53 | #ifdef STATISTICS |
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[88] | 54 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 55 | (*_sum_inst_enable) += enable; |
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[78] | 56 | #endif |
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| 57 | _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; |
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| 58 | } |
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[85] | 59 | |
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[101] | 60 | _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS); |
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[88] | 61 | _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; |
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[101] | 62 | _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE); |
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[88] | 63 | _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; |
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[78] | 64 | |
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| 65 | reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; |
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| 66 | } |
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| 67 | |
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| 68 | // ========================================================== |
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| 69 | // =====[ DECOD ]============================================ |
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| 70 | // ========================================================== |
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| 71 | bool have_instruction_decod = false; |
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| 72 | bool have_instruction_enable = false; |
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| 73 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 74 | { |
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| 75 | if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) |
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| 76 | { |
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| 77 | have_instruction_decod = true; |
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| 78 | _queue[reg_PTR_READ]->_instruction_enable [i] = false; |
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| 79 | } |
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| 80 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
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| 81 | } |
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| 82 | |
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| 83 | // Test if all is decoded |
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| 84 | if (have_instruction_decod and not have_instruction_enable) |
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| 85 | { |
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| 86 | // all is decod |
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| 87 | _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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| 88 | reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; |
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| 89 | } |
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| 90 | |
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| 91 | // ========================================================== |
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| 92 | // =====[ ICACHE_RSP ]======================================= |
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| 93 | // ========================================================== |
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| 94 | if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) |
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| 95 | { |
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[88] | 96 | Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; |
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[78] | 97 | |
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| 98 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 99 | _queue[ptr]->_instruction [i] = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]); |
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| 100 | |
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| 101 | switch (PORT_READ(in_ICACHE_RSP_ERROR)) |
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| 102 | { |
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| 103 | case ICACHE_ERROR_NONE : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE ; break; |
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| 104 | case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break; |
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| 105 | default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value."); |
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| 106 | } |
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| 107 | |
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| 108 | switch (_queue[ptr]->_state) |
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| 109 | { |
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| 110 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break; |
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| 111 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
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| 112 | default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state."); |
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| 113 | } |
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| 114 | } |
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| 115 | |
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| 116 | // ========================================================== |
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| 117 | // =====[ EVENT_RESET ]====================================== |
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| 118 | // ========================================================== |
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| 119 | if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK) |
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| 120 | { |
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| 121 | // Scan all entry of queue and test the status |
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| 122 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 123 | switch (_queue[i]->_state) |
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| 124 | { |
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| 125 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : break; |
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| 126 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break; |
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| 127 | default : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
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| 128 | } |
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| 129 | |
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| 130 | // all entry is empty (or wait respons to flush) |
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| 131 | // reset ptr |
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| 132 | // 1) reg_PTR_READ = reg_PTR_WRITE = = 0 |
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| 133 | // 2) reg_PTR_READ = reg_PTR_WRITE |
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| 134 | // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2) |
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| 135 | reg_PTR_READ = reg_PTR_WRITE; |
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| 136 | } |
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| 137 | |
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[88] | 138 | #if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) |
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| 139 | log_printf(TRACE,Ifetch_queue,FUNCTION," * Dump ifetch_queue"); |
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| 140 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); |
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| 141 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); |
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[85] | 142 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 143 | { |
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[101] | 144 | log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", |
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| 145 | i, |
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| 146 | _queue [i]->_address, |
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| 147 | _queue [i]->_address<<2, |
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| 148 | _queue [i]->_inst_ifetch_ptr, |
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| 149 | _queue [i]->_branch_state, |
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| 150 | _queue [i]->_branch_update_prediction_id, |
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| 151 | _queue [i]->_exception, |
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| 152 | toString(_queue [i]->_state).c_str() |
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| 153 | ); |
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[85] | 154 | |
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| 155 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
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[101] | 156 | log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); |
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[85] | 157 | } |
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| 158 | #endif |
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[78] | 159 | |
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| 160 | #ifdef STATISTICS |
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[88] | 161 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 162 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 163 | switch (_queue[i]->_state) |
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| 164 | { |
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| 165 | case IFETCH_QUEUE_STATE_EMPTY : break; |
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| 166 | case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; |
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| 167 | case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; |
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| 168 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; |
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| 169 | default : break; |
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| 170 | } |
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[78] | 171 | #endif |
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| 172 | } |
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[88] | 173 | |
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[78] | 174 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 175 | end_cycle (); |
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| 176 | #endif |
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| 177 | |
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[88] | 178 | log_end(Ifetch_queue,FUNCTION); |
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[78] | 179 | }; |
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| 180 | |
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| 181 | }; // end namespace ifetch_queue |
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| 182 | }; // end namespace ifetch_unit |
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| 183 | }; // end namespace front_end |
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| 184 | }; // end namespace multi_front_end |
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| 185 | }; // end namespace core |
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| 186 | |
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| 187 | }; // end namespace behavioural |
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| 188 | }; // end namespace morpheo |
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| 189 | #endif |
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