Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp

Timestamp:

Dec 10, 2008, 7:31:39 PM (16 years ago)

Author:

rosiere

Message:

Almost complete design
with Test and test platform

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp (modified) (7 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp

@@ -22 +22 @@
   void Ifetch_queue::transition (void)
   {
-    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
+    log_begin(Ifetch_queue,FUNCTION);
 
     if (PORT_READ(in_NRESET) == 0)
@@ -34 +34 @@
     else
       {
-        log_printf(NONE,Ifetch_queue,FUNCTION," * KANE address : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
-    
-
         // ==========================================================
         // =====[ ADDRESS ]==========================================
@@ -47 +44 @@
               
 #ifdef STATISTICS
-            (*_sum_transaction_address) ++;
+            if (usage_is_set(_usage,USE_STATISTICS))
+              (*_sum_transaction_address) ++;
 #endif
 
@@ -54 +52 @@
                 Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]);
 #ifdef STATISTICS
-                (*_sum_inst_enable) += enable;
+                if (usage_is_set(_usage,USE_STATISTICS))
+                  (*_sum_inst_enable) += enable;
 #endif
                 _queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
@@ -60 +59 @@
 
             _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS        );
-            _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
+            _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
             _queue[reg_PTR_WRITE]->_branch_state                = PORT_READ(in_ADDRESS_BRANCH_STATE               );
-            _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_branch_update_prediction_id)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
+            _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
             
             reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue;
@@ -95 +94 @@
         if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
           {
-            Tpacket_t ptr = (_param->_have_port_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
+            Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
             
             for (uint32_t i=0; i<_param->_nb_instruction; i++)
@@ -137 +136 @@
           }
 
-#if DEBUG >= DEBUG_TRACE
-        log_printf(TRACE,Ifetch_queue,FUNCTION,"Dump ifetch_queue");
-        log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE);
-        log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ  : %d",reg_PTR_READ );
+#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
+        log_printf(TRACE,Ifetch_queue,FUNCTION,"  * Dump ifetch_queue");
+        log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+        log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_READ  : %d",reg_PTR_READ );
         for (uint32_t i=0; i<_param->_size_queue; i++)
           {
-            log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
             
             for (uint32_t j=0; j<_param->_nb_instruction; j++)
-              log_printf(TRACE,Ifetch_queue,FUNCTION,"    * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
+              log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
           }
 #endif
 
 #ifdef STATISTICS
-        for (uint32_t i=0; i<_param->_size_queue; i++)
-          switch (_queue[i]->_state)
-            {
-            case IFETCH_QUEUE_STATE_EMPTY          : break;
-            case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
-            case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
-            case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
-            default : break;
-            }
+        if (usage_is_set(_usage,USE_STATISTICS))
+          for (uint32_t i=0; i<_param->_size_queue; i++)
+            switch (_queue[i]->_state)
+              {
+              case IFETCH_QUEUE_STATE_EMPTY          : break;
+              case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
+              case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
+              case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
+              default : break;
+              }
 #endif
       }
-
+    
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     end_cycle ();
 #endif
 
-    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
+    log_end(Ifetch_queue,FUNCTION);
   };