[78] | 1 | #ifdef SYSTEMC |
---|
| 2 | /* |
---|
| 3 | * $Id: Ifetch_queue_transition.cpp 119 2009-05-25 17:40:26Z rosiere $ |
---|
| 4 | * |
---|
| 5 | * [ Description ] |
---|
| 6 | * |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
---|
| 10 | |
---|
| 11 | namespace morpheo { |
---|
| 12 | namespace behavioural { |
---|
| 13 | namespace core { |
---|
| 14 | namespace multi_front_end { |
---|
| 15 | namespace front_end { |
---|
| 16 | namespace ifetch_unit { |
---|
| 17 | namespace ifetch_queue { |
---|
| 18 | |
---|
| 19 | |
---|
| 20 | #undef FUNCTION |
---|
| 21 | #define FUNCTION "Ifetch_queue::transition" |
---|
| 22 | void Ifetch_queue::transition (void) |
---|
| 23 | { |
---|
[88] | 24 | log_begin(Ifetch_queue,FUNCTION); |
---|
[119] | 25 | log_function(Ifetch_queue,FUNCTION,_name.c_str()); |
---|
[78] | 26 | |
---|
| 27 | if (PORT_READ(in_NRESET) == 0) |
---|
| 28 | { |
---|
| 29 | reg_PTR_READ = 0; |
---|
| 30 | reg_PTR_WRITE = 0; |
---|
| 31 | |
---|
| 32 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
| 33 | _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; |
---|
| 34 | } |
---|
| 35 | else |
---|
| 36 | { |
---|
| 37 | // ========================================================== |
---|
| 38 | // =====[ ADDRESS ]========================================== |
---|
| 39 | // ========================================================== |
---|
| 40 | if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK) |
---|
| 41 | { |
---|
[119] | 42 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS : Transaction"); |
---|
| 43 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); |
---|
| 44 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS)); |
---|
| 45 | |
---|
[78] | 46 | // New slot in ifetch_queue is allocated |
---|
| 47 | |
---|
[101] | 48 | _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; |
---|
[78] | 49 | |
---|
| 50 | #ifdef STATISTICS |
---|
[88] | 51 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 52 | (*_sum_transaction_address) ++; |
---|
[78] | 53 | #endif |
---|
| 54 | |
---|
| 55 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 56 | { |
---|
| 57 | Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); |
---|
| 58 | #ifdef STATISTICS |
---|
[88] | 59 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 60 | (*_sum_inst_enable) += enable; |
---|
[78] | 61 | #endif |
---|
| 62 | _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; |
---|
| 63 | } |
---|
[85] | 64 | |
---|
[101] | 65 | _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS); |
---|
[88] | 66 | _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; |
---|
[101] | 67 | _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE); |
---|
[88] | 68 | _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; |
---|
[78] | 69 | |
---|
| 70 | reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; |
---|
| 71 | } |
---|
| 72 | |
---|
| 73 | // ========================================================== |
---|
| 74 | // =====[ DECOD ]============================================ |
---|
| 75 | // ========================================================== |
---|
| 76 | bool have_instruction_decod = false; |
---|
| 77 | bool have_instruction_enable = false; |
---|
| 78 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 79 | { |
---|
| 80 | if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) |
---|
| 81 | { |
---|
[119] | 82 | log_printf(TRACE,Ifetch_queue,FUNCTION," * DECOD [%d] : Transaction",i); |
---|
| 83 | |
---|
[78] | 84 | have_instruction_decod = true; |
---|
| 85 | _queue[reg_PTR_READ]->_instruction_enable [i] = false; |
---|
| 86 | } |
---|
| 87 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
---|
| 88 | } |
---|
| 89 | |
---|
| 90 | // Test if all is decoded |
---|
| 91 | if (have_instruction_decod and not have_instruction_enable) |
---|
| 92 | { |
---|
| 93 | // all is decod |
---|
| 94 | _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; |
---|
| 95 | reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; |
---|
| 96 | } |
---|
| 97 | |
---|
| 98 | // ========================================================== |
---|
| 99 | // =====[ ICACHE_RSP ]======================================= |
---|
| 100 | // ========================================================== |
---|
| 101 | if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) |
---|
| 102 | { |
---|
[119] | 103 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ICACHE_RSP : Transaction"); |
---|
| 104 | |
---|
[88] | 105 | Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; |
---|
[78] | 106 | |
---|
| 107 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 108 | _queue[ptr]->_instruction [i] = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]); |
---|
| 109 | |
---|
| 110 | switch (PORT_READ(in_ICACHE_RSP_ERROR)) |
---|
| 111 | { |
---|
| 112 | case ICACHE_ERROR_NONE : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE ; break; |
---|
| 113 | case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break; |
---|
| 114 | default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value."); |
---|
| 115 | } |
---|
| 116 | |
---|
| 117 | switch (_queue[ptr]->_state) |
---|
| 118 | { |
---|
| 119 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break; |
---|
| 120 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
---|
| 121 | default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state."); |
---|
| 122 | } |
---|
| 123 | } |
---|
| 124 | |
---|
| 125 | // ========================================================== |
---|
| 126 | // =====[ EVENT_RESET ]====================================== |
---|
| 127 | // ========================================================== |
---|
| 128 | if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK) |
---|
| 129 | { |
---|
[119] | 130 | log_printf(TRACE,Ifetch_queue,FUNCTION," * EVENT_RESET : Transaction"); |
---|
| 131 | |
---|
[78] | 132 | // Scan all entry of queue and test the status |
---|
| 133 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
| 134 | switch (_queue[i]->_state) |
---|
| 135 | { |
---|
| 136 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : break; |
---|
| 137 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break; |
---|
| 138 | default : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
---|
| 139 | } |
---|
| 140 | |
---|
| 141 | // all entry is empty (or wait respons to flush) |
---|
| 142 | // reset ptr |
---|
| 143 | // 1) reg_PTR_READ = reg_PTR_WRITE = = 0 |
---|
| 144 | // 2) reg_PTR_READ = reg_PTR_WRITE |
---|
| 145 | // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2) |
---|
| 146 | reg_PTR_READ = reg_PTR_WRITE; |
---|
| 147 | } |
---|
| 148 | |
---|
[88] | 149 | #if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) |
---|
| 150 | log_printf(TRACE,Ifetch_queue,FUNCTION," * Dump ifetch_queue"); |
---|
| 151 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); |
---|
| 152 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); |
---|
[85] | 153 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
| 154 | { |
---|
[101] | 155 | log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", |
---|
| 156 | i, |
---|
| 157 | _queue [i]->_address, |
---|
| 158 | _queue [i]->_address<<2, |
---|
| 159 | _queue [i]->_inst_ifetch_ptr, |
---|
| 160 | _queue [i]->_branch_state, |
---|
| 161 | _queue [i]->_branch_update_prediction_id, |
---|
| 162 | _queue [i]->_exception, |
---|
| 163 | toString(_queue [i]->_state).c_str() |
---|
| 164 | ); |
---|
[85] | 165 | |
---|
| 166 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
---|
[101] | 167 | log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); |
---|
[85] | 168 | } |
---|
| 169 | #endif |
---|
[78] | 170 | |
---|
| 171 | #ifdef STATISTICS |
---|
[88] | 172 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 173 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
| 174 | switch (_queue[i]->_state) |
---|
| 175 | { |
---|
| 176 | case IFETCH_QUEUE_STATE_EMPTY : break; |
---|
| 177 | case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; |
---|
| 178 | case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; |
---|
| 179 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; |
---|
| 180 | default : break; |
---|
| 181 | } |
---|
[78] | 182 | #endif |
---|
| 183 | } |
---|
[88] | 184 | |
---|
[78] | 185 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 186 | end_cycle (); |
---|
| 187 | #endif |
---|
| 188 | |
---|
[88] | 189 | log_end(Ifetch_queue,FUNCTION); |
---|
[78] | 190 | }; |
---|
| 191 | |
---|
| 192 | }; // end namespace ifetch_queue |
---|
| 193 | }; // end namespace ifetch_unit |
---|
| 194 | }; // end namespace front_end |
---|
| 195 | }; // end namespace multi_front_end |
---|
| 196 | }; // end namespace core |
---|
| 197 | |
---|
| 198 | }; // end namespace behavioural |
---|
| 199 | }; // end namespace morpheo |
---|
| 200 | #endif |
---|