[78] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: Ifetch_queue_vhdl_body.cpp 135 2009-07-17 08:59:05Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | namespace ifetch_queue { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Ifetch_queue::vhdl_body" |
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| 22 | void Ifetch_queue::vhdl_body (Vhdl * & vhdl) |
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| 23 | { |
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| 24 | log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); |
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[135] | 25 | |
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| 26 | vhdl->set_comment(0,"========================================="); |
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| 27 | vhdl->set_comment(0,"===== CONSTANT =========================="); |
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| 28 | vhdl->set_comment(0,"========================================="); |
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| 29 | vhdl->set_body (0,""); |
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| 30 | vhdl->set_body (0,"internal_ICACHE_RSP_ACK <= '1';"); |
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| 31 | vhdl->set_body (0,"internal_EVENT_RESET_ACK <= '1';"); |
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| 32 | vhdl->set_body (0,"out_EVENT_RESET_ACK <= '1';"); |
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| 33 | vhdl->set_body (0,"out_ICACHE_RSP_ACK <= '1';"); |
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| 34 | vhdl->set_body (0,""); |
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| 35 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 36 | vhdl->set_comment(0,"TRANSLATION "); |
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| 37 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 38 | vhdl->set_body (0,"TRANSITION : process (in_CLOCK)"); |
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| 39 | vhdl->set_body (0,"variable have_instruction_decod : std_logic;"); |
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| 40 | vhdl->set_body (0,"variable have_instruction_enable : std_logic;"); |
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| 41 | // vhdl->set_body (0,"variable reg_INSTRUCTION_ENABLE_VAR : std_logic;"); |
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| 42 | if (_param->_size_queue>1) { |
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| 43 | vhdl->set_body (0,"variable var_PTR_READ :"+ std_logic(log2(_param->_size_queue))+";"); |
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| 44 | vhdl->set_body (0,"variable var_PTR_WRITE :"+ std_logic(log2(_param->_size_queue))+";"); |
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| 45 | } |
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| 46 | // vhdl->set_body (0,"variable var_EMPTY : std_logic;"); |
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| 47 | vhdl->set_body (0,"variable var_STATE : Tstate;"); |
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| 48 | vhdl->set_body (0,"variable var_INSTRUCTION_ENABLE : Tenable;"); |
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| 49 | vhdl->set_body (0,"variable var_ADDRESS : Tadress;"); |
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| 50 | if(_param->_have_port_inst_ifetch_ptr) |
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| 51 | vhdl->set_body (0,"variable var_INST_IFETCH_PTR : Tinst_ptr;"); |
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| 52 | vhdl->set_body (0,"variable var_BRANCH_STATE : Tbranch_state;"); |
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| 53 | if(_param->_have_port_depth) |
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| 54 | vhdl->set_body (0,"variable var_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); |
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| 55 | // vhdl->set_body (0,"variable var_internal_ICACHE_RSP_ACK : std_logic;"); |
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| 56 | if (_param->_have_port_ifetch_queue_ptr) |
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| 57 | vhdl->set_body (0,"variable var_internal_ICACHE_RSP_PACKET_ID : "+std_logic(_param->_size_ifetch_queue_ptr)+";"); |
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| 58 | vhdl->set_body (0,"variable var_EXCEPTION : Texception;"); |
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| 59 | |
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| 60 | |
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| 61 | vhdl->set_body (0,"begin -- TRANSITION"); |
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| 62 | vhdl->set_body (1,"if (in_CLOCK'event and in_CLOCK = '1')then"); |
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| 63 | vhdl->set_body (0,""); |
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| 64 | vhdl->set_comment(2,"---------------------------------------------------------------------------"); |
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| 65 | vhdl->set_comment(2,"Reset"); |
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| 66 | vhdl->set_comment(2,"---------------------------------------------------------------------------"); |
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| 67 | vhdl->set_body (2,"if (in_NRESET = '0') then"); |
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| 68 | if (_param->_size_queue>1) |
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| 69 | { |
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| 70 | vhdl->set_body (3,"reg_PTR_READ <= "+std_logic_cst( log2(_param->_size_queue), 0)+";"); |
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| 71 | vhdl->set_body (3,"reg_PTR_WRITE <= "+std_logic_cst( log2(_param->_size_queue), 0)+";"); |
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| 72 | } |
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| 73 | // vhdl->set_body (3,"var_EMPTY := '1';"); |
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| 74 | |
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| 75 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 76 | { |
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| 77 | vhdl->set_body (3,"reg_STATE("+toString(i)+") <= IFETCH_QUEUE_STATE_EMPTY;"); |
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| 78 | } |
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| 79 | |
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| 80 | vhdl->set_body (3,""); |
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| 81 | vhdl->set_body (2,"else"); |
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| 82 | vhdl->set_body (3,""); |
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| 83 | // std::string write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; |
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| 84 | // vhdl->set_body (3,"var_STATE := reg_STATE ("+write+");"); |
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| 85 | vhdl->set_body (3,"var_STATE := reg_STATE ;"); |
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| 86 | if (_param->_size_queue>1) |
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| 87 | { |
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| 88 | vhdl->set_body (3,"var_PTR_READ := reg_PTR_READ;"); |
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| 89 | vhdl->set_body (3,"var_PTR_WRITE := reg_PTR_WRITE;"); |
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| 90 | } |
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| 91 | |
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| 92 | // if (_param->_size_queue>1) |
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| 93 | // { |
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| 94 | // vhdl->set_body (3,"var_EMPTY := reg_EMPTY ;"); |
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| 95 | // } |
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| 96 | vhdl->set_body (3,"var_INSTRUCTION_ENABLE := reg_INSTRUCTION_ENABLE ;"); |
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| 97 | vhdl->set_body (3,"var_ADDRESS := reg_ADDRESS ;"); |
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| 98 | if(_param->_have_port_inst_ifetch_ptr) |
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| 99 | vhdl->set_body (3,"var_INST_IFETCH_PTR := reg_INST_IFETCH_PTR ;"); |
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| 100 | if (_param->_have_port_ifetch_queue_ptr) |
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| 101 | // vhdl->set_body (3,"var_BRANCH_UPDATE_PREDICTION_ID := reg_BRANCH_UPDATE_PREDICTION_ID;"); |
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| 102 | vhdl->set_body (3,"var_BRANCH_STATE := reg_BRANCH_STATE ;"); |
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| 103 | vhdl->set_body (3,"var_EXCEPTION := reg_EXCEPTION ;"); |
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| 104 | |
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| 105 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 106 | vhdl->set_comment(3,"ADDRESS "); |
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| 107 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 108 | { |
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| 109 | std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; |
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| 110 | vhdl->set_body (3,"if ((in_ADDRESS_VAL and internal_ADDRESS_ACK) = '1') then"); |
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| 111 | vhdl->set_body (3,"var_STATE ("+reg_ptr_write+") := IFETCH_QUEUE_STATE_WAIT_RSP;"); |
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| 112 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 113 | vhdl->set_body (3,"var_INSTRUCTION_ENABLE ("+reg_ptr_write+")("+toString(i)+") := in_address_"+toString(i)+"_instruction_enable;"); |
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| 114 | |
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| 115 | vhdl->set_body (3,"var_ADDRESS("+reg_ptr_write+") := in_ADDRESS_INSTRUCTION_ADDRESS;"); |
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| 116 | if(_param->_have_port_inst_ifetch_ptr) |
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| 117 | { |
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| 118 | vhdl->set_body (3,"var_INST_IFETCH_PTR("+reg_ptr_write+") := in_ADDRESS_INST_IFETCH_PTR;"); |
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| 119 | } |
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| 120 | vhdl->set_body (3,"var_BRANCH_STATE("+reg_ptr_write+") := in_ADDRESS_BRANCH_STATE;"); |
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| 121 | if(_param->_have_port_depth) |
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| 122 | vhdl->set_body (3,"var_BRANCH_UPDATE_PREDICTION_ID := in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;"); |
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| 123 | if (_param->_size_queue>1) |
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| 124 | { |
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| 125 | vhdl->set_body (3,"if (var_PTR_WRITE ="+std_logic_cst( log2(_param->_size_queue),_param->_size_queue-1)+") then"); |
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| 126 | vhdl->set_body (3,"var_PTR_WRITE := "+std_logic_cst( log2(_param->_size_queue), 0)+";"); |
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| 127 | vhdl->set_body (3,"else"); |
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| 128 | if (_param->_size_ifetch_queue_ptr == 1) |
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| 129 | vhdl->set_body (3,"var_PTR_WRITE := not var_PTR_WRITE;"); |
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| 130 | else |
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| 131 | vhdl->set_body (3,"var_PTR_WRITE := (var_PTR_WRITE +"+std_logic_cst( log2(_param->_size_queue),1)+");"); |
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| 132 | vhdl->set_body (3,"end if;"); |
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| 133 | } |
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| 134 | vhdl->set_body (3,"end if;"); |
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| 135 | } |
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| 136 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 137 | vhdl->set_comment(3,"DECOD "); |
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| 138 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 139 | |
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| 140 | // have_instruction_decod <= ((internal_DECOD_0_VAL and in_DECOD_0_ACK) or |
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| 141 | // (internal_DECOD_1_VAL and in_DECOD_1_ACK) or |
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| 142 | // (internal_DECOD_2_VAL and in_DECOD_2_ACK) or |
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| 143 | // (internal_DECOD_3_VAL and in_DECOD_3_ACK)); |
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| 144 | vhdl->set_body (3,"have_instruction_decod := '0';"); |
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| 145 | vhdl->set_body (3,"have_instruction_enable := '0';"); |
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| 146 | std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)"; |
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| 147 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 148 | { |
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| 149 | vhdl->set_body (3,"if ((internal_DECOD_"+toString(i)+"_VAL and in_DECOD_"+toString(i)+"_ACK) = '1') then"); |
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| 150 | vhdl->set_body (4,"have_instruction_decod := '1';"); |
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| 151 | vhdl->set_body (4,"var_INSTRUCTION_ENABLE ("+reg_ptr_read+")("+toString(i)+") := '0';"); |
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| 152 | vhdl->set_body (3,"end if;"); |
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| 153 | vhdl->set_body (4,"have_instruction_enable := have_instruction_enable or var_INSTRUCTION_ENABLE ("+reg_ptr_read+")("+toString(i)+");"); |
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| 154 | } |
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| 155 | vhdl->set_body (3,"if (have_instruction_decod = '1') then"); |
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| 156 | vhdl->set_body (3,"if (have_instruction_enable = '0') then"); |
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| 157 | vhdl->set_body (4,"var_STATE ("+reg_ptr_read+") := IFETCH_QUEUE_STATE_EMPTY;"); |
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| 158 | |
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| 159 | if(_param->_size_queue>1) |
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| 160 | { |
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| 161 | vhdl->set_body (4,"if (var_PTR_READ ="+std_logic_cst( log2(_param->_size_queue),_param->_size_queue-1)+") then"); |
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| 162 | vhdl->set_body (4,"var_PTR_READ := "+std_logic_cst( log2(_param->_size_queue), 0)+"; else"); |
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| 163 | if (_param->_size_ifetch_queue_ptr == 1) |
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| 164 | vhdl->set_body (4,"var_PTR_READ := not var_PTR_READ;"); |
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| 165 | else |
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| 166 | vhdl->set_body (4,"var_PTR_READ := var_PTR_READ +"+std_logic_cst( log2(_param->_size_queue),1)+";"); |
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| 167 | vhdl->set_body (4,"end if;"); |
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| 168 | } |
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| 169 | vhdl->set_body (3,"end if;"); |
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| 170 | vhdl->set_body (3,"end if;"); |
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| 171 | |
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| 172 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 173 | vhdl->set_comment(3,"ICACHE_RSP "); |
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| 174 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 175 | { std::string address; |
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| 176 | if (_param->_have_port_ifetch_queue_ptr) |
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| 177 | { |
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| 178 | address="conv_integer(var_internal_ICACHE_RSP_PACKET_ID)"; |
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| 179 | } |
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| 180 | else |
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| 181 | { |
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| 182 | address="0"; |
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| 183 | } |
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| 184 | vhdl->set_body (3,"if ((in_ICACHE_RSP_VAL and internal_ICACHE_RSP_ACK)= '1') then"); |
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| 185 | if (_param->_have_port_ifetch_queue_ptr) |
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| 186 | { |
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| 187 | vhdl->set_body(4,"var_internal_ICACHE_RSP_PACKET_ID := in_ICACHE_RSP_PACKET_ID;"); |
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| 188 | } |
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| 189 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 190 | vhdl->set_body(3,"reg_DATA("+address+")("+toString(i)+") <= in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION ;"); |
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| 191 | |
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| 192 | vhdl->set_body(4,"if (in_ICACHE_RSP_ERROR = ICACHE_ERROR_NONE) then"); |
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| 193 | vhdl->set_body(5,"var_EXCEPTION("+address+") := EXCEPTION_IFETCH_NONE;"); |
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| 194 | vhdl->set_body(4,"else if (in_ICACHE_RSP_ERROR = ICACHE_ERROR_BUS_ERROR) then"); |
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| 195 | vhdl->set_body(5,"var_EXCEPTION("+address+") := EXCEPTION_IFETCH_BUS_ERROR;"); |
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| 196 | vhdl->set_body (4,"end if;"); |
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| 197 | vhdl->set_body (4,"end if;"); |
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| 198 | vhdl->set_body(4,"if (var_STATE("+address+") = IFETCH_QUEUE_STATE_WAIT_RSP) then"); |
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| 199 | vhdl->set_body(5," var_STATE("+address+") := IFETCH_QUEUE_STATE_HAVE_RSP;"); |
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| 200 | vhdl->set_body(4,"else if var_STATE("+address+") = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP then"); |
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| 201 | vhdl->set_body(5," var_STATE("+address+") := IFETCH_QUEUE_STATE_EMPTY;"); |
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| 202 | vhdl->set_body (4,"end if;"); |
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| 203 | vhdl->set_body (4,"end if;"); |
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| 204 | vhdl->set_body (3,"end if;"); |
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| 205 | } |
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| 206 | |
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| 207 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 208 | vhdl->set_comment(3,"EVENT_RESET"); |
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| 209 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 210 | vhdl->set_body (3,"if ((in_EVENT_RESET_VAL and internal_EVENT_RESET_ACK) = '1' ) then"); |
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| 211 | for (uint32_t i=0; i<_param->_size_queue; i++) { |
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| 212 | vhdl->set_body(4,"if (var_STATE("+toString(i)+") = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP) then "); |
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| 213 | vhdl->set_body(4,"var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_ERROR_WAIT_RSP;"); |
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| 214 | vhdl->set_body(4,"else if var_STATE("+toString(i)+") = IFETCH_QUEUE_STATE_WAIT_RSP then "); |
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| 215 | vhdl->set_body(4,"var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_ERROR_WAIT_RSP;"); |
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| 216 | vhdl->set_body(4,"else var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_EMPTY;"); |
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| 217 | if (_param->_size_queue>1) |
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| 218 | vhdl->set_body(5,"var_PTR_READ := var_PTR_WRITE;"); |
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| 219 | // else |
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| 220 | // vhdl->set_body(5,"reg_EMPTY <= '1';"); |
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| 221 | |
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| 222 | vhdl->set_body(4,"end if;"); |
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| 223 | vhdl->set_body(4,"end if;"); |
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| 224 | } |
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| 225 | //vhdl->set_body (3,"end if;"); |
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| 226 | vhdl->set_body (3,"end if;"); |
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| 227 | |
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| 228 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 229 | vhdl->set_comment(3,"WRITE Register"); |
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| 230 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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| 231 | { |
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| 232 | if (_param->_size_queue>1) { |
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| 233 | vhdl->set_body (3,"reg_PTR_READ <= var_PTR_READ;"); |
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| 234 | vhdl->set_body (3,"reg_PTR_WRITE <= var_PTR_WRITE;"); |
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| 235 | } |
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| 236 | // vhdl->set_body (3,"reg_EMPTY <= var_EMPTY;"); |
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| 237 | std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; |
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| 238 | // vhdl->set_body (3,"reg_STATE ("+reg_ptr_write+") <= var_STATE;"); |
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| 239 | vhdl->set_body (3,"reg_STATE <= var_STATE;"); |
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| 240 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 241 | vhdl->set_body (3,"reg_INSTRUCTION_ENABLE("+reg_ptr_write+")("+toString(i)+") <= var_INSTRUCTION_ENABLE("+reg_ptr_write+")("+toString(i)+");"); |
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| 242 | // vhdl->set_body (3,"reg_ADDRESS ("+reg_ptr_write+") <= var_ADDRESS;"); |
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| 243 | vhdl->set_body (3,"reg_ADDRESS <= var_ADDRESS;"); |
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| 244 | if(_param->_have_port_inst_ifetch_ptr) |
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| 245 | // vhdl->set_body (3,"reg_INST_IFETCH_PTR ("+reg_ptr_write+") <= var_INST_IFETCH_PTR;"); |
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| 246 | vhdl->set_body (3,"reg_INST_IFETCH_PTR <= var_INST_IFETCH_PTR;"); |
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| 247 | // vhdl->set_body (3,"reg_BRANCH_STATE ("+reg_ptr_write+") <= var_BRANCH_STATE;"); |
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| 248 | vhdl->set_body (3,"reg_BRANCH_STATE <= var_BRANCH_STATE;"); |
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| 249 | if(_param->_have_port_depth) |
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| 250 | vhdl->set_body (3,"reg_BRANCH_UPDATE_PREDICTION_ID("+reg_ptr_write+") <= var_BRANCH_UPDATE_PREDICTION_ID;"); |
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| 251 | if (_param->_size_queue>1) |
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| 252 | vhdl->set_body (3,"reg_PTR_WRITE <= var_PTR_WRITE;"); |
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| 253 | |
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| 254 | std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)"; |
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| 255 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 256 | vhdl->set_body (3,"reg_INSTRUCTION_ENABLE("+reg_ptr_read+") ("+toString(i)+") <= var_INSTRUCTION_ENABLE("+reg_ptr_read+")("+toString(i)+");"); |
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| 257 | // vhdl->set_body (3,"reg_STATE("+reg_ptr_read+") <= var_STATE;"); |
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| 258 | if(_param->_size_queue>1) |
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| 259 | vhdl->set_body (3,"reg_PTR_READ <= var_PTR_READ ;"); |
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| 260 | // vhdl->set_body (3,"internal_ICACHE_RSP_ACK <= internal_ICACHE_RSP_ACK;"); |
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| 261 | if (_param->_have_port_ifetch_queue_ptr) |
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| 262 | { |
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| 263 | vhdl->set_body (3,"internal_ICACHE_RSP_PACKET_ID <= var_internal_ICACHE_RSP_PACKET_ID;"); |
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| 264 | std::string address; |
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| 265 | if (_param->_have_port_ifetch_queue_ptr) |
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| 266 | address="conv_integer(var_internal_ICACHE_RSP_PACKET_ID)"; |
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| 267 | else |
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| 268 | address="0"; |
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| 269 | // vhdl->set_body (3,"reg_EXCEPTION("+address+") <= var_EXCEPTION;"); |
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| 270 | vhdl->set_body (3,"reg_EXCEPTION <= var_EXCEPTION;"); |
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| 271 | } |
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| 272 | } |
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| 273 | vhdl->set_body (2,"end if;"); |
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| 274 | vhdl->set_body (1,"end if;"); |
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| 275 | vhdl->set_body (0,"end process; -- TRANSITION"); |
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| 276 | |
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| 277 | |
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| 278 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 279 | vhdl->set_comment(0,"GENMOORE"); |
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| 280 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 281 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 282 | vhdl->set_comment(0,"ADDRESS "); |
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| 283 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 284 | { |
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| 285 | std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; |
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| 286 | vhdl->set_body (1,"internal_ADDRESS_ACK <= '1' WHEN (reg_STATE("+reg_ptr_write+") = IFETCH_QUEUE_STATE_EMPTY) ELSE"); |
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| 287 | vhdl->set_body (1,"'0';"); |
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| 288 | vhdl->set_body (1,"out_ADDRESS_ACK <= internal_ADDRESS_ACK;"); |
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| 289 | if (_param->_have_port_ifetch_queue_ptr) { |
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| 290 | vhdl->set_body (1,"out_ADDRESS_IFETCH_QUEUE_ID <= reg_PTR_WRITE;"); |
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| 291 | } |
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| 292 | } |
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| 293 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 294 | vhdl->set_comment(0,"DECOD "); |
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| 295 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 296 | { |
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| 297 | std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)"; |
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| 298 | vhdl->set_body (0,"internal_ack <= '1' WHEN (reg_STATE("+reg_ptr_read+") = IFETCH_QUEUE_STATE_HAVE_RSP) ELSE"); |
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| 299 | vhdl->set_body (0,"'0';"); |
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| 300 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
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| 301 | { |
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| 302 | vhdl->set_body(0,"internal_DECOD_"+toString(j)+"_VAL <= (internal_ack AND reg_INSTRUCTION_ENABLE("+reg_ptr_read+")("+toString(j)+"));"); |
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| 303 | vhdl->set_body(0,"out_DECOD_"+toString(j)+"_VAL <= internal_DECOD_"+toString(j)+"_VAL;"); |
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| 304 | vhdl->set_body(0,"out_DECOD_"+toString(j)+"_INSTRUCTION <= reg_DATA("+reg_ptr_read+")("+toString(j)+") ;"); |
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| 305 | } |
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| 306 | vhdl->set_body(0,"out_DECOD_ADDRESS <= reg_ADDRESS("+reg_ptr_read+");"); |
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| 307 | if (_param->_have_port_inst_ifetch_ptr) |
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| 308 | vhdl->set_body(0,"out_DECOD_INST_IFETCH_PTR <= reg_INST_IFETCH_PTR("+reg_ptr_read+");"); |
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| 309 | vhdl->set_body(0,"out_DECOD_BRANCH_STATE <= reg_BRANCH_STATE("+reg_ptr_read+");"); |
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| 310 | if (_param->_have_port_depth) |
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| 311 | vhdl->set_body(0,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID <= reg_BRANCH_UPDATE_PREDICTION_ID("+reg_ptr_read+");"); |
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| 312 | vhdl->set_body(0,"out_DECOD_EXCEPTION <= reg_EXCEPTION("+reg_ptr_read+");"); |
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| 313 | } |
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| 314 | vhdl->set_body(0,""); |
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| 315 | |
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[78] | 316 | log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); |
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| 317 | }; |
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| 318 | |
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| 319 | }; // end namespace ifetch_queue |
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| 320 | }; // end namespace ifetch_unit |
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| 321 | }; // end namespace front_end |
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| 322 | }; // end namespace multi_front_end |
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| 323 | }; // end namespace core |
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| 324 | |
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| 325 | }; // end namespace behavioural |
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| 326 | }; // end namespace morpheo |
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| 327 | #endif |
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