[78] | 1 | /* |
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| 2 | * $Id: test.cpp 82 2008-05-01 16:48:45Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[82] | 9 | #define NB_ITERATION 1 |
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| 10 | #define CYCLE_MAX (128*NB_ITERATION) |
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| 11 | |
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[78] | 12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/include/test.h" |
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| 13 | #include "Common/include/Test.h" |
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| 14 | #include "Behavioural/include/Allocation.h" |
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| 15 | |
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| 16 | void test (string name, |
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| 17 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * _param) |
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| 18 | { |
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| 19 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 20 | |
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| 21 | #ifdef STATISTICS |
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| 22 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 23 | #endif |
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| 24 | |
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[82] | 25 | Ifetch_unit * _Ifetch_unit = new Ifetch_unit |
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| 26 | (name.c_str(), |
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[78] | 27 | #ifdef STATISTICS |
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[82] | 28 | _parameters_statistics, |
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[78] | 29 | #endif |
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[82] | 30 | _param, |
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| 31 | USE_ALL); |
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[78] | 32 | |
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| 33 | #ifdef SYSTEMC |
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| 34 | /********************************************************************* |
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| 35 | * Déclarations des signaux |
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| 36 | *********************************************************************/ |
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| 37 | string rename; |
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| 38 | |
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| 39 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 40 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 41 | |
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| 42 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ); |
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| 43 | ALLOC_SC_SIGNAL ( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ); |
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| 44 | //ALLOC_SC_SIGNAL (out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ); |
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| 45 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ); |
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| 46 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t); |
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| 47 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ); |
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| 48 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); |
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| 49 | ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); |
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| 50 | //ALLOC_SC_SIGNAL ( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ); |
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| 51 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); |
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| 52 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); |
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| 53 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); |
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| 54 | ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
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| 55 | ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
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| 56 | ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t ); |
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| 57 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t ); |
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| 58 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
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| 59 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t ); |
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| 60 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
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| 61 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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| 62 | ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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| 63 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
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| 64 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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| 65 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); |
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| 66 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); |
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| 67 | ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); |
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| 68 | //ALLOC_SC_SIGNAL (out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ); |
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| 69 | ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); |
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| 70 | ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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| 71 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); |
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| 72 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); |
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| 73 | ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ); |
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| 74 | ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
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| 75 | ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
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| 76 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t ); |
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| 77 | |
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| 78 | /******************************************************** |
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| 79 | * Instanciation |
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| 80 | ********************************************************/ |
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| 81 | |
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| 82 | msg(_("<%s> : Instanciation of _Ifetch_unit.\n"),name.c_str()); |
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| 83 | |
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| 84 | (*(_Ifetch_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 85 | (*(_Ifetch_unit->in_NRESET)) (*(in_NRESET)); |
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| 86 | |
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| 87 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_VAL ); |
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| 88 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK ); |
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| 89 | //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID ); |
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| 90 | if (_param->_have_port_queue_ptr) |
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| 91 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID ); |
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| 92 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS ); |
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| 93 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_TYPE ); |
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| 94 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_VAL ); |
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| 95 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK ); |
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| 96 | //INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID ); |
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| 97 | if (_param->_have_port_queue_ptr) |
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| 98 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID ); |
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| 99 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); |
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| 100 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_ERROR ); |
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| 101 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_VAL ); |
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| 102 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_ACK ); |
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| 103 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_PREVIOUS ); |
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| 104 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT ); |
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| 105 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
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| 106 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT ); |
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| 107 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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| 108 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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| 109 | if (_param->_have_port_instruction_ptr) |
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| 110 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR ); |
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| 111 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE ); |
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| 112 | if (_param->_have_port_branch_update_prediction_id) |
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| 113 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 114 | INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL ,_param->_nb_instruction); |
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| 115 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_DECOD_ACK ,_param->_nb_instruction); |
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| 116 | INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_INSTRUCTION ,_param->_nb_instruction); |
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| 117 | //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID ); |
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| 118 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS ); |
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| 119 | if (_param->_have_port_instruction_ptr) |
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| 120 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR ); |
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| 121 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE ); |
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| 122 | if (_param->_have_port_branch_update_prediction_id) |
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| 123 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); |
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| 124 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION ); |
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| 125 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_VAL ); |
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| 126 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK ); |
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| 127 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS ); |
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| 128 | |
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| 129 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 130 | |
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| 131 | Time * _time = new Time(); |
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| 132 | |
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| 133 | /******************************************************** |
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| 134 | * Simulation - Begin |
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| 135 | ********************************************************/ |
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| 136 | |
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| 137 | // Initialisation |
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| 138 | |
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| 139 | const uint32_t seed = 0; |
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| 140 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 141 | |
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| 142 | srand(seed); |
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| 143 | |
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| 144 | SC_START(0); |
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| 145 | LABEL("Initialisation"); |
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| 146 | |
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| 147 | LABEL("Reset"); |
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| 148 | in_NRESET->write(0); |
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| 149 | SC_START(5); |
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| 150 | in_NRESET->write(1); |
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| 151 | |
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| 152 | LABEL("Loop of Test"); |
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| 153 | |
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| 154 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 155 | { |
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| 156 | LABEL("Iteration %d",iteration); |
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| 157 | |
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| 158 | SC_START(100); |
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| 159 | } |
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| 160 | |
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| 161 | /******************************************************** |
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| 162 | * Simulation - End |
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| 163 | ********************************************************/ |
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| 164 | |
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| 165 | TEST_OK ("End of Simulation"); |
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| 166 | delete _time; |
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| 167 | |
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| 168 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 169 | |
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| 170 | delete in_CLOCK; |
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| 171 | delete in_NRESET; |
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| 172 | |
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| 173 | delete out_ICACHE_REQ_VAL ; |
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| 174 | delete in_ICACHE_REQ_ACK ; |
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| 175 | //delete out_ICACHE_REQ_THREAD_ID ; |
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| 176 | delete out_ICACHE_REQ_PACKET_ID ; |
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| 177 | delete out_ICACHE_REQ_ADDRESS ; |
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| 178 | delete out_ICACHE_REQ_TYPE ; |
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| 179 | |
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| 180 | delete in_ICACHE_RSP_VAL ; |
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| 181 | delete out_ICACHE_RSP_ACK ; |
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| 182 | //delete in_ICACHE_RSP_THREAD_ID ; |
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| 183 | delete in_ICACHE_RSP_PACKET_ID ; |
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| 184 | delete [] in_ICACHE_RSP_INSTRUCTION ; |
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| 185 | delete in_ICACHE_RSP_ERROR ; |
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| 186 | |
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| 187 | delete out_PREDICT_VAL ; |
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| 188 | delete in_PREDICT_ACK ; |
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| 189 | delete out_PREDICT_PC_PREVIOUS ; |
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| 190 | delete out_PREDICT_PC_CURRENT ; |
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| 191 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
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| 192 | delete in_PREDICT_PC_NEXT ; |
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| 193 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
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| 194 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
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| 195 | delete in_PREDICT_INST_IFETCH_PTR ; |
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| 196 | delete in_PREDICT_BRANCH_STATE ; |
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| 197 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; |
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| 198 | |
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| 199 | delete [] out_DECOD_VAL ; |
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| 200 | delete [] in_DECOD_ACK ; |
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| 201 | delete [] out_DECOD_INSTRUCTION ; |
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| 202 | //delete out_DECOD_CONTEXT_ID ; |
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| 203 | delete out_DECOD_ADDRESS ; |
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| 204 | delete out_DECOD_INST_IFETCH_PTR ; |
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| 205 | delete out_DECOD_BRANCH_STATE ; |
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| 206 | delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; |
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| 207 | delete out_DECOD_EXCEPTION ; |
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| 208 | |
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| 209 | delete in_EVENT_VAL ; |
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| 210 | delete out_EVENT_ACK ; |
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| 211 | delete in_EVENT_ADDRESS ; |
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| 212 | #endif |
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| 213 | |
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| 214 | delete _Ifetch_unit; |
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| 215 | #ifdef STATISTICS |
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| 216 | delete _parameters_statistics; |
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| 217 | #endif |
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| 218 | } |
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