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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp @ 82

Last change on this file since 82 was 82, checked in by rosiere, 16 years ago
support locale (now must "just" translate) update all component with new test format update all component with usage New component : decod queue and prediction_unit
Property svn:keywords set to `Id`
File size: 19.7 KB

Line
1	/*
2	* $Id: Ifetch_unit_allocation.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace ifetch_unit {
17
18
19
20	#undef FUNCTION
21	#define FUNCTION "Ifetch_unit::allocation"
22	void Ifetch_unit::allocation (
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * param_statistics
25	#else
26	void
27	#endif
28	)
29	{
30	log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
31
32	_component = new Component (_usage);
33
34	Entity * entity = _component->set_entity (_name
35	,"Ifetch_unit"
36	#ifdef POSITION
37	,COMBINATORY
38	#endif
39	);
40
41	_interfaces = entity->set_interfaces();
42
43	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
44	{
45	Interface * interface = _interfaces->set_interface(""
46	#ifdef POSITION
47	,IN
48	,SOUTH,
49	"Generalist interface"
50	#endif
51	);
52
53	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
54	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
55	}
56
57	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58	{
59	ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction cache request.");
60
61	ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL);
62	ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK);
63	//ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id );
64	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_queue_ptr );
65	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_address );
66	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type);
67	}
68
69	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
70	{
71	ALLOC_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.");
72
73	ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL);
74	ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK);
75	//ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id );
76	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_queue_ptr );
77	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error);
78	}
79	{
80	ALLOC1_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_instruction);
81
82	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
83	}
84
85	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86	{
87	ALLOC_INTERFACE("predict",OUT, NORTH, "Acces Instruction cache respons.");
88
89	ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL);
90	ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK);
91	ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_address);
92	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_address);
93	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1);
94	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_address);
95	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1);
96	ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
97	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
98	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
99	}
100	{
101	ALLOC1_INTERFACE("predict",IN , NORTH, "Acces Instruction cache respons.",_param->_nb_instruction);
102
103	ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1);
104	}
105
106	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
107	{
108	ALLOC_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.");
109
110	//ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
111	ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_address);
112	ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
113	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
114	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
115	ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);
116	}
117	{
118	ALLOC1_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.",_param->_nb_instruction);
119
120	ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL);
121	ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK);
122	ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction);
123	}
124
125	// ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
126	{
127	ALLOC_INTERFACE("event",IN , NORTH, "Event interface.");
128
129	ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL);
130	ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK);
131	ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address);
132	}
133
134	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
135	std::string name;
136
137	{
138	name = _name+"_address_management";
139	std::cout << "Create : " << name << std::endl;
140
141	_component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management
142	(name.c_str()
143	#ifdef STATISTICS
144	,param_statistics
145	#endif
146	,_param->_param_address_management
147	,_usage);
148
149	_component->set_component (_component_address_management->_component
150	#ifdef POSITION
151	, 50, 50, 10, 10
152	#endif
153	);
154	}
155
156	{
157	name = _name+"_ifetch_queue";
158	std::cout << "Create : " << name << std::endl;
159
160	_component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue
161	(name.c_str()
162	#ifdef STATISTICS
163	,param_statistics
164	#endif
165	,_param->_param_ifetch_queue
166	,_usage);
167
168	_component->set_component (_component_ifetch_queue->_component
169	#ifdef POSITION
170	, 50, 50, 10, 10
171	#endif
172	);
173	}
174
175	{
176	name = _name+"_ifetch_unit_glue";
177	std::cout << "Create : " << name << std::endl;
178
179	_component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue
180	(name.c_str()
181	#ifdef STATISTICS
182	,param_statistics
183	#endif
184	,_param->_param_ifetch_unit_glue
185	,_usage);
186
187	_component->set_component (_component_ifetch_unit_glue->_component
188	#ifdef POSITION
189	, 50, 50, 10, 10
190	#endif
191	);
192	}
193
194	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
195	std::string src,dest;
196
197	// ===================================================================
198	// =====[ address_management ]========================================
199	// ===================================================================
200	{
201	src = _name+"_address_management";
202	std::cout << "Instance : " << src << std::endl;
203
204	{
205	dest = _name;
206	#ifdef POSITION
207	_component->interface_map (src ,"",
208	dest,"");
209	#endif
210	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
211	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
212	}
213
214	{
215	dest = _name;
216
217	#ifdef POSITION
218	_component->interface_map (src ,"address",
219	dest,"icache_req");
220	_component->interface_map (src ,"address",
221	dest+"_ifetch_unit_glue","address");
222	#endif
223
224	for (uint32_t i=0; i<_param->_nb_instruction; i++)
225	{
226	#ifdef POSITION
227	_component->interface_map (src ,"address_"+toString(i),
228	dest+"_ifetch_queue","address_"+toString(i));
229	#endif
230	PORT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
231	dest+"_ifetch_queue", "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
232	}
233
234	PORT_MAP(_component,src ,"out_ADDRESS_VAL" ,
235	dest+"_ifetch_unit_glue", "in_ICACHE_REQ_ADDRESS_VAL" );
236	PORT_MAP(_component,src , "in_ADDRESS_ACK" ,
237	dest+"_ifetch_unit_glue","out_ICACHE_REQ_ADDRESS_ACK" );
238	PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS" ,
239	dest,"out_ICACHE_REQ_ADDRESS");
240	PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS" ,
241	dest+"_ifetch_queue", "in_ADDRESS_INSTRUCTION_ADDRESS" );
242	if (_param->_have_port_instruction_ptr)
243	PORT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" ,
244	dest+"_ifetch_queue", "in_ADDRESS_INST_IFETCH_PTR" );
245	PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" ,
246	dest+"_ifetch_queue", "in_ADDRESS_BRANCH_STATE" );
247	if (_param->_have_port_branch_update_prediction_id)
248	PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
249	dest+"_ifetch_queue", "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
250	}
251
252	{
253	dest = _name;
254
255	#ifdef POSITION
256	_component->interface_map (src ,"predict",
257	dest,"predict");
258	#endif
259
260	for (uint32_t i=0; i<_param->_nb_instruction; i++)
261	{
262	#ifdef POSITION
263	_component->interface_map (src ,"predict_"+toString(i),
264	dest,"predict_"+toString(i));
265	#endif
266	PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE"
267	,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" );
268	}
269
270	PORT_MAP(_component,src ,"out_PREDICT_VAL"
271	,dest,"out_PREDICT_VAL" );
272	PORT_MAP(_component,src , "in_PREDICT_ACK"
273	,dest, "in_PREDICT_ACK" );
274	PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS"
275	,dest,"out_PREDICT_PC_PREVIOUS" );
276	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT"
277	,dest,"out_PREDICT_PC_CURRENT" );
278	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE"
279	,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" );
280	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT"
281	,dest, "in_PREDICT_PC_NEXT" );
282	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE"
283	,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" );
284	if (_param->_have_port_instruction_ptr)
285	PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR"
286	,dest, "in_PREDICT_INST_IFETCH_PTR" );
287	PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE"
288	,dest, "in_PREDICT_BRANCH_STATE" );
289	if (_param->_have_port_branch_update_prediction_id)
290	PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"
291	,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID");
292	}
293
294	{
295	dest = _name+"_ifetch_unit_glue";
296
297	#ifdef POSITION
298	_component->interface_map (src ,"event",
299	dest,"event");
300	_component->interface_map (src ,"event",
301	_name,"event");
302	#endif
303
304	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL");
305	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK");
306	PORT_MAP(_component,src , "in_EVENT_ADDRESS",_name, "in_EVENT_ADDRESS");
307	}
308	}
309
310	// ===================================================================
311	// =====[ ifetch_queue ]==============================================
312	// ===================================================================
313	{
314	src = _name+"_ifetch_queue";
315	std::cout << "Instance : " << src << std::endl;
316
317	{
318	dest = _name;
319	#ifdef POSITION
320	_component->interface_map (src ,"",
321	dest,"");
322	#endif
323	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
324	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
325	}
326
327	{
328	dest = _name;
329
330	#ifdef POSITION
331	_component->interface_map (src ,"address",
332	dest,"address");
333	#endif
334
335	for (uint32_t i=0; i<_param->_nb_instruction; i++)
336	{
337	#ifdef POSITION
338	_component->interface_map (src ,"address_"+toString(i),
339	dest+"_address_management","address_"+toString(i));
340	#endif
341
342	PORT_MAP(_component,src , "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE" ,
343	dest+"_address_management","out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE" );
344	}
345
346	PORT_MAP(_component,src , "in_ADDRESS_VAL" ,
347	dest+"_ifetch_unit_glue" ,"out_ICACHE_REQ_QUEUE_VAL" );
348	PORT_MAP(_component,src ,"out_ADDRESS_ACK" ,
349	dest+"_ifetch_unit_glue" , "in_ICACHE_REQ_QUEUE_ACK" );
350	if (_param->_have_port_queue_ptr)
351	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" ,
352	dest ,"out_ICACHE_REQ_PACKET_ID" );
353	PORT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS" ,
354	dest+"_address_management","out_ADDRESS_INSTRUCTION_ADDRESS" );
355	if (_param->_have_port_instruction_ptr)
356	PORT_MAP(_component,src , "in_ADDRESS_INST_IFETCH_PTR" ,
357	dest+"_address_management","out_ADDRESS_INST_IFETCH_PTR" );
358	PORT_MAP(_component,src , "in_ADDRESS_BRANCH_STATE" ,
359	dest+"_address_management","out_ADDRESS_BRANCH_STATE" );
360	if (_param->_have_port_branch_update_prediction_id)
361	PORT_MAP(_component,src , "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
362	dest+"_address_management","out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
363	}
364
365	{
366	dest = _name;
367
368	#ifdef POSITION
369	_component->interface_map (src ,"icache_rsp",
370	dest,"icache_rsp");
371	#endif
372
373	for (uint32_t i=0; i<_param->_nb_instruction; i++)
374	{
375	#ifdef POSITION
376	_component->interface_map (src ,"icache_rsp_"+toString(i),
377	dest,"icache_rsp_"+toString(i));
378	#endif
379
380	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" ,
381	dest,"out_DECOD_"+toString(i)+"_VAL" );
382	PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" ,
383	dest, "in_DECOD_"+toString(i)+"_ACK" );
384	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" ,
385	dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" );
386	}
387
388	PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" );
389	if (_param->_have_port_instruction_ptr)
390	PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" );
391	PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" );
392	if (_param->_have_port_branch_update_prediction_id)
393	PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");
394	PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" );
395	}
396
397	{
398	dest = _name;
399
400	#ifdef POSITION
401	_component->interface_map (src ,"icache_rsp",
402	dest,"icache_rsp");
403	#endif
404
405	PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" );
406	PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" );
407	if (_param->_have_port_queue_ptr)
408	PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID");
409	PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" );
410
411	for (uint32_t i=0; i<_param->_nb_instruction; i++)
412	{
413	#ifdef POSITION
414	_component->interface_map (src ,"icache_rsp_"+toString(i),
415	dest,"icache_rsp_"+toString(i));
416	#endif
417	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION",
418	dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION");
419	}
420	}
421
422	{
423	dest = _name+"_ifetch_unit_glue";
424
425	#ifdef POSITION
426	_component->interface_map (src ,"event_reset",
427	dest,"event");
428	#endif
429
430	PORT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
431	PORT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
432	}
433	}
434
435	// ===================================================================
436	// =====[ ifetch_unit_glue ]==========================================
437	// ===================================================================
438	{
439	src = _name+"_ifetch_unit_glue";
440	std::cout << "Instance : " << src << std::endl;
441
442	{
443	dest = _name;
444	#ifdef POSITION
445	_component->interface_map (src ,"",
446	dest,"");
447	#endif
448	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
449	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
450	}
451
452	{
453	dest = _name;
454
455	#ifdef POSITION
456	_component->interface_map (src ,"icache_req",
457	dest,"icache_req");
458	#endif
459
460	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest ,"out_ICACHE_REQ_VAL");
461	PORT_MAP(_component,src , "in_ICACHE_REQ_ADDRESS_VAL",dest+"_address_management","out_ADDRESS_VAL");
462	PORT_MAP(_component,src ,"out_ICACHE_REQ_QUEUE_VAL" ,dest+"_ifetch_queue" , "in_ADDRESS_VAL" );
463	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest , "in_ICACHE_REQ_ACK");
464	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS_ACK",dest+"_address_management", "in_ADDRESS_ACK");
465	PORT_MAP(_component,src , "in_ICACHE_REQ_QUEUE_ACK" ,dest+"_ifetch_queue" ,"out_ADDRESS_ACK");
466	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest ,"out_ICACHE_REQ_TYPE");
467	}
468
469	{
470	dest = _name;
471
472	#ifdef POSITION
473	_component->interface_map (src ,"event",
474	dest,"event");
475	#endif
476
477	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" );
478	PORT_MAP(_component,src ,"out_EVENT_ADDRESS_VAL",dest+"_address_management", "in_EVENT_VAL" );
479	PORT_MAP(_component,src ,"out_EVENT_QUEUE_VAL" ,dest+"_ifetch_queue" , "in_EVENT_RESET_VAL" );
480	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" );
481	PORT_MAP(_component,src , "in_EVENT_ADDRESS_ACK",dest+"_address_management","out_EVENT_ACK" );
482	PORT_MAP(_component,src , "in_EVENT_QUEUE_ACK" ,dest+"_ifetch_queue" ,"out_EVENT_RESET_ACK" );
483	}
484	}
485
486	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
487	_component->test_map();
488
489	#ifdef POSITION
490	_component->generate_file();
491	#endif
492
493	log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
494	};
495
496	}; // end namespace ifetch_unit
497	}; // end namespace front_end
498	}; // end namespace multi_front_end
499	}; // end namespace core
500
501	}; // end namespace behavioural
502	}; // end namespace morpheo

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