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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp @ 85

Last change on this file since 85 was 85, checked in by rosiere, 16 years ago
Ifetch_unit : systemC test ok modif shell script and makefile.tools : SHELL=/bin/bash
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1	/*
2	* $Id: Ifetch_unit_allocation.cpp 85 2008-05-14 13:09:48Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace ifetch_unit {
17
18
19
20	#undef FUNCTION
21	#define FUNCTION "Ifetch_unit::allocation"
22	void Ifetch_unit::allocation (
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * param_statistics
25	#else
26	void
27	#endif
28	)
29	{
30	log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
31
32	_component = new Component (_usage);
33
34	Entity * entity = _component->set_entity (_name
35	,"Ifetch_unit"
36	#ifdef POSITION
37	,COMBINATORY
38	#endif
39	);
40
41	_interfaces = entity->set_interfaces();
42
43	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
44	{
45	Interface * interface = _interfaces->set_interface(""
46	#ifdef POSITION
47	,IN
48	,SOUTH,
49	"Generalist interface"
50	#endif
51	);
52
53	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
54	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
55	}
56
57	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58	{
59	ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction cache request.");
60
61	ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL);
62	ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK);
63	//ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id );
64	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_queue_ptr );
65	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_address );
66	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type);
67	}
68
69	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
70	{
71	ALLOC_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.");
72
73	ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL);
74	ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK);
75	//ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id );
76	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_queue_ptr );
77	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error);
78	}
79	{
80	ALLOC1_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_instruction);
81
82	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
83	}
84
85	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86	{
87	ALLOC_INTERFACE("predict",OUT, NORTH, "Acces Instruction cache respons.");
88
89	ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL);
90	ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK);
91	ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_address);
92	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_address);
93	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1);
94	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_address);
95	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1);
96	ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
97	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
98	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
99	}
100	{
101	ALLOC1_INTERFACE("predict",IN , NORTH, "Acces Instruction cache respons.",_param->_nb_instruction);
102
103	ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1);
104	}
105
106	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
107	{
108	ALLOC_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.");
109
110	//ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
111	ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_address);
112	ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
113	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
114	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
115	ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);
116	}
117	{
118	ALLOC1_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.",_param->_nb_instruction);
119
120	ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL);
121	ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK);
122	ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction);
123	}
124
125	// ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
126	{
127	ALLOC_INTERFACE("event",IN , NORTH, "Event interface.");
128
129	ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL);
130	ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK);
131	ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address);
132	}
133
134	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
135	std::string name;
136
137	{
138	name = _name+"_address_management";
139	std::cout << "Create : " << name << std::endl;
140
141	_component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management
142	(name.c_str()
143	#ifdef STATISTICS
144	,param_statistics
145	#endif
146	,_param->_param_address_management
147	,_usage);
148
149	_component->set_component (_component_address_management->_component
150	#ifdef POSITION
151	, 50, 50, 10, 10
152	#endif
153	);
154	}
155
156	{
157	name = _name+"_ifetch_queue";
158	std::cout << "Create : " << name << std::endl;
159
160	_component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue
161	(name.c_str()
162	#ifdef STATISTICS
163	,param_statistics
164	#endif
165	,_param->_param_ifetch_queue
166	,_usage);
167
168	_component->set_component (_component_ifetch_queue->_component
169	#ifdef POSITION
170	, 50, 50, 10, 10
171	#endif
172	);
173	}
174
175	{
176	name = _name+"_ifetch_unit_glue";
177	std::cout << "Create : " << name << std::endl;
178
179	_component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue
180	(name.c_str()
181	#ifdef STATISTICS
182	,param_statistics
183	#endif
184	,_param->_param_ifetch_unit_glue
185	,_usage);
186
187	_component->set_component (_component_ifetch_unit_glue->_component
188	#ifdef POSITION
189	, 50, 50, 10, 10
190	#endif
191	);
192	}
193
194	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
195	std::string src,dest;
196
197	// ===================================================================
198	// =====[ address_management ]========================================
199	// ===================================================================
200	{
201	src = _name+"_address_management";
202	std::cout << "Instance : " << src << std::endl;
203
204	{
205	dest = _name;
206	#ifdef POSITION
207	_component->interface_map (src ,"",
208	dest,"");
209	#endif
210	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
211	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
212	}
213
214	{
215	dest = _name+"_ifetch_queue";
216
217	for (uint32_t i=0; i<_param->_nb_instruction; i++)
218	{
219	#ifdef POSITION
220	_component->interface_map (src ,"address_"+toString(i),
221	dest,"address_"+toString(i));
222	#endif
223	COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
224	dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
225	}
226
227	if (_param->_have_port_instruction_ptr)
228	COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" ,
229	dest, "in_ADDRESS_INST_IFETCH_PTR" );
230	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" ,
231	dest, "in_ADDRESS_BRANCH_STATE" );
232	if (_param->_have_port_branch_update_prediction_id)
233	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
234	dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
235
236	dest = _name+"_ifetch_unit_glue";
237
238	#ifdef POSITION
239	_component->interface_map (src ,"address",
240	dest,"address");
241	#endif
242
243	COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL" ,
244	dest, "in_ICACHE_REQ_ADDRESS_VAL");
245	COMPONENT_MAP(_component,src , "in_ADDRESS_ACK" ,
246	dest,"out_ICACHE_REQ_ADDRESS_ACK");
247	COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS",
248	dest, "in_ICACHE_REQ_ADDRESS_ADDRESS");
249	}
250
251	{
252	dest = _name;
253
254	#ifdef POSITION
255	_component->interface_map (src ,"predict",
256	dest,"predict");
257	#endif
258
259	for (uint32_t i=0; i<_param->_nb_instruction; i++)
260	{
261	#ifdef POSITION
262	_component->interface_map (src ,"predict_"+toString(i),
263	dest,"predict_"+toString(i));
264	#endif
265	PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE"
266	,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" );
267	}
268
269	PORT_MAP(_component,src ,"out_PREDICT_VAL"
270	,dest,"out_PREDICT_VAL" );
271	PORT_MAP(_component,src , "in_PREDICT_ACK"
272	,dest, "in_PREDICT_ACK" );
273	PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS"
274	,dest,"out_PREDICT_PC_PREVIOUS" );
275	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT"
276	,dest,"out_PREDICT_PC_CURRENT" );
277	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE"
278	,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" );
279	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT"
280	,dest, "in_PREDICT_PC_NEXT" );
281	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE"
282	,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" );
283	if (_param->_have_port_instruction_ptr)
284	PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR"
285	,dest, "in_PREDICT_INST_IFETCH_PTR" );
286	PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE"
287	,dest, "in_PREDICT_BRANCH_STATE" );
288	if (_param->_have_port_branch_update_prediction_id)
289	PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"
290	,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID");
291	}
292
293	{
294	dest = _name+"_ifetch_unit_glue";
295
296	#ifdef POSITION
297	_component->interface_map (src ,"event",
298	dest,"event");
299	_component->interface_map (src ,"event",
300	_name,"event");
301	#endif
302
303	COMPONENT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL");
304	COMPONENT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK");
305
306
307	dest = _name;
308	PORT_MAP(_component,src , "in_EVENT_ADDRESS",dest, "in_EVENT_ADDRESS");
309	}
310	}
311
312	// ===================================================================
313	// =====[ ifetch_queue ]==============================================
314	// ===================================================================
315	{
316	src = _name+"_ifetch_queue";
317	std::cout << "Instance : " << src << std::endl;
318
319	{
320	dest = _name;
321	#ifdef POSITION
322	_component->interface_map (src ,"",
323	dest,"");
324	#endif
325	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
326	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
327	}
328
329	{
330	dest = _name;
331
332	#ifdef POSITION
333	_component->interface_map (src ,"address",
334	dest,"address");
335	#endif
336
337	if (_param->_have_port_queue_ptr)
338	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" ,
339	dest,"out_ICACHE_REQ_PACKET_ID" );
340
341	for (uint32_t i=0; i<_param->_nb_instruction; i++)
342	{
343	#ifdef POSITION
344	_component->interface_map (src ,"address_"+toString(i),
345	dest+"_address_management","address_"+toString(i));
346	#endif
347
348	//out_ADDRESS_INSTRUCTION_ENABLE - address_management
349	}
350
351	dest = _name+"_ifetch_unit_glue";
352
353	COMPONENT_MAP(_component,src , "in_ADDRESS_VAL" ,
354	dest,"out_ICACHE_REQ_QUEUE_VAL");
355	COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK" ,
356	dest, "in_ICACHE_REQ_QUEUE_ACK");
357	COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS",
358	dest,"out_ICACHE_REQ_QUEUE_ADDRESS");
359	// in_ADDRESS_INST_IFETCH_PTR - address_management
360	// in_ADDRESS_BRANCH_STATE - address_management
361	// in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management
362	}
363
364	{
365	dest = _name;
366
367	#ifdef POSITION
368	_component->interface_map (src ,"icache_rsp",
369	dest,"icache_rsp");
370	#endif
371
372	for (uint32_t i=0; i<_param->_nb_instruction; i++)
373	{
374	#ifdef POSITION
375	_component->interface_map (src ,"icache_rsp_"+toString(i),
376	dest,"icache_rsp_"+toString(i));
377	#endif
378
379	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" ,
380	dest,"out_DECOD_"+toString(i)+"_VAL" );
381	PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" ,
382	dest, "in_DECOD_"+toString(i)+"_ACK" );
383	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" ,
384	dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" );
385	}
386
387	PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" );
388	if (_param->_have_port_instruction_ptr)
389	PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" );
390	PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" );
391	if (_param->_have_port_branch_update_prediction_id)
392	PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");
393	PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" );
394	}
395
396	{
397	dest = _name;
398
399	#ifdef POSITION
400	_component->interface_map (src ,"icache_rsp",
401	dest,"icache_rsp");
402	#endif
403
404	PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" );
405	PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" );
406	if (_param->_have_port_queue_ptr)
407	PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID");
408	PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" );
409
410	for (uint32_t i=0; i<_param->_nb_instruction; i++)
411	{
412	#ifdef POSITION
413	_component->interface_map (src ,"icache_rsp_"+toString(i),
414	dest,"icache_rsp_"+toString(i));
415	#endif
416	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION",
417	dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION");
418	}
419	}
420
421	{
422	dest = _name+"_ifetch_unit_glue";
423
424	#ifdef POSITION
425	_component->interface_map (src ,"event_reset",
426	dest,"event");
427	#endif
428
429	COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
430	COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
431	}
432	}
433
434	// ===================================================================
435	// =====[ ifetch_unit_glue ]==========================================
436	// ===================================================================
437	{
438	src = _name+"_ifetch_unit_glue";
439	std::cout << "Instance : " << src << std::endl;
440
441	{
442	dest = _name;
443	#ifdef POSITION
444	_component->interface_map (src ,"",
445	dest,"");
446	#endif
447	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
448	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
449	}
450
451	{
452	dest = _name;
453
454	#ifdef POSITION
455	_component->interface_map (src ,"icache_req",
456	dest,"icache_req");
457	#endif
458
459	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_VAL");
460	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_ACK");
461	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_TYPE");
462	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS");
463
464	// in_ICACHE_REQ_ADDRESS_VAL - address_management
465	//out_ICACHE_REQ_QUEUE_VAL - ifetch_queue
466	//out_ICACHE_REQ_ADDRESS_ACK - address_management
467	// in_ICACHE_REQ_QUEUE_ACK - ifetch_queue
468	// in_ICACHE_REQ_ADDRESS_ADDRESS - address_management
469	//out_ICACHE_REQ_QUEUE_ADDRESS - ifetch_queue
470
471	}
472
473	{
474	dest = _name;
475
476	#ifdef POSITION
477	_component->interface_map (src ,"event",
478	dest,"event");
479	#endif
480
481	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" );
482	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" );
483
484	//out_EVENT_ADDRESS_VAL - address_management
485	//out_EVENT_QUEUE_VAL - ifetch_queue
486	// in_EVENT_ADDRESS_ACK - address_management
487	// in_EVENT_QUEUE_ACK - ifetch_queue
488	}
489	}
490
491	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
492	if (DEBUG_Ifetch_unit == true)
493	_component->test_map();
494
495	#ifdef POSITION
496	_component->generate_file();
497	#endif
498
499	log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
500	};
501
502	}; // end namespace ifetch_unit
503	}; // end namespace front_end
504	}; // end namespace multi_front_end
505	}; // end namespace core
506
507	}; // end namespace behavioural
508	}; // end namespace morpheo

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