[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Branch_Target_Buffer_Register_transition.cpp 107 2009-02-10 23:03:25Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace branch_target_buffer { |
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| 18 | namespace branch_target_buffer_register { |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Branch_Target_Buffer_Register::transition" |
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| 22 | void Branch_Target_Buffer_Register::transition (void) |
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| 23 | { |
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[88] | 24 | log_begin(Branch_Target_Buffer_Register,FUNCTION); |
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| 25 | log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); |
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[78] | 26 | |
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| 27 | if (PORT_READ(in_NRESET) == 0) |
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| 28 | { |
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| 29 | for (uint32_t i=0; i<_param->_size_bank; i++) |
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| 30 | for (uint32_t j=0; j<_param->_associativity; j++) |
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| 31 | reg_BTB [i][j]._val = false; |
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| 32 | } |
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| 33 | else |
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| 34 | { |
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[82] | 35 | if (not _param->_have_port_victim) |
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| 36 | { |
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| 37 | genMealy_decod (); |
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| 38 | genMealy_update (); |
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| 39 | } |
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| 40 | |
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[78] | 41 | // ======================================================= |
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| 42 | // =====[ PREDICT ]======================================= |
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| 43 | // ======================================================= |
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| 44 | |
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| 45 | // ======================================================= |
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| 46 | // =====[ DECOD ]========================================= |
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| 47 | // ======================================================= |
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| 48 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 49 | if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
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| 50 | { |
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| 51 | bool hit = internal_DECOD_HIT [i]; |
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| 52 | // uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
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| 53 | // uint32_t num_entry = (hit)?internal_DECOD_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0); |
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| 54 | |
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| 55 | // detect new branch !!! insert in branch target buffer |
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| 56 | if (not hit) |
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| 57 | { |
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| 58 | // =====[ Miss Case ] |
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| 59 | uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
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| 60 | uint32_t num_entry = (_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0; |
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| 61 | |
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| 62 | // dest_val if not jr or jalr |
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| 63 | Tbranch_condition_t cond = PORT_READ(in_DECOD_CONDITION [i]); |
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| 64 | bool dest_val = not ((cond == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or |
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| 65 | (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or |
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| 66 | (cond == BRANCH_CONDITION_READ_STACK )); |
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| 67 | |
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| 68 | reg_BTB[num_bank][num_entry]._val = 1; |
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| 69 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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| 70 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_DECOD_ADDRESS_SRC [i]); |
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| 71 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [i]); |
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| 72 | reg_BTB[num_bank][num_entry]._address_dest_val = dest_val; |
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| 73 | reg_BTB[num_bank][num_entry]._condition = cond; |
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| 74 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_DECOD_LAST_TAKE [i]); |
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[82] | 75 | reg_BTB[num_bank][num_entry]._accurate = (PORT_READ(in_DECOD_IS_ACCURATE [i]))?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; |
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[78] | 76 | } |
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| 77 | // else (hit) : no update -> it's not the last result of the branch |
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| 78 | } |
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| 79 | |
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| 80 | // ======================================================= |
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| 81 | // =====[ UPDATE ]========================================= |
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| 82 | // ======================================================= |
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| 83 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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| 84 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
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| 85 | { |
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[88] | 86 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * UPDATE [%d]",i); |
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| 87 | |
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[78] | 88 | bool hit = internal_UPDATE_HIT [i]; |
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| 89 | uint32_t num_bank = internal_UPDATE_NUM_BANK [i]; |
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| 90 | uint32_t num_entry = (hit)?internal_UPDATE_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM [i]):0); |
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| 91 | bool miss_pred = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); |
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| 92 | |
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| 93 | // detect new branch !!! insert in branch target buffer |
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[107] | 94 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); |
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| 95 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * miss_pred : %d",miss_pred); |
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| 96 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); |
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| 97 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); |
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[88] | 98 | |
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[78] | 99 | Tcounter_t accurate_new = 0; |
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| 100 | |
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| 101 | if (hit) |
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| 102 | { |
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| 103 | // =====[ Hit Case ] |
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| 104 | // * Have destination |
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| 105 | // * if cond == read_register or read_stack : destination valid in commit stage |
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| 106 | // * if cond != read_register or read_stack : destination valid in decod stage |
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| 107 | // * in all case : is valid in this step |
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| 108 | Tcounter_t accurate_old = reg_BTB[num_bank][num_entry]._accurate; |
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[107] | 109 | |
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| 110 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * accurate_old : %d",accurate_old); |
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| 111 | |
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[78] | 112 | // hit : increase accurate |
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| 113 | // miss : decrease accurate |
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[107] | 114 | accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); |
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[78] | 115 | |
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| 116 | // test if accurate go to the threshold |
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| 117 | if ((accurate_old >= _param->_accurate_limit) and |
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| 118 | (accurate_new < _param->_accurate_limit)) |
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[107] | 119 | { |
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| 120 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * decrease downto the accurate_limid (%d)",_param->_accurate_limit); |
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| 121 | accurate_new = 0; |
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| 122 | } |
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[78] | 123 | |
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| 124 | //reg_BTB[num_bank][num_entry]._val : no update because hit |
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| 125 | //reg_BTB[num_bank][num_entry]._context : no update because hit |
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| 126 | //reg_BTB[num_bank][num_entry]._address_src : no update because hit |
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| 127 | //reg_BTB[num_bank][num_entry]._condition : no update because hit |
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| 128 | } |
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| 129 | else |
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| 130 | { |
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| 131 | // =====[ Miss Case ] |
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| 132 | //reg_BTB[num_bank][num_entry]._val = 1; |
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| 133 | //reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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| 134 | //reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
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| 135 | //reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
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| 136 | |
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| 137 | accurate_new = (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; |
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[82] | 138 | |
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[88] | 139 | // reg_BTB[num_bank][num_entry]._val = 1; |
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| 140 | // reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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| 141 | // reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
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| 142 | // reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
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| 143 | // reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
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[107] | 144 | // reg_BTB[num_bank][num_entry]._address_dest_val = 0; |
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[88] | 145 | } |
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[78] | 146 | |
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| 147 | // =====[ All Case ] |
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[88] | 148 | // if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) |
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| 149 | // { |
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| 150 | // reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
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| 151 | // reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
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| 152 | // } |
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[107] | 153 | |
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| 154 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * accurate_new : %d",accurate_new); |
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| 155 | |
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[88] | 156 | reg_BTB[num_bank][num_entry]._val = 1; |
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| 157 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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| 158 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
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| 159 | reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
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| 160 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
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| 161 | reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
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| 162 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
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[78] | 163 | reg_BTB[num_bank][num_entry]._accurate = accurate_new; |
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| 164 | } |
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| 165 | |
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[88] | 166 | #if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register |
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| 167 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * Dump BTB"); |
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[78] | 168 | for (uint32_t i=0; i<_param->_size_bank; i++) |
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| 169 | for (uint32_t j=0; j<_param->_associativity; j++) |
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[88] | 170 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", |
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[78] | 171 | i,j, |
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| 172 | reg_BTB [i][j]._val , |
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| 173 | reg_BTB [i][j]._context , |
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| 174 | reg_BTB [i][j]._address_src , |
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[88] | 175 | reg_BTB [i][j]._address_src <<2, |
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[78] | 176 | reg_BTB [i][j]._address_dest_val, |
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| 177 | reg_BTB [i][j]._address_dest , |
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[88] | 178 | reg_BTB [i][j]._address_dest<<2 , |
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[78] | 179 | reg_BTB [i][j]._condition , |
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| 180 | reg_BTB [i][j]._last_take , |
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| 181 | reg_BTB [i][j]._accurate ); |
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[88] | 182 | #endif |
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[78] | 183 | } |
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[88] | 184 | |
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[78] | 185 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 186 | end_cycle (); |
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| 187 | #endif |
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| 188 | |
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[88] | 189 | log_end(Branch_Target_Buffer_Register,FUNCTION); |
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[78] | 190 | }; |
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| 191 | |
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| 192 | }; // end namespace branch_target_buffer_register |
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| 193 | }; // end namespace branch_target_buffer |
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| 194 | }; // end namespace prediction_unit |
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| 195 | }; // end namespace front_end |
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| 196 | }; // end namespace multi_front_end |
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| 197 | }; // end namespace core |
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| 198 | |
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| 199 | }; // end namespace behavioural |
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| 200 | }; // end namespace morpheo |
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| 201 | #endif |
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