Changeset 107 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp

Timestamp:

Feb 11, 2009, 12:03:25 AM (15 years ago)

Author:

rosiere

Message:

1) Fix test in Direction_Glue for Conditionnal Branch
2) Fix Instruction Address Compute

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp (modified) (4 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp

@@ -92 +92 @@
 
               // detect new branch !!! insert in branch target buffer
-              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * hit       : %d",hit);
-              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_bank  : %d",num_bank );
-              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_entry : %d",num_entry);
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * hit          : %d",hit);
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * miss_pred    : %d",miss_pred);
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_bank     : %d",num_bank );
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_entry    : %d",num_entry);
 
               Tcounter_t accurate_new = 0;
@@ -106 +107 @@
                   //    * in all case : is valid in this step
                   Tcounter_t accurate_old = reg_BTB[num_bank][num_entry]._accurate;
+
+                  log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * accurate_old : %d",accurate_old);
+
                   // hit  : increase accurate
                   // miss : decrease accurate
-                  Tcounter_t accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old);
+                  accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old);
 
                   // test if accurate go to the threshold
                   if ((accurate_old >= _param->_accurate_limit) and
                       (accurate_new <  _param->_accurate_limit))
-                    accurate_new = 0;
+                    {
+                      log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * decrease downto the accurate_limid (%d)",_param->_accurate_limit);
+                      accurate_new = 0;
+                    }
                     
                 //reg_BTB[num_bank][num_entry]._val              : no update because hit
@@ -135 +142 @@
 //                reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
 //                reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
-                  reg_BTB[num_bank][num_entry]._address_dest_val = 0;
+//                reg_BTB[num_bank][num_entry]._address_dest_val = 0;
                 }
 
@@ -144 +151 @@
 //                reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
 //              }
+
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * accurate_new : %d",accurate_new);
+
               reg_BTB[num_bank][num_entry]._val              = 1;
               reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;