[81] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace prediction_unit_glue { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Prediction_unit_Glue::genMealy_predict" |
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| 22 | void Prediction_unit_Glue::genMealy_predict (void) |
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| 23 | { |
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| 24 | log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); |
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| 25 | |
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| 26 | Tcontrol_t ack [_param->_nb_context]; |
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| 27 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 28 | { |
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[82] | 29 | ack [i] = 0; |
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| 30 | |
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| 31 | if (_param->_have_port_depth[i]) |
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| 32 | { |
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| 33 | PORT_WRITE(out_DEPTH_TAIL [i],PORT_READ(in_DEPTH_UPT_TAIL [i])); |
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| 34 | } |
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| 35 | PORT_WRITE(out_DEPTH_NB_BRANCH [i],PORT_READ(in_DEPTH_UPT_NB_BRANCH [i])); |
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| 36 | } |
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| 37 | |
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| 38 | for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) |
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| 39 | { |
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[81] | 40 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"PREDICT [%d]",i); |
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| 41 | |
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| 42 | Tcontrol_t btb_val; |
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| 43 | Tcontrol_t dir_val; |
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| 44 | Tcontrol_t ras_val; |
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| 45 | Tcontrol_t upt_val; |
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| 46 | |
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| 47 | Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; |
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| 48 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); |
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| 49 | |
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| 50 | ack [context] = 1; |
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| 51 | |
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| 52 | if (PORT_READ(in_PREDICT_VAL[context]) == 0) |
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| 53 | { |
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| 54 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); |
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| 55 | |
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| 56 | btb_val = false; |
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| 57 | dir_val = false; |
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| 58 | ras_val = false; |
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| 59 | upt_val = false; |
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| 60 | } |
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| 61 | else |
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| 62 | { |
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| 63 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); |
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| 64 | |
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| 65 | Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); |
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| 66 | Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); |
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| 67 | Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); |
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| 68 | |
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| 69 | Taddress_t pc_next ; |
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| 70 | Tcontrol_t pc_next_is_ds_take ; |
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| 71 | Tbranch_state_t branch_state ; |
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| 72 | Tprediction_ptr_t branch_update_prediction_id ; |
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| 73 | Tinst_ifetch_ptr_t inst_ifetch_ptr ; |
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| 74 | |
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| 75 | // STEP (1) - Compute the address source |
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| 76 | Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; |
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| 77 | Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 |
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| 78 | Taddress_t address_msb; |
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| 79 | |
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| 80 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%x",address); |
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| 81 | |
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| 82 | // STEP (2) - Test if branch (access at branch_target_buffer) |
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| 83 | btb_val = true; |
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| 84 | ack [context] &= PORT_READ(in_PREDICT_BTB_ACK [i]); |
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| 85 | |
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| 86 | if (_param->_have_port_context_id) |
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| 87 | PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); |
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| 88 | PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); |
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| 89 | |
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| 90 | // special case : |
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| 91 | // if pc_current_is_ds, then pc_previous have branch, also hit must be set. |
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| 92 | // else : a another branch have eject this branch : can't accurate |
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| 93 | Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); |
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| 94 | Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); |
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| 95 | |
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| 96 | // STEP (3) : Test if have branch in the packet |
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| 97 | if (hit == 1) |
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| 98 | { |
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| 99 | // STEP (3a) : branch - test condition |
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| 100 | |
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| 101 | bool use_dir = false; |
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| 102 | bool use_ras = false; |
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| 103 | bool use_upt = false; |
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| 104 | |
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| 105 | Tbranch_condition_t cond = PORT_READ(in_PREDICT_BTB_CONDITION [i]); |
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| 106 | Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); |
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| 107 | Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); |
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| 108 | Tcontrol_t push; |
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| 109 | Tcontrol_t direction; |
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| 110 | |
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| 111 | switch (cond) |
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| 112 | { |
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| 113 | case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j |
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| 114 | { |
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| 115 | // use none unit (dir, upt and ras) |
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| 116 | direction = true; |
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| 117 | pc_next = address_dest; |
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| 118 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 119 | break; |
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| 120 | } |
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| 121 | case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal |
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| 122 | { |
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| 123 | use_upt = true; |
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| 124 | use_ras = true; |
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| 125 | push = true; |
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| 126 | direction = true; |
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| 127 | pc_next = address_dest; |
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| 128 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 129 | break; |
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| 130 | } |
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| 131 | case BRANCH_CONDITION_FLAG_UNSET : // l.bnf |
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| 132 | case BRANCH_CONDITION_FLAG_SET : // l.bf |
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| 133 | { |
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| 134 | use_upt = true; |
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| 135 | use_dir = true; |
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| 136 | // Test direction |
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| 137 | direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same |
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| 138 | if (direction = 1) |
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| 139 | { |
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| 140 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 141 | pc_next = address_dest; |
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| 142 | } |
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| 143 | else |
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| 144 | { |
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| 145 | branch_state = BRANCH_STATE_SPEC_NTAKE; |
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[82] | 146 | pc_next = address_src+2; // +1 = delay slot |
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[81] | 147 | } |
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| 148 | break; |
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| 149 | } |
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| 150 | case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) |
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| 151 | { |
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| 152 | use_upt = true; |
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| 153 | use_ras = true; |
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| 154 | push = true; |
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| 155 | direction = true; |
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| 156 | pc_next = address_dest; |
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| 157 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 158 | break; |
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| 159 | } |
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| 160 | case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr |
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| 161 | { |
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| 162 | use_upt = true; |
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| 163 | use_ras = true; |
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| 164 | push = true; |
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| 165 | direction = true; |
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| 166 | pc_next = address_dest; |
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| 167 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 168 | break; |
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| 169 | } |
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| 170 | case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) |
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| 171 | { |
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| 172 | use_upt = true; |
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| 173 | use_ras = true; |
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| 174 | push = false; |
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| 175 | direction = true; |
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| 176 | pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); |
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| 177 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 178 | break; |
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| 179 | } |
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| 180 | default : |
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| 181 | { |
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| 182 | ERRORMORPHEO(FUNCTION,"Unknow Condition"); |
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| 183 | break; |
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| 184 | } |
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| 185 | } |
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| 186 | |
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| 187 | if (use_dir) |
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| 188 | { |
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| 189 | ack[context] &= PORT_READ(in_PREDICT_DIR_ACK [i]); |
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| 190 | PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); |
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| 191 | PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take |
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| 192 | // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); |
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| 193 | } |
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| 194 | |
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| 195 | if (use_ras) |
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| 196 | { |
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| 197 | ack[context] &= PORT_READ(in_PREDICT_RAS_ACK [i]); |
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| 198 | if (_param->_have_port_context_id) |
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| 199 | PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); |
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| 200 | PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); |
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[82] | 201 | PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); |
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[81] | 202 | |
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| 203 | is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate |
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| 204 | } |
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| 205 | |
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| 206 | if (use_upt) |
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| 207 | { |
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| 208 | ack[context] &= PORT_READ(in_PREDICT_UPT_ACK [i]); |
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| 209 | |
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| 210 | PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); |
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| 211 | PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); |
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| 212 | PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); |
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| 213 | PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],cond); |
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| 214 | PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); |
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| 215 | PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); |
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| 216 | // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); |
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| 217 | PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); |
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| 218 | // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); |
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| 219 | } |
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| 220 | |
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| 221 | // ack = 1 if : |
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| 222 | // * btb_ack |
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| 223 | // * use_dir and dir_ack |
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| 224 | // * use_ras and ras_ack |
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| 225 | // * use_upt and upt_ack |
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| 226 | // ack [context] = (PORT_READ(in_PREDICT_BTB_ACK [i]) and |
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| 227 | // (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i])) and |
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| 228 | // (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])) and |
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| 229 | // (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i]))); |
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| 230 | |
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[82] | 231 | dir_val = (use_dir and |
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| 232 | PORT_READ(in_PREDICT_BTB_ACK [i]) and |
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| 233 | (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i]))) and |
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| 234 | (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); |
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[81] | 235 | |
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[82] | 236 | ras_val = (use_ras and |
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| 237 | PORT_READ(in_PREDICT_BTB_ACK [i]) and |
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| 238 | (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and |
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| 239 | (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); |
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[81] | 240 | |
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[82] | 241 | upt_val = (use_upt and |
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| 242 | PORT_READ(in_PREDICT_BTB_ACK [i]) and |
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| 243 | (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and |
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| 244 | (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])))); |
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[81] | 245 | |
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| 246 | // pc_next - is previously computed |
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| 247 | // branch_state - is previously computed |
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| 248 | |
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| 249 | Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; |
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| 250 | |
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[82] | 251 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); |
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| 252 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); |
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[81] | 253 | if (address_src_lsb == (_param->_nb_instruction [context]-1)) |
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| 254 | { |
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| 255 | // branch is in the last slot of the packet |
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[82] | 256 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); |
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| 257 | |
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[81] | 258 | address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) |
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| 259 | pc_next_is_ds_take = 1; |
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| 260 | } |
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| 261 | else |
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| 262 | { |
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| 263 | // branch is in the last slot of the packet |
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| 264 | address_msb = (address_src_lsb+2); // +1 == delayed slot |
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| 265 | pc_next_is_ds_take = 0; |
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| 266 | } |
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[82] | 267 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); |
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[81] | 268 | |
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| 269 | inst_ifetch_ptr = address_src_lsb; |
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[82] | 270 | branch_update_prediction_id = (_param->_have_port_depth[context])?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_size_depth[context]):0; |
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[81] | 271 | } |
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| 272 | else |
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| 273 | { |
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| 274 | // STEP (3b) : Sequential order : compute next paquet |
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| 275 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); |
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| 276 | |
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| 277 | pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial |
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| 278 | pc_next_is_ds_take = 0; // no branch, also no delay slot |
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| 279 | inst_ifetch_ptr = 0; |
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| 280 | branch_state = BRANCH_STATE_NONE; |
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| 281 | branch_update_prediction_id = 0; |
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| 282 | |
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| 283 | address_msb = _param->_nb_instruction [context]; |
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| 284 | } |
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| 285 | |
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| 286 | PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); |
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| 287 | PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); |
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[82] | 288 | |
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| 289 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); |
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| 290 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); |
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| 291 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0",address_lsb); |
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| 292 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_lsb,((pc_current_is_ds_take)?1:address_msb)); |
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| 293 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",((pc_current_is_ds_take)?1:address_msb),_param->_nb_instruction [context]); |
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| 294 | |
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[81] | 295 | for (uint32_t j=0; j<address_lsb; j++) |
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| 296 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid |
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| 297 | for (uint32_t j=address_lsb; j<((pc_current_is_ds_take)?1:address_msb); j++) |
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| 298 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Vald packet |
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| 299 | for (uint32_t j=((pc_current_is_ds_take)?1:address_msb); j<_param->_nb_instruction [context]; j++) |
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| 300 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid |
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| 301 | if (_param->_have_port_inst_ifetch_ptr[context]) |
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| 302 | PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); |
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| 303 | PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); |
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| 304 | if (_param->_have_port_depth[context]) |
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| 305 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , branch_update_prediction_id); |
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| 306 | } |
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| 307 | |
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| 308 | // Write output |
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| 309 | PORT_WRITE(out_PREDICT_BTB_VAL [i], btb_val); |
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| 310 | PORT_WRITE(out_PREDICT_DIR_VAL [i], dir_val); |
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| 311 | PORT_WRITE(out_PREDICT_RAS_VAL [i], ras_val); |
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| 312 | PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); |
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| 313 | } |
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| 314 | |
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| 315 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 316 | PORT_WRITE(out_PREDICT_ACK[i],ack[i]); |
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| 317 | |
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| 318 | log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); |
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| 319 | }; |
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| 320 | |
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| 321 | }; // end namespace prediction_unit_glue |
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| 322 | }; // end namespace prediction_unit |
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| 323 | }; // end namespace front_end |
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| 324 | }; // end namespace multi_front_end |
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| 325 | }; // end namespace core |
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| 326 | |
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| 327 | }; // end namespace behavioural |
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| 328 | }; // end namespace morpheo |
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| 329 | #endif |
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