[81] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace prediction_unit_glue { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Prediction_unit_Glue::genMealy_predict" |
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| 22 | void Prediction_unit_Glue::genMealy_predict (void) |
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| 23 | { |
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[88] | 24 | log_begin(Prediction_unit_Glue,FUNCTION); |
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| 25 | log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); |
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[98] | 26 | |
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| 27 | if (PORT_READ(in_NRESET)) |
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| 28 | { |
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| 29 | |
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| 30 | // Init |
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[81] | 31 | Tcontrol_t ack [_param->_nb_context]; |
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| 32 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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[98] | 33 | ack [i] = 0; |
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[82] | 34 | |
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| 35 | for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) |
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| 36 | { |
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[88] | 37 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); |
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[81] | 38 | |
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[98] | 39 | Tcontrol_t btb_val = false; |
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| 40 | Tcontrol_t dir_val = false; |
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| 41 | Tcontrol_t ras_val = false; |
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| 42 | Tcontrol_t upt_val = false; |
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[81] | 43 | |
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[98] | 44 | Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); |
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| 45 | Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); |
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| 46 | Tcontrol_t ras_ack = PORT_READ(in_PREDICT_RAS_ACK [i]); |
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| 47 | Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); |
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| 48 | |
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| 49 | Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority |
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[88] | 50 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); |
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[81] | 51 | |
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[88] | 52 | ack [context] = 1; |
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[98] | 53 | |
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[88] | 54 | if (PORT_READ(in_PREDICT_VAL[context]) == 0) |
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| 55 | { |
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| 56 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); |
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[81] | 57 | |
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[98] | 58 | // btb_val = false; |
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| 59 | // dir_val = false; |
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| 60 | // ras_val = false; |
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| 61 | // upt_val = false; |
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[88] | 62 | } |
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| 63 | else |
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| 64 | { |
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| 65 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); |
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[81] | 66 | |
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[88] | 67 | Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); |
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| 68 | Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); |
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| 69 | Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); |
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[81] | 70 | |
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[98] | 71 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x",pc_previous ); |
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| 72 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x",pc_current ); |
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| 73 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); |
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| 74 | |
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[88] | 75 | Taddress_t pc_next ; |
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| 76 | Tcontrol_t pc_next_is_ds_take ; |
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| 77 | Tbranch_state_t branch_state ; |
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| 78 | // Tprediction_ptr_t branch_update_prediction_id ; |
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| 79 | Tinst_ifetch_ptr_t inst_ifetch_ptr ; |
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| 80 | |
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| 81 | // STEP (1) - Compute the address source |
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[98] | 82 | // if pc_current is a ds take, then pc_previous is a branchement |
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[88] | 83 | Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; |
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| 84 | Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 |
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| 85 | Taddress_t address_msb; |
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[81] | 86 | |
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[98] | 87 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x",address); |
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| 88 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); |
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[81] | 89 | |
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[88] | 90 | // STEP (2) - Test if branch (access at branch_target_buffer) |
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| 91 | btb_val = true; |
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[81] | 92 | |
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[88] | 93 | if (_param->_have_port_context_id) |
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| 94 | PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); |
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| 95 | PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); |
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[81] | 96 | |
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[98] | 97 | ack [context] &= btb_ack; |
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| 98 | |
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| 99 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); |
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| 100 | |
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| 101 | // BTB_ack = 0 ? |
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| 102 | if (not btb_ack) |
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| 103 | continue; |
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| 104 | |
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[88] | 105 | // special case : |
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| 106 | // if pc_current_is_ds, then pc_previous have branch, also hit must be set. |
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| 107 | // else : a another branch have eject this branch : can't accurate |
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| 108 | Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); |
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| 109 | Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); |
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[81] | 110 | |
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[98] | 111 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit : %d" ,hit); |
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| 112 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); |
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| 113 | |
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[88] | 114 | // STEP (3) : Test if have branch in the packet |
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| 115 | if (hit == 1) |
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| 116 | { |
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| 117 | // STEP (3a) : branch - test condition |
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| 118 | bool use_dir = false; |
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| 119 | bool use_ras = false; |
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| 120 | bool use_upt = false; |
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| 121 | |
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[98] | 122 | Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); |
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[88] | 123 | Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); |
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| 124 | Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); |
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[98] | 125 | Tcontrol_t push ; |
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[88] | 126 | Tcontrol_t direction; |
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[81] | 127 | |
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[98] | 128 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); |
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| 129 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x",address_src); |
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| 130 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x",address_dest); |
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| 131 | |
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| 132 | switch (condition) |
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[88] | 133 | { |
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| 134 | case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j |
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| 135 | { |
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| 136 | // use none unit (dir, upt and ras) |
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| 137 | direction = true; |
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| 138 | pc_next = address_dest; |
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| 139 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 140 | break; |
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| 141 | } |
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| 142 | case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal |
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| 143 | { |
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| 144 | use_upt = true; |
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| 145 | use_ras = true; |
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| 146 | push = true; |
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| 147 | direction = true; |
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| 148 | pc_next = address_dest; |
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| 149 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 150 | break; |
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| 151 | } |
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| 152 | case BRANCH_CONDITION_FLAG_UNSET : // l.bnf |
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| 153 | case BRANCH_CONDITION_FLAG_SET : // l.bf |
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| 154 | { |
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| 155 | use_upt = true; |
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| 156 | use_dir = true; |
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| 157 | // Test direction |
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| 158 | direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same |
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| 159 | if (direction = 1) |
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| 160 | { |
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| 161 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 162 | pc_next = address_dest; |
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| 163 | } |
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| 164 | else |
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| 165 | { |
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| 166 | branch_state = BRANCH_STATE_SPEC_NTAKE; |
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| 167 | pc_next = address_src+2; // +1 = delay slot |
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| 168 | } |
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| 169 | break; |
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| 170 | } |
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| 171 | case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) |
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| 172 | { |
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| 173 | use_upt = true; |
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| 174 | use_ras = true; |
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| 175 | push = true; |
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| 176 | direction = true; |
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| 177 | pc_next = address_dest; |
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| 178 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 179 | break; |
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| 180 | } |
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| 181 | case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr |
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| 182 | { |
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| 183 | use_upt = true; |
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| 184 | use_ras = true; |
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| 185 | push = true; |
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| 186 | direction = true; |
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| 187 | pc_next = address_dest; |
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| 188 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 189 | break; |
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| 190 | } |
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| 191 | case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) |
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| 192 | { |
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| 193 | use_upt = true; |
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| 194 | use_ras = true; |
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| 195 | push = false; |
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| 196 | direction = true; |
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| 197 | pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); |
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| 198 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 199 | break; |
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| 200 | } |
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| 201 | default : |
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| 202 | { |
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| 203 | ERRORMORPHEO(FUNCTION,"Unknow Condition"); |
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| 204 | break; |
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| 205 | } |
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| 206 | } |
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[81] | 207 | |
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[88] | 208 | if (use_dir) |
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| 209 | { |
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[98] | 210 | ack[context] &= dir_ack; |
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[88] | 211 | PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); |
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| 212 | PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take |
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| 213 | // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); |
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| 214 | } |
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[81] | 215 | |
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[88] | 216 | if (use_ras) |
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| 217 | { |
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[98] | 218 | ack[context] &= ras_ack; |
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[88] | 219 | if (_param->_have_port_context_id) |
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| 220 | PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); |
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| 221 | PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); |
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| 222 | PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); |
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[81] | 223 | |
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[88] | 224 | is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate |
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| 225 | } |
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[81] | 226 | |
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[88] | 227 | if (use_upt) |
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| 228 | { |
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[98] | 229 | ack[context] &= upt_ack; |
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[88] | 230 | |
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[98] | 231 | if (_param->_have_port_context_id) |
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[88] | 232 | PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); |
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| 233 | PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); |
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| 234 | PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); |
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[98] | 235 | PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); |
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[88] | 236 | PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); |
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| 237 | PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); |
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| 238 | // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); |
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| 239 | PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); |
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| 240 | // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); |
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| 241 | } |
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[81] | 242 | |
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[88] | 243 | // ack = 1 if : |
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| 244 | // * btb_ack |
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| 245 | // * use_dir and dir_ack |
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| 246 | // * use_ras and ras_ack |
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| 247 | // * use_upt and upt_ack |
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[98] | 248 | // ack [context] = (btb_ack and |
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| 249 | // (use_dir and dir_ack) and |
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| 250 | // (use_ras and ras_ack) and |
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| 251 | // (use_upt and upt_ack)); |
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[81] | 252 | |
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[98] | 253 | dir_val = (btb_ack and |
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| 254 | use_dir and |
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| 255 | // use_ras and |
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| 256 | // use_upt and |
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| 257 | // (not use_dir or (use_dir and dir_ack)) and |
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| 258 | (not use_ras or (use_ras and ras_ack)) and |
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| 259 | (not use_upt or (use_upt and upt_ack))); |
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[81] | 260 | |
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[98] | 261 | ras_val = (btb_ack and |
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| 262 | // use_dir and |
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| 263 | use_ras and |
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| 264 | // use_upt and |
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| 265 | (not use_dir or (use_dir and dir_ack)) and |
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| 266 | // (not use_ras or (use_ras and ras_ack)) and |
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| 267 | (not use_upt or (use_upt and upt_ack))); |
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[81] | 268 | |
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[98] | 269 | upt_val = (btb_ack and |
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| 270 | // use_dir and |
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| 271 | // use_ras and |
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| 272 | use_upt and |
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| 273 | (not use_dir or (use_dir and dir_ack)) and |
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| 274 | (not use_ras or (use_ras and ras_ack))// and |
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| 275 | // (not use_upt or (use_upt and upt_ack)) |
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| 276 | ); |
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[81] | 277 | |
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[88] | 278 | // pc_next - is previously computed |
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| 279 | // branch_state - is previously computed |
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[81] | 280 | |
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[88] | 281 | Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; |
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[81] | 282 | |
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[88] | 283 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); |
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| 284 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); |
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[98] | 285 | |
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[88] | 286 | if (address_src_lsb == (_param->_nb_instruction [context]-1)) |
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| 287 | { |
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| 288 | // branch is in the last slot of the packet |
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| 289 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); |
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| 290 | |
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| 291 | address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) |
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| 292 | pc_next_is_ds_take = 1; |
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| 293 | } |
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| 294 | else |
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| 295 | { |
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| 296 | // branch is in the last slot of the packet |
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| 297 | address_msb = (address_src_lsb+2); // +1 == delayed slot |
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| 298 | pc_next_is_ds_take = 0; |
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| 299 | } |
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| 300 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); |
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[81] | 301 | |
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[88] | 302 | inst_ifetch_ptr = address_src_lsb; |
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| 303 | // branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0; |
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| 304 | } |
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| 305 | else |
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| 306 | { |
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| 307 | // STEP (3b) : Sequential order : compute next paquet |
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| 308 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); |
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[81] | 309 | |
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[88] | 310 | pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial |
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| 311 | pc_next_is_ds_take = 0; // no branch, also no delay slot |
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| 312 | inst_ifetch_ptr = 0; |
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| 313 | branch_state = BRANCH_STATE_NONE; |
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| 314 | // branch_update_prediction_id = 0; |
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[81] | 315 | |
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[88] | 316 | address_msb = _param->_nb_instruction [context]; |
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| 317 | } |
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| 318 | |
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| 319 | PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); |
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| 320 | PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); |
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[82] | 321 | |
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[98] | 322 | Taddress_t address_limit_min = address_lsb; |
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| 323 | Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); |
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| 324 | |
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[88] | 325 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); |
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| 326 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); |
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[98] | 327 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); |
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| 328 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); |
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| 329 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); |
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[82] | 330 | |
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[98] | 331 | for (uint32_t j=0; j<address_limit_min; j++) |
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[88] | 332 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid |
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[98] | 333 | for (uint32_t j=address_limit_min; j<address_limit_max; j++) |
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[88] | 334 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Vald packet |
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[98] | 335 | for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) |
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[88] | 336 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid |
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| 337 | if (_param->_have_port_inst_ifetch_ptr) |
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| 338 | PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); |
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| 339 | PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); |
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| 340 | if (_param->_have_port_depth) |
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| 341 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); |
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| 342 | } |
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[81] | 343 | |
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[88] | 344 | // Write output |
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| 345 | PORT_WRITE(out_PREDICT_BTB_VAL [i], btb_val); |
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| 346 | PORT_WRITE(out_PREDICT_DIR_VAL [i], dir_val); |
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| 347 | PORT_WRITE(out_PREDICT_RAS_VAL [i], ras_val); |
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| 348 | PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); |
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[81] | 349 | } |
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| 350 | |
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| 351 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 352 | PORT_WRITE(out_PREDICT_ACK[i],ack[i]); |
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[98] | 353 | } |
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[81] | 354 | |
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[88] | 355 | log_end(Prediction_unit_Glue,FUNCTION); |
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[81] | 356 | }; |
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| 357 | |
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| 358 | }; // end namespace prediction_unit_glue |
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| 359 | }; // end namespace prediction_unit |
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| 360 | }; // end namespace front_end |
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| 361 | }; // end namespace multi_front_end |
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| 362 | }; // end namespace core |
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| 363 | |
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| 364 | }; // end namespace behavioural |
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| 365 | }; // end namespace morpheo |
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| 366 | #endif |
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