[78] | 1 | #ifdef SYSTEMC |
---|
| 2 | /* |
---|
| 3 | * $Id$ |
---|
| 4 | * |
---|
| 5 | * [ Description ] |
---|
| 6 | * |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h" |
---|
| 10 | |
---|
| 11 | namespace morpheo { |
---|
| 12 | namespace behavioural { |
---|
| 13 | namespace core { |
---|
| 14 | namespace multi_front_end { |
---|
| 15 | namespace front_end { |
---|
| 16 | namespace prediction_unit { |
---|
| 17 | namespace return_address_stack { |
---|
| 18 | |
---|
| 19 | |
---|
| 20 | #undef FUNCTION |
---|
| 21 | #define FUNCTION "Return_Address_Stack::transition" |
---|
| 22 | void Return_Address_Stack::transition (void) |
---|
| 23 | { |
---|
| 24 | log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); |
---|
| 25 | |
---|
| 26 | if (PORT_READ(in_NRESET)) |
---|
| 27 | { |
---|
| 28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 29 | { |
---|
| 30 | reg_TOP [i] = 0; |
---|
| 31 | reg_BOTTOM [i] = 0; |
---|
| 32 | |
---|
| 33 | reg_PREDICT_TOP [i] = 0; |
---|
| 34 | reg_PREDICT_BOTTOM [i] = 0; |
---|
| 35 | |
---|
| 36 | for (uint32_t j=0; j<_param->_size_queue [i]; j++) |
---|
| 37 | reg_stack[i][j]._val = false; |
---|
| 38 | } |
---|
| 39 | } |
---|
| 40 | else |
---|
| 41 | { |
---|
| 42 | // =================================================================== |
---|
| 43 | // =====[ PREDICT ]=================================================== |
---|
| 44 | // =================================================================== |
---|
| 45 | for (uint32_t i=0; i<_param->_nb_inst_predict; i++) |
---|
| 46 | if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) |
---|
| 47 | { |
---|
| 48 | Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; |
---|
| 49 | Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); |
---|
| 50 | Tptr_t top_old = reg_PREDICT_TOP [i]; |
---|
| 51 | Tptr_t top_new; |
---|
| 52 | |
---|
| 53 | if (internal_PREDICT_HIT [i]) |
---|
| 54 | { |
---|
| 55 | if (push) |
---|
| 56 | { |
---|
| 57 | // push |
---|
| 58 | top_new = (top_old+1)%_param->_size_queue[context]; |
---|
| 59 | |
---|
| 60 | reg_stack [context][top_new]._val = true; // New addr |
---|
| 61 | reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr) |
---|
| 62 | //reg_stack [context][top_new]._miss = ; |
---|
| 63 | reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); |
---|
| 64 | |
---|
| 65 | // the stack is full, erase the most old stack |
---|
| 66 | if (top_new == reg_PREDICT_BOTTOM [i]) |
---|
| 67 | reg_PREDICT_BOTTOM [i] = (reg_PREDICT_BOTTOM [i]+1)%_param->_size_queue[context]; |
---|
| 68 | } |
---|
| 69 | else |
---|
| 70 | { |
---|
| 71 | // pop |
---|
| 72 | top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
---|
| 73 | |
---|
| 74 | //reg_stack [context][top_new]._val = ; |
---|
| 75 | //reg_stack [context][top_new]._predict = ; |
---|
| 76 | //reg_stack [context][top_new]._miss = ; |
---|
| 77 | //reg_stack [context][top_new]._address = ; |
---|
| 78 | |
---|
| 79 | // the stack is empty |
---|
| 80 | if (top_old == reg_PREDICT_BOTTOM [i]) |
---|
| 81 | reg_PREDICT_BOTTOM [i] = top_new; |
---|
| 82 | |
---|
| 83 | } |
---|
| 84 | |
---|
| 85 | reg_PREDICT_TOP [i] = top_new; |
---|
| 86 | } |
---|
| 87 | } |
---|
| 88 | |
---|
| 89 | // // =================================================================== |
---|
| 90 | // // =====[ DECOD ]===================================================== |
---|
| 91 | // // =================================================================== |
---|
| 92 | // for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
---|
| 93 | // if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
---|
| 94 | // { |
---|
| 95 | // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
---|
| 96 | // Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); |
---|
| 97 | // Tptr_t top_old = reg_TOP [i]; |
---|
| 98 | // Tptr_t top_new; |
---|
| 99 | |
---|
| 100 | // Tcontrol_t hit = PORT_READ(in_DECOD_HIT [i]); |
---|
| 101 | // Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); |
---|
| 102 | |
---|
| 103 | // if (push) |
---|
| 104 | // { |
---|
| 105 | // // push |
---|
| 106 | // top_new = (top_old+1)%_param->_size_queue[context]; |
---|
| 107 | |
---|
| 108 | // reg_stack [context][top_new]._val = true; |
---|
| 109 | // reg_stack [context][top_new]._predict = false; |
---|
| 110 | // reg_stack [context][top_new]._miss = false; |
---|
| 111 | // reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); |
---|
| 112 | |
---|
| 113 | // // the stack is full, erase the most old stack |
---|
| 114 | // if (top_old == reg_BOTTOM [i]) |
---|
| 115 | // reg_BOTTOM [i] = top_new; |
---|
| 116 | // } |
---|
| 117 | // else |
---|
| 118 | // { |
---|
| 119 | // // pop |
---|
| 120 | // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
---|
| 121 | |
---|
| 122 | // //reg_stack [context][top_new]._val = ; |
---|
| 123 | // //reg_stack [context][top_new]._predict = ; |
---|
| 124 | // //reg_stack [context][top_new]._miss = ; |
---|
| 125 | // //reg_stack [context][top_new]._address = ; |
---|
| 126 | // } |
---|
| 127 | |
---|
| 128 | // reg_TOP [i] = top_new; |
---|
| 129 | |
---|
| 130 | // // have previous miss of ifetch ? |
---|
| 131 | // // 2 miss : |
---|
| 132 | // // 1) miss predict : is very limited (local at context), can be update very quickly |
---|
| 133 | // // 2) miss decod : result is in commit stage ... |
---|
| 134 | // if (miss) |
---|
| 135 | // { |
---|
| 136 | // reg_PREDICT_BOTTOM [i] = reg_BOTTOM [i]; |
---|
| 137 | // reg_PREDICT_TOP [i] = reg_TOP [i]; |
---|
| 138 | |
---|
| 139 | // for (uint32_t j=0; j<_param->_size_queue [i]; j++) |
---|
| 140 | // if (reg_stack [context][top_new]._predict) |
---|
| 141 | // { |
---|
| 142 | // reg_stack [context][top_new]._predict = false; |
---|
| 143 | // reg_stack [context][top_new]._miss = true; |
---|
| 144 | // } |
---|
| 145 | // } |
---|
| 146 | // } |
---|
| 147 | |
---|
| 148 | // =================================================================== |
---|
| 149 | // =====[ UPDATE ]=================================================== |
---|
| 150 | // =================================================================== |
---|
| 151 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
---|
| 152 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
---|
| 153 | { |
---|
| 154 | Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
| 155 | Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); |
---|
| 156 | Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); |
---|
| 157 | |
---|
| 158 | if (PORT_READ(in_UPDATE_MISS_PREDICTION [i])) |
---|
| 159 | { |
---|
| 160 | if (push) |
---|
| 161 | { |
---|
| 162 | // push |
---|
| 163 | top_new = (top_old+1)%_param->_size_queue[context]; |
---|
| 164 | |
---|
| 165 | reg_stack [context][index]._val = true; |
---|
| 166 | reg_stack [context][index]._predict = false; |
---|
| 167 | reg_stack [context][index]._miss = false; |
---|
| 168 | reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); |
---|
| 169 | |
---|
| 170 | } |
---|
| 171 | else |
---|
| 172 | { |
---|
| 173 | //reg_stack [context][top_new]._val = ; |
---|
| 174 | //reg_stack [context][top_new]._predict = ; |
---|
| 175 | //reg_stack [context][top_new]._miss = ; |
---|
| 176 | //reg_stack [context][top_new]._address = ; |
---|
| 177 | } |
---|
| 178 | |
---|
| 179 | // Mouais bof ....... |
---|
| 180 | reg_PREDICT_TOP [i] = index; |
---|
| 181 | } |
---|
| 182 | } |
---|
| 183 | } |
---|
| 184 | |
---|
| 185 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 186 | end_cycle (); |
---|
| 187 | #endif |
---|
| 188 | |
---|
| 189 | log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); |
---|
| 190 | }; |
---|
| 191 | |
---|
| 192 | }; // end namespace return_address_stack |
---|
| 193 | }; // end namespace prediction_unit |
---|
| 194 | }; // end namespace front_end |
---|
| 195 | }; // end namespace multi_front_end |
---|
| 196 | }; // end namespace core |
---|
| 197 | |
---|
| 198 | }; // end namespace behavioural |
---|
| 199 | }; // end namespace morpheo |
---|
| 200 | #endif |
---|