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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 111

Last change on this file since 111 was 111, checked in by rosiere, 15 years ago
1) Decod_queue : multi implementation (one_fifo, multi_fifo) 2) Issue_queue : multi implementation (in_order, out_of_order) 3) Direction : Add Meta predictor 4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative) 5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction 6) UPT : Fix bug in multi event 7) Prediction_glue : in read_stack case, insert in UPT pc_next 8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0
Property svn:keywords set to `Id`
File size: 141.4 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101	ALLOC1_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,"out_DECOD_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
102
103	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
111	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
112	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
113
114	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
115	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
116	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
118	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
121	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
122
123	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
139	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
140
141	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
142	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
144	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
145
146	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
147	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
148	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
149	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
150	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
151
152	/********************************************************
153	* Instanciation
154	********************************************************/
155
156	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
157
158	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
159	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
160
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
162	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
163	if (_param->_have_port_context_id)
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
169	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
170	if (_param->_have_port_history)
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
173	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
174	if (_param->_have_port_depth)
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
178	if (_param->_have_port_context_id)
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
187	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
188	if (_param->_have_port_depth)
189	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
190	//if (_param->_have_port_depth)
191	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod);
194
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
196	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
197	if (_param->_have_port_context_id)
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
199	if (_param->_have_port_depth)
200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
204	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
205	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
206	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
207
208	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
209	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
210	//if (_param->_have_port_context_id)
211	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
212	if (_param->_have_port_depth)
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
214	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
215	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
218
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
221	if (_param->_have_port_context_id)
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
227	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
230	if (_param->_have_port_history)
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
238	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
239	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
241	if (_param->_have_port_depth)
242	{
243	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
244	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
247	}
248	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
249	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
250
251	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
252
253	Time * _time = new Time();
254
255	/********************************************************
256	* Simulation - Begin
257	********************************************************/
258
259	// Initialisation
260
261	const uint32_t seed = 0;
262	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
263
264	srand(seed);
265
266	const int32_t percent_transaction_predict = 75;
267	const int32_t percent_transaction_decod = 75;
268	const int32_t percent_transaction_branch_complete = 75;
269	const int32_t percent_transaction_update = 75;
270	const int32_t percent_transaction_branch_event = 75;
271	const int32_t percent_transaction_event = 75;
272
273	const bool test1 = true;
274	const bool test2 = true;
275	const bool test3 = true;
276	const bool test4 = true;
277	const bool test5 = true;
278
279	std::list<request_t> ufpt;
280	std::list<request_t> upt;
281	request_t event;
282
283	SC_START(0);
284	LABEL("Initialisation");
285
286	LABEL("Reset");
287	in_NRESET->write(0);
288	SC_START(5);
289	in_NRESET->write(1);
290
291	Tdepth_t ufpt_bottom [_param->_nb_context];
292	Tdepth_t ufpt_top [_param->_nb_context];
293
294	Tdepth_t upt_bottom [_param->_nb_context];
295	Tdepth_t upt_top [_param->_nb_context];
296	Tdepth_t upt_top_event[_param->_nb_context];
297
298	for (uint32_t i=0; i<_param->_nb_context; ++i)
299	{
300	ufpt_bottom [i] = 0;
301	ufpt_top [i] = 0;
302	upt_bottom [i] = 0;
303	upt_top [i] = 0;
304	upt_top_event[i] = 0;
305	}
306
307	for (uint32_t i=0; i<_param->_nb_context; ++i)
308	{
309	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
310	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
311	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
312	}
313
314	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
315	{
316	LABEL("Iteration %d",iteration);
317
318	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
319	in_PREDICT_VAL [i]->write(0);
320	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
321	in_DECOD_VAL [i]->write(0);
322	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
323	in_BRANCH_COMPLETE_VAL [i]->write(0);
324	for (uint32_t i=0; i<_param->_nb_context; ++i)
325	in_BRANCH_EVENT_ACK [i]->write(0);
326	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
327	in_UPDATE_ACK [i]->write(0);
328	for (uint32_t i=0; i<_param->_nb_context; ++i)
329	in_EVENT_VAL [i]->write(0);
330
331	//---------------------------------------------------------------------
332	//---------------------------------------------------------------------
333	// COMMON CASE
334	//---------------------------------------------------------------------
335	//---------------------------------------------------------------------
336	if (test1)
337	{
338	uint32_t context = rand() % _param->_nb_context;
339
340	{
341	LABEL("PREDICT - fill the queue");
342	uint32_t port = rand() % _param->_nb_inst_predict;
343
344	LABEL(" * context : %d",context);
345	LABEL(" * port : %d",port);
346
347	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
348	{
349	request_t request;
350	request.context = context;
351	request.address_src = 0xdeadbeef+i;
352	request.address_dest = 0x21071981+i;
353	request.address_good = request.address_dest;
354	request.condition = BRANCH_CONDITION_FLAG_SET;
355	request.take = 1;
356	request.take_good = 1;
357	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
358	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
359	request.is_accurate = true;
360	request.miss_ifetch = false;
361	request.miss_decod = false;
362	request.miss_commit = false;
363	request.history = i;
364	request.ras_address = 0xdeaddead+i;
365	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
366	request.ufpt_ptr = ufpt_top [context];
367	// request.upt_ptr;
368
369	bool have_transaction = false;
370	do
371	{
372	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
373	in_PREDICT_CONTEXT_ID [port]->write(request.context );
374	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
375	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
376	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
377	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
378	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
379	in_PREDICT_DIR_HISTORY [port]->write(request.history );
380	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
381	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
382
383	if (_param->_have_port_depth)
384	{
385	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
386	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
387	}
388	SC_START(0); // fct melay
389
390	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
391	port,
392	in_PREDICT_VAL [port]->read(),
393	out_PREDICT_ACK [port]->read(),
394	in_PREDICT_BTB_IS_ACCURATE [port]->read());
395
396	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
397	{
398	LABEL("PREDICT [%d] - Transaction accepted",port);
399	have_transaction = true;
400
401	if (_param->_have_port_depth)
402	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
403
404	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
405	}
406
407	SC_START(1); // transition
408
409	} while (not have_transaction);
410
411	ufpt.push_back(request);
412
413	in_PREDICT_VAL [port]->write(0);
414
415	if (_param->_have_port_depth)
416	{
417	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
418	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
419	}
420	}
421	}
422
423	{
424	LABEL("DECOD");
425	uint32_t port = rand() % _param->_nb_inst_decod;
426
427	LABEL(" * context : %d",context);
428	LABEL(" * port : %d",port);
429
430	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
431	{
432	request_t request = ufpt.front();
433
434	bool have_transaction = false;
435	do
436	{
437	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
438	in_DECOD_CONTEXT_ID [port]->write(request.context );
439	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
440	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
441	in_DECOD_BTB_CONDITION [port]->write(request.condition );
442	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
443	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
444	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
445	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
446	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
447	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
448	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
449
450	SC_START(0); // fct melay
451
452	LABEL("DECOD [%d] %d - %d",
453	port,
454	in_PREDICT_VAL [port]->read(),
455	out_PREDICT_ACK [port]->read());
456
457	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
458	{
459	LABEL("DECOD [%d] - Transaction accepted",port);
460	have_transaction = true;
461
462	request.upt_ptr = upt_top [context];
463	upt.push_back(request);
464	ufpt.pop_front();
465
466	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
467	}
468
469	SC_START(1); // transition
470
471	} while (not have_transaction);
472
473	in_DECOD_VAL [port]->write(0);
474
475	if (_param->_have_port_depth)
476	{
477	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
478	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
479	}
480	}
481	}
482
483	{
484	LABEL("BRANCH_COMPLETE - hit ifetch");
485
486	uint32_t port = rand() % _param->_nb_inst_branch_complete;
487
488	LABEL(" * port : %d",port);
489
490	std::list<request_t>::iterator it_upt = upt.begin();
491
492	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
493	for (uint32_t i=0; i<upt.size(); i++)
494	{
495	bool have_transaction = false;
496
497	do
498	{
499	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
500	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
501	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
502	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
503	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
504
505	if (_param->_have_port_depth)
506	{
507	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
508	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
509	}
510
511	SC_START(0);
512
513	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
514
515	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
516	{
517	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
518	have_transaction = true;
519
520	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
521	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
522	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
523	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
524
525	it_upt ++;
526	}
527
528	SC_START(1);
529	} while (not have_transaction);
530
531	in_BRANCH_COMPLETE_VAL [port]->write(0);
532
533	if (_param->_have_port_depth)
534	{
535	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
536	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
537	}
538	}
539	}
540
541	{
542	LABEL("UPDATE - hit ifetch");
543
544	uint32_t port = 0;
545
546	LABEL(" * port : %d",port);
547	std::list<request_t>::iterator it_upt = upt.begin();
548
549	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
550	for (uint32_t i=0; i<upt.size(); i++)
551	{
552	bool have_transaction = false;
553
554	do
555	{
556	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
557
558	// if (_param->_have_port_depth)
559	// {
560	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
561	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
562	// }
563
564	SC_START(0);
565
566	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
567
568	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
569	{
570	LABEL("UPDATE [%d] - Transaction accepted",port);
571	have_transaction = true;
572
573	if (_param->_have_port_context_id)
574	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
575	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
576	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
577	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
578	if (update_btb(it_upt->condition))
579	{
580	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
581	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
582	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
583	}
584	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
585	if (update_dir(it_upt->condition))
586	if (_param->_have_port_history)
587	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
588	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
589	if (update_ras(it_upt->condition))
590	{
591	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
592	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
593	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
594	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
595	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
596	}
597	++ it_upt;
598	}
599
600	SC_START(1);
601	} while (not have_transaction);
602
603	in_UPDATE_ACK [port]->write(0);
604	// if (_param->_have_port_depth)
605	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
606	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
607	}
608	upt.clear();
609	}
610
611	// Wait Garbage Collector
612	{
613	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
614	// upt_top [context] = (upt_top [context]);
615
616	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
617	(upt_top [context] != out_DEPTH_MAX [context]->read()))
618	SC_START(1);
619
620	}
621	}
622
623	//---------------------------------------------------------------------
624	//---------------------------------------------------------------------
625	// DECOD MISS : no RAS in ifetch
626	//---------------------------------------------------------------------
627	//---------------------------------------------------------------------
628	if (test2)
629	{
630	uint32_t context = rand() % _param->_nb_context;
631
632	{
633	LABEL("PREDICT - fill the queue");
634	uint32_t port = rand() % _param->_nb_inst_predict;
635
636	LABEL(" * context : %d",context);
637	LABEL(" * port : %d",port);
638
639	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
640	{
641	request_t request;
642	request.context = context;
643	request.address_src = 0xdeadbeef+i;
644	request.address_dest = 0x21071981+i;
645	request.address_good = request.address_dest;
646	request.condition = BRANCH_CONDITION_FLAG_SET;
647	request.take = 1;
648	request.take_good = 1;
649	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
650	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
651	request.is_accurate = true;
652	request.miss_ifetch = false;
653	request.miss_decod = false;
654	request.miss_commit = false;
655	request.history = i;
656	request.ras_address = 0xdeaddead+i;
657	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
658	request.ufpt_ptr = ufpt_top [context];
659	// request.upt_ptr;
660
661	bool have_transaction = false;
662	do
663	{
664	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
665	in_PREDICT_CONTEXT_ID [port]->write(request.context );
666	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
667	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
668	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
669	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
670	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
671	in_PREDICT_DIR_HISTORY [port]->write(request.history );
672	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
673	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
674
675	if (_param->_have_port_depth)
676	{
677	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
678	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
679	}
680	SC_START(0); // fct melay
681
682	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
683	port,
684	in_PREDICT_VAL [port]->read(),
685	out_PREDICT_ACK [port]->read(),
686	in_PREDICT_BTB_IS_ACCURATE [port]->read());
687
688	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
689	{
690	LABEL("PREDICT [%d] - Transaction accepted",port);
691	have_transaction = true;
692
693	if (_param->_have_port_depth)
694	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
695
696	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
697	}
698
699	SC_START(1); // transition
700
701	} while (not have_transaction);
702
703	// ufpt.push_back(request);
704
705	in_PREDICT_VAL [port]->write(0);
706
707	if (_param->_have_port_depth)
708	{
709	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
710	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
711	}
712	}
713	}
714
715	{
716	LABEL("DECOD - Miss");
717	uint32_t port = rand() % _param->_nb_inst_decod;
718
719	LABEL(" * context : %d",context);
720	LABEL(" * port : %d",port);
721
722	request_t request;
723	request.context = context;
724	request.address_src = 0x14011959;
725	request.address_dest = 0x25071959; // after = not take
726	request.address_good = request.address_dest;
727	request.condition = BRANCH_CONDITION_FLAG_SET;
728	request.take = 0;
729	request.take_good = 0;
730	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
731	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
732	request.is_accurate = true;
733	request.miss_ifetch = false;
734	request.miss_decod = true ;
735	request.miss_commit = false;
736	request.history = 1;
737	request.ras_address = 0xbabababa;
738	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
739	request.ufpt_ptr = ufpt_top [context];
740	request.upt_ptr = upt_top [context];
741
742	event = request;
743
744	// for (uint32_t i=0; i<upt.size(); i++)
745	// just one
746	{
747	bool have_transaction = false;
748	do
749	{
750	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
751	in_DECOD_CONTEXT_ID [port]->write(request.context );
752	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
753	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
754	in_DECOD_BTB_CONDITION [port]->write(request.condition );
755	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
756	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
757	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
758	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
759	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
760	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
761	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
762
763	SC_START(0); // fct melay
764
765	LABEL("DECOD [%d] %d - %d",
766	port,
767	in_PREDICT_VAL [port]->read(),
768	out_PREDICT_ACK [port]->read());
769
770	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
771	{
772	LABEL("DECOD [%d] - Transaction accepted",port);
773	have_transaction = true;
774
775	request.upt_ptr = upt_top [context];
776	upt.push_back(request);
777	// ufpt.pop_front();
778
779	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
780	}
781
782	SC_START(1); // transition
783
784	} while (not have_transaction);
785
786	in_DECOD_VAL [port]->write(0);
787
788	if (_param->_have_port_depth)
789	{
790	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
791	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
792	}
793	}
794	}
795
796	{
797	LABEL("BRANCH_COMPLETE - hit ifetch");
798
799	uint32_t port = rand() % _param->_nb_inst_branch_complete;
800
801	LABEL(" * port : %d",port);
802
803	std::list<request_t>::iterator it_upt = upt.begin();
804
805	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
806	// for (uint32_t i=0; i<upt.size(); i++)
807	// just one
808	{
809	bool have_transaction = false;
810
811	do
812	{
813	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
814	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
815	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
816	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
817	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
818
819	if (_param->_have_port_depth)
820	{
821	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
822	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
823	}
824	SC_START(0);
825
826	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
827
828	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
829	{
830	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
831	have_transaction = true;
832
833	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
834	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
835	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
836	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
837
838	it_upt ++;
839	}
840
841	SC_START(1);
842	} while (not have_transaction);
843
844	in_BRANCH_COMPLETE_VAL [port]->write(0);
845
846	if (_param->_have_port_depth)
847	{
848	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
849	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
850	}
851	}
852	}
853
854	{
855	LABEL("UPDATE - hit ifetch");
856
857	uint32_t port = 0;
858
859	LABEL(" * port : %d",port);
860	std::list<request_t>::iterator it_upt = upt.begin();
861
862	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
863	// for (uint32_t i=0; i<upt.size(); i++)
864	// just one
865	{
866	bool have_transaction = false;
867
868	do
869	{
870	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
871
872	// if (_param->_have_port_depth)
873	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
874	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
875
876	SC_START(0);
877
878	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
879
880	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
881	{
882	LABEL("UPDATE [%d] - Transaction accepted",port);
883	have_transaction = true;
884
885	if (_param->_have_port_context_id)
886	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
887	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
888	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
889	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
890	if (update_btb(it_upt->condition))
891	{
892	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
893	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
894	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
895	}
896	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
897
898	if (update_dir(it_upt->condition))
899	if (_param->_have_port_history)
900	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
901	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
902	if (update_ras(it_upt->condition))
903	{
904	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
905	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
906	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
907	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
908	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
909	}
910	++ it_upt;
911	}
912
913	SC_START(1);
914	} while (not have_transaction);
915
916	in_UPDATE_ACK [port]->write(0);
917	// if (_param->_have_port_depth)
918	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
919	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
920	}
921	upt.clear();
922	}
923
924	{
925	LABEL("BRANCH_EVENT - have miss decod");
926
927	uint32_t port = context;
928
929	{
930	bool have_transaction = false;
931
932	do
933	{
934	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
935
936	SC_START(0);
937
938	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
939
940	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
941	{
942	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
943	have_transaction = true;
944
945	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
946	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
947	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
948	if (event.take)
949	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
950
951	event.address_src = 0;
952	event.take = 0;
953	event.address_dest = 0;
954	}
955
956	SC_START(1);
957	} while (not have_transaction);
958
959	in_BRANCH_EVENT_ACK [port]->write(0);
960	}
961	}
962
963	{
964	LABEL("EVENT_STATE");
965
966	SC_START(1);
967	in_EVENT_VAL [context]->write(1);
968	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
969
970	SC_START(1);
971	in_EVENT_VAL [context]->write(0);
972	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
973	}
974
975	// Wait Garbage Collector
976	{
977	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
978	// upt_top [context] = (upt_top [context]);
979
980	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
981	(upt_top [context] != out_DEPTH_MAX [context]->read()))
982	SC_START(1);
983
984	}
985	}
986
987	//---------------------------------------------------------------------
988	//---------------------------------------------------------------------
989	// DECOD MISS : with RAS in ifetch
990	//---------------------------------------------------------------------
991	//---------------------------------------------------------------------
992	if (test3)
993	{
994	uint32_t context = rand() % _param->_nb_context;
995	uint32_t have_ras = false;
996	{
997	LABEL("PREDICT - fill the queue");
998	uint32_t port = rand() % _param->_nb_inst_predict;
999
1000	LABEL(" * context : %d",context);
1001	LABEL(" * port : %d",port);
1002
1003	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1004	{
1005	request_t request;
1006	request.context = context;
1007	request.address_src = 0xdeadbeef+i;
1008	request.address_dest = 0x21071981+i;
1009	request.address_good = request.address_dest;
1010	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1011	BRANCH_CONDITION_FLAG_SET;
1012
1013	have_ras \|= (update_ras(request.condition));
1014
1015	request.take = 1;
1016	request.take_good = 1;
1017	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1018	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1019	request.is_accurate = true;
1020	request.miss_ifetch = false;
1021	request.miss_decod = true ;
1022	request.miss_commit = false;
1023	request.history = i;
1024	request.ras_address = 0x12344321+i;
1025	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
1026	request.ufpt_ptr = ufpt_top [context];
1027	// request.upt_ptr;
1028
1029	bool have_transaction = false;
1030	do
1031	{
1032	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1033	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1034	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1035	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1036	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1037	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1038	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1039	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1040	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1041	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1042
1043	if (_param->_have_port_depth)
1044	{
1045	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1046	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1047	}
1048	SC_START(0); // fct melay
1049
1050	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1051	port,
1052	in_PREDICT_VAL [port]->read(),
1053	out_PREDICT_ACK [port]->read(),
1054	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1055
1056	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1057	{
1058	LABEL("PREDICT [%d] - Transaction accepted",port);
1059	have_transaction = true;
1060
1061	if (_param->_have_port_depth)
1062	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1063
1064	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1065	}
1066
1067	SC_START(1); // transition
1068
1069	} while (not have_transaction);
1070
1071	ufpt.push_back(request); // to update
1072
1073	in_PREDICT_VAL [port]->write(0);
1074
1075	if (_param->_have_port_depth)
1076	{
1077	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1078	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1079	}
1080	}
1081	}
1082
1083	{
1084	LABEL("DECOD - Miss");
1085	uint32_t port = rand() % _param->_nb_inst_decod;
1086
1087	LABEL(" * context : %d",context);
1088	LABEL(" * port : %d",port);
1089
1090	request_t request;
1091	request.context = context;
1092	request.address_src = 0x14011959;
1093	request.address_dest = 0x25071959; // after = not take
1094	request.address_good = request.address_dest;
1095	request.condition = BRANCH_CONDITION_FLAG_SET;
1096	request.take = 0;
1097	request.take_good = 0;
1098	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1099	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1100	request.is_accurate = true;
1101	request.miss_ifetch = false;
1102	request.miss_decod = true ;
1103	request.miss_commit = false;
1104	request.history = 1;
1105	request.ras_address = 0xbabababa;
1106	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1107	request.ufpt_ptr = ufpt_top [context];
1108	request.upt_ptr = upt_top [context];
1109
1110	event = request;
1111
1112	// for (uint32_t i=0; i<upt.size(); i++)
1113	// just one
1114	{
1115	bool have_transaction = false;
1116	do
1117	{
1118	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1119	in_DECOD_CONTEXT_ID [port]->write(request.context );
1120	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1121	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1122	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1123	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1124	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1125	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1126	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1127	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1128	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1129	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1130
1131	SC_START(0); // fct melay
1132
1133	LABEL("DECOD [%d] %d - %d",
1134	port,
1135	in_PREDICT_VAL [port]->read(),
1136	out_PREDICT_ACK [port]->read());
1137
1138	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1139	{
1140	LABEL("DECOD [%d] - Transaction accepted",port);
1141	have_transaction = true;
1142
1143	request.upt_ptr = upt_top [context];
1144	upt.push_back(request);
1145	// ufpt.pop_front();
1146
1147	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1148	}
1149
1150	SC_START(1); // transition
1151
1152	} while (not have_transaction);
1153
1154	in_DECOD_VAL [port]->write(0);
1155
1156	if (_param->_have_port_depth)
1157	{
1158	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1159	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1160	}
1161	}
1162	}
1163
1164	{
1165	LABEL("BRANCH_COMPLETE - hit ifetch");
1166
1167	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1168
1169	LABEL(" * port : %d",port);
1170
1171	std::list<request_t>::iterator it_upt = upt.begin();
1172
1173	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1174	// for (uint32_t i=0; i<upt.size(); i++)
1175	// just one
1176	{
1177	bool have_transaction = false;
1178
1179	do
1180	{
1181	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1182	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1183	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1184	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1185	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1186
1187	if (_param->_have_port_depth)
1188	{
1189	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1190	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1191	}
1192	SC_START(0);
1193
1194	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1195
1196	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1197	{
1198	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1199	have_transaction = true;
1200
1201	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1202	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1203	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1204	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1205
1206	it_upt ++;
1207	}
1208
1209	SC_START(1);
1210	} while (not have_transaction);
1211
1212	in_BRANCH_COMPLETE_VAL [port]->write(0);
1213
1214	if (_param->_have_port_depth)
1215	{
1216	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1217	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1218	}
1219	}
1220	}
1221
1222	if (have_ras)
1223	{
1224	LABEL("UPDATE - Update UPFT");
1225
1226	uint32_t port = 0;
1227
1228	LABEL(" * port : %d",port);
1229	std::list<request_t>::iterator it_ufpt = ufpt.end();
1230	-- it_ufpt;
1231
1232	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1233	{
1234	bool have_transaction = false;
1235
1236	do
1237	{
1238	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1239
1240	// if (_param->_have_port_depth)
1241	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1242	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1243
1244	SC_START(0);
1245
1246	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1247
1248	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1249	{
1250	LABEL("UPDATE [%d] - Transaction accepted",port);
1251	have_transaction = true;
1252
1253	if (_param->_have_port_context_id)
1254	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1255	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1256	it_ufpt->miss_decod or
1257	it_ufpt->miss_commit ));
1258	// if (update_btb(it_ufpt->condition) or
1259	// update_dir(it_ufpt->condition))
1260	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1261	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1262	// if (update_btb(it_ufpt->condition))
1263	// {
1264	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1265	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1266	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1267	// }
1268	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1269
1270	// if (update_dir(it_ufpt->condition))
1271	// if (_param->_have_port_history)
1272	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1273	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1274	if (update_ras(it_ufpt->condition))
1275	{
1276	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1277	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1278	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1279	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1280
1281	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1282	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1283	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1284	}
1285	}
1286
1287	SC_START(1);
1288	} while (not have_transaction);
1289
1290	-- it_ufpt;
1291
1292
1293	in_UPDATE_ACK [port]->write(0);
1294	// if (_param->_have_port_depth)
1295	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1296	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1297	}
1298	}
1299	ufpt.clear();
1300
1301	{
1302	LABEL("UPDATE - hit ifetch");
1303
1304	uint32_t port = 0;
1305
1306	LABEL(" * port : %d",port);
1307	std::list<request_t>::iterator it_upt = upt.begin();
1308
1309	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1310	// for (uint32_t i=0; i<upt.size(); i++)
1311	// just one
1312	{
1313	bool have_transaction = false;
1314
1315	do
1316	{
1317	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1318
1319	// if (_param->_have_port_depth)
1320	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1321	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1322
1323	SC_START(0);
1324
1325	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1326
1327	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1328	{
1329	LABEL("UPDATE [%d] - Transaction accepted",port);
1330	have_transaction = true;
1331
1332	if (_param->_have_port_context_id)
1333	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1334	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1335	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1336	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1337	if (update_btb(it_upt->condition))
1338	{
1339	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1340	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1341	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1342	}
1343	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1344
1345	if (update_dir(it_upt->condition))
1346	if (_param->_have_port_history)
1347	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1348	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1349	if (update_ras(it_upt->condition))
1350	{
1351	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1352	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1353	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1354	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1355	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1356	}
1357	++ it_upt;
1358	}
1359
1360	SC_START(1);
1361	} while (not have_transaction);
1362
1363	in_UPDATE_ACK [port]->write(0);
1364	// if (_param->_have_port_depth)
1365	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1366	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1367	}
1368	}
1369	upt.clear();
1370
1371	{
1372	LABEL("BRANCH_EVENT - have miss decod");
1373
1374	uint32_t port = context;
1375
1376	{
1377	bool have_transaction = false;
1378
1379	do
1380	{
1381	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1382
1383	SC_START(0);
1384
1385	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1386
1387	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1388	{
1389	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1390	have_transaction = true;
1391
1392	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1393	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1394	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1395	if (event.take)
1396	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1397
1398	event.address_src = 0;
1399	event.take = 0;
1400	event.address_dest = 0;
1401	}
1402
1403	SC_START(1);
1404	} while (not have_transaction);
1405
1406	in_BRANCH_EVENT_ACK [port]->write(0);
1407	}
1408	}
1409
1410	{
1411	LABEL("EVENT_STATE");
1412
1413	SC_START(1);
1414	in_EVENT_VAL [context]->write(1);
1415	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
1416
1417	SC_START(1);
1418	in_EVENT_VAL [context]->write(0);
1419	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1420	}
1421
1422	// Wait Garbage Collector
1423	{
1424	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1425	// upt_top [context] = (upt_top [context]);
1426
1427	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1428	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1429	SC_START(1);
1430	}
1431	}
1432
1433	//---------------------------------------------------------------------
1434	//---------------------------------------------------------------------
1435	// COMMIT MISS : with RAS in UPFT and UPT
1436	//---------------------------------------------------------------------
1437	//---------------------------------------------------------------------
1438	if (test4)
1439	{
1440	uint32_t context = rand() % _param->_nb_context;
1441	uint32_t have_ufpt_ras = false;
1442	uint32_t have_upt_ras = false;
1443	{
1444	LABEL("PREDICT - fill the queue");
1445	uint32_t port = rand() % _param->_nb_inst_predict;
1446
1447	LABEL(" * context : %d",context);
1448	LABEL(" * port : %d",port);
1449
1450	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1451	{
1452	request_t request;
1453	request.context = context;
1454	request.address_src = rand();
1455	request.address_dest = rand();
1456
1457	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
1458	BRANCH_CONDITION_FLAG_SET;
1459
1460	request.take = 1;
1461	request.take_good = 1;
1462	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1463	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1464	request.is_accurate = true ;
1465	request.miss_ifetch = false;
1466	request.miss_decod = false;
1467	request.miss_commit = false;
1468	request.history = i;
1469	request.ras_address = rand();
1470	request.ras_index = rand()%_param->_size_ras_index[context];
1471	request.ufpt_ptr = ufpt_top [context];
1472	// request.upt_ptr;
1473
1474	bool have_transaction = false;
1475	do
1476	{
1477	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1478	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1479	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1480	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1481	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1482	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1483	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1484	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1485	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1486	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1487
1488	if (_param->_have_port_depth)
1489	{
1490	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1491	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1492	}
1493	SC_START(0); // fct melay
1494
1495	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1496	port,
1497	in_PREDICT_VAL [port]->read(),
1498	out_PREDICT_ACK [port]->read(),
1499	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1500
1501	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1502	{
1503	LABEL("PREDICT [%d] - Transaction accepted",port);
1504	have_transaction = true;
1505
1506	if (_param->_have_port_depth)
1507	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1508
1509	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1510	}
1511
1512	SC_START(1); // transition
1513
1514	} while (not have_transaction);
1515
1516	ufpt.push_back(request); // to update
1517
1518	in_PREDICT_VAL [port]->write(0);
1519
1520	if (_param->_have_port_depth)
1521	{
1522	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1523	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1524	}
1525	}
1526	}
1527
1528	{
1529	LABEL("DECOD");
1530	uint32_t port = rand() % _param->_nb_inst_decod;
1531
1532	LABEL(" * context : %d",context);
1533	LABEL(" * port : %d",port);
1534
1535	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1536	{
1537	request_t request = ufpt.front();
1538
1539	bool have_transaction = false;
1540	do
1541	{
1542	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1543	in_DECOD_CONTEXT_ID [port]->write(request.context );
1544	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1545	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1546	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1547	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1548	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1549	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1550	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1551	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1552	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1553	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1554
1555	have_upt_ras \|= (update_ras(request.condition));
1556
1557	SC_START(0); // fct melay
1558
1559	LABEL("DECOD [%d] %d - %d",
1560	port,
1561	in_DECOD_VAL [port]->read(),
1562	out_DECOD_ACK [port]->read());
1563
1564	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1565	{
1566	LABEL("DECOD [%d] - Transaction accepted",port);
1567	have_transaction = true;
1568
1569	request.upt_ptr = upt_top [context];
1570	upt.push_back(request);
1571	ufpt.pop_front();
1572
1573	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1574	}
1575
1576	SC_START(1); // transition
1577
1578	} while (not have_transaction);
1579
1580	in_DECOD_VAL [port]->write(0);
1581
1582	if (_param->_have_port_depth)
1583	{
1584	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1585	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1586	}
1587	}
1588	}
1589
1590	{
1591	LABEL("PREDICT - fill the queue");
1592	uint32_t port = rand() % _param->_nb_inst_predict;
1593
1594	LABEL(" * context : %d",context);
1595	LABEL(" * port : %d",port);
1596
1597	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1598	{
1599	request_t request;
1600	request.context = context;
1601	request.address_src = rand();
1602	request.address_dest = rand();
1603	request.address_good = request.address_dest;
1604	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1605	BRANCH_CONDITION_FLAG_SET;
1606
1607	have_ufpt_ras \|= (update_ras(request.condition));
1608
1609	request.take = 1;
1610	request.take_good = 1;
1611	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1612	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1613	request.is_accurate = true ;
1614	request.miss_ifetch = false;
1615	request.miss_decod = false;
1616	request.miss_commit = true;
1617	request.history = i;
1618	request.ras_address = rand();
1619	request.ras_index = rand()%_param->_size_ras_index[context];
1620	request.ufpt_ptr = ufpt_top [context];
1621	// request.upt_ptr;
1622
1623	bool have_transaction = false;
1624	do
1625	{
1626	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1627	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1628	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1629	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1630	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1631	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1632	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1633	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1634	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1635	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1636
1637	if (_param->_have_port_depth)
1638	{
1639	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1640	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1641	}
1642	SC_START(0); // fct melay
1643
1644	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1645	port,
1646	in_PREDICT_VAL [port]->read(),
1647	out_PREDICT_ACK [port]->read(),
1648	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1649
1650	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1651	{
1652	LABEL("PREDICT [%d] - Transaction accepted",port);
1653	have_transaction = true;
1654
1655	if (_param->_have_port_depth)
1656	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1657
1658	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1659	}
1660
1661	SC_START(1); // transition
1662
1663	} while (not have_transaction);
1664
1665	ufpt.push_back(request); // to update
1666
1667	in_PREDICT_VAL [port]->write(0);
1668
1669	if (_param->_have_port_depth)
1670	{
1671	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1672	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1673	}
1674	}
1675	}
1676
1677	std::list<request_t>::iterator it_event;
1678	{
1679	LABEL("BRANCH_COMPLETE - Miss ifetch");
1680
1681	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1682
1683	LABEL(" * port : %d",port);
1684
1685	// middle
1686	it_event = upt.begin();
1687	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1688	it_event ++;
1689
1690	for (std::list<request_t>::iterator it_upt = it_event;
1691	it_upt != upt.end();
1692	++it_upt)
1693	it_upt->miss_commit = true;
1694
1695	if (update_ras(it_event->condition))
1696	{
1697	it_event->address_good = ~(it_event->address_dest);
1698	}
1699	else
1700	{
1701	it_event->address_good = it_event->address_dest;
1702	it_event->flag = not it_event->flag;
1703	it_event->no_sequence = not it_event->no_sequence;
1704	it_event->take_good = not it_event->take_good;
1705	}
1706
1707	event = *it_event;
1708
1709
1710	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1711	// for (uint32_t i=0; i<upt.size(); i++)
1712	// just one
1713	{
1714	bool have_transaction = false;
1715
1716	do
1717	{
1718	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1719	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1720	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1721	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1722	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1723
1724	if (_param->_have_port_depth)
1725	{
1726	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1727	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1728	}
1729
1730	SC_START(0);
1731
1732	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1733
1734	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1735	{
1736	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1737	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1738	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1739	LABEL(" * CONDITION : %d" ,it_event->condition );
1740	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1741	LABEL(" * FLAG : %d" ,it_event->flag );
1742	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1743
1744	have_transaction = true;
1745
1746	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1747	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1748	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1749	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1750
1751	upt_top_event [it_event->context] = upt_top [it_event->context];
1752	upt_top [it_event->context] = it_event->upt_ptr;
1753	}
1754
1755	SC_START(1);
1756	} while (not have_transaction);
1757
1758	in_BRANCH_COMPLETE_VAL [port]->write(0);
1759
1760	if (_param->_have_port_depth)
1761	{
1762	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1763	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1764	}
1765	}
1766	}
1767
1768	{
1769	LABEL("BRANCH_COMPLETE - Hit ifetch");
1770
1771	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1772
1773	LABEL(" * port : %d",port);
1774
1775	std::list<request_t>::iterator it_upt = upt.begin();
1776
1777	while (it_upt != it_event)
1778	{
1779	bool have_transaction = false;
1780
1781	do
1782	{
1783	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1784	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1785	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1786	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1787	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1788
1789	if (_param->_have_port_depth)
1790	{
1791	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1792	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1793	}
1794	SC_START(0);
1795
1796	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1797
1798	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1799	{
1800	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1801	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1802	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1803	LABEL(" * CONDITION : %d" ,it_upt->condition );
1804	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1805	LABEL(" * FLAG : %d" ,it_upt->flag );
1806	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1807
1808	have_transaction = true;
1809
1810	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1811	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1812	it_upt->take_good = it_upt->take;
1813	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1814	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1815
1816	it_upt++;
1817	}
1818
1819	SC_START(1);
1820	} while (not have_transaction);
1821
1822	in_BRANCH_COMPLETE_VAL [port]->write(0);
1823
1824	if (_param->_have_port_depth)
1825	{
1826	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1827	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1828	}
1829	}
1830	}
1831
1832	if (have_ufpt_ras)
1833	{
1834	LABEL("UPDATE - Update UPFT");
1835
1836	uint32_t port = 0;
1837
1838	LABEL(" * port : %d",port);
1839	std::list<request_t>::iterator it_ufpt = ufpt.end();
1840	-- it_ufpt;
1841
1842	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1843	{
1844	bool have_transaction = false;
1845
1846	do
1847	{
1848	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1849
1850	// if (_param->_have_port_depth)
1851	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1852	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1853
1854	SC_START(0);
1855
1856	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1857
1858	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1859	{
1860	LABEL("UPDATE [%d] - Transaction accepted",port);
1861	have_transaction = true;
1862
1863	if (_param->_have_port_context_id)
1864	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1865	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1866	it_ufpt->miss_decod or
1867	it_ufpt->miss_commit ));
1868	// if (update_btb(it_ufpt->condition) or
1869	// update_dir(it_ufpt->condition))
1870	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1871	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1872	// if (update_btb(it_ufpt->condition))
1873	// {
1874	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1875	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1876	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1877	// }
1878	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1879
1880	// if (update_dir(it_ufpt->condition))
1881	// if (_param->_have_port_history)
1882	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1883	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1884	if (update_ras(it_ufpt->condition))
1885	{
1886	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1887	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1888	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1889	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1890	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1891	}
1892	}
1893
1894	SC_START(1);
1895	} while (not have_transaction);
1896
1897	-- it_ufpt;
1898
1899
1900	in_UPDATE_ACK [port]->write(0);
1901	// if (_param->_have_port_depth)
1902	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1903	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1904	}
1905	}
1906	ufpt.clear();
1907
1908	{
1909	LABEL("UPDATE - upt (after event)");
1910
1911	uint32_t port = 0;
1912
1913	LABEL(" * port : %d",port);
1914	std::list<request_t>::iterator it_upt = upt.end();
1915
1916	// for (uint32_t i=0; i<upt.size(); i++)
1917	do
1918	{
1919	--it_upt;
1920
1921	bool have_transaction = false;
1922
1923	if (need_update(it_upt->condition))
1924	do
1925	{
1926	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1927
1928	// if (_param->_have_port_depth)
1929	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1930	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1931
1932	SC_START(0);
1933
1934	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1935
1936	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1937	{
1938	LABEL("UPDATE [%d] - Transaction accepted",port);
1939	LABEL(" * address_src : %.8x",it_upt->address_src);
1940	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1941
1942	have_transaction = true;
1943
1944	bool btb_val = ((it_upt == it_event) and
1945	(update_btb(it_upt->condition)));
1946	bool dir_val = ((it_upt == it_event) and
1947	update_dir(it_upt->condition) and
1948	not (it_upt->miss_ifetch or it_upt->miss_decod));
1949	bool ras_val = update_ras(it_upt->condition);
1950
1951	if (_param->_have_port_context_id)
1952	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1953	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1954	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1955
1956	if (btb_val)
1957	{
1958	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1959	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1960	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1961	}
1962	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1963
1964	if (dir_val)
1965	{
1966	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1967	if (_param->_have_port_history)
1968	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1969	}
1970	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1971
1972	if (ras_val)
1973	{
1974	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1975	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1976	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1977	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1978	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1979	}
1980
1981	// -- it_upt;
1982	}
1983
1984	SC_START(1);
1985	} while (not have_transaction);
1986
1987	upt.pop_back();
1988	in_UPDATE_ACK [port]->write(0);
1989	// if (_param->_have_port_depth)
1990	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1991	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1992	}
1993	while (it_upt != it_event);
1994
1995	}
1996
1997	{
1998	LABEL("BRANCH_EVENT - have miss decod");
1999
2000	uint32_t port = context;
2001
2002	{
2003	bool have_transaction = false;
2004
2005	do
2006	{
2007	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2008
2009	SC_START(0);
2010
2011	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2012
2013	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2014	{
2015	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2016	have_transaction = true;
2017
2018	LABEL(" * event.address_src : %.8x,",event.address_src );
2019	LABEL(" * event.address_good : %.8x,",event.address_good);
2020	LABEL(" * event.take : %.8x,",event.take );
2021
2022	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2023	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2024	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2025	if (event.take_good)
2026	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2027
2028	event.address_src = 0;
2029	event.take = 0;
2030	event.address_dest = 0;
2031	}
2032
2033	SC_START(1);
2034	} while (not have_transaction);
2035
2036	in_BRANCH_EVENT_ACK [port]->write(0);
2037	}
2038	}
2039
2040	{
2041	LABEL("EVENT_STATE");
2042
2043	SC_START(1);
2044	in_EVENT_VAL [context]->write(1);
2045	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2046
2047	SC_START(1);
2048	in_EVENT_VAL [context]->write(0);
2049	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2050	}
2051
2052	{
2053	LABEL("UPDATE - upt (before event)");
2054
2055	uint32_t port = 0;
2056
2057	LABEL(" * port : %d",port);
2058	LABEL(" * size : %d",upt.size());
2059	std::list<request_t>::iterator it_upt = upt.begin();
2060
2061	for (uint32_t i=0; i<upt.size(); i++)
2062	{
2063	bool have_transaction = false;
2064
2065	do
2066	{
2067	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2068
2069	// if (_param->_have_port_depth)
2070	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2071	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2072
2073	SC_START(0);
2074
2075	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2076
2077	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2078	{
2079	LABEL("UPDATE [%d] - Transaction accepted",port);
2080	have_transaction = true;
2081
2082	if (_param->_have_port_context_id)
2083	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2084	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2085	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2086	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2087	if (update_btb(it_upt->condition))
2088	{
2089	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2090	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2091	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2092	}
2093	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2094
2095	if (update_dir(it_upt->condition))
2096	if (_param->_have_port_history)
2097	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2098	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2099	if (update_ras(it_upt->condition))
2100	{
2101	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2102	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2103	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2104	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2105	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2106	}
2107
2108	++ it_upt;
2109	}
2110
2111	SC_START(1);
2112	} while (not have_transaction);
2113
2114	in_UPDATE_ACK [port]->write(0);
2115	// if (_param->_have_port_depth)
2116	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2117	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2118	}
2119	}
2120	upt.clear();
2121
2122	// Wait Garbage Collector
2123	{
2124	LABEL("GARBAGE COLLECTOR");
2125	LABEL(" * upt bottom : %d",upt_bottom [context]);
2126	LABEL(" * upt top : %d",upt_top [context]);
2127
2128	upt_top [context] = (upt_top_event [context]);
2129	upt_bottom [context] = (upt_top [context]);
2130
2131	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2132	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2133	{
2134	SC_START(1);
2135	}
2136
2137	}
2138	}
2139
2140	//---------------------------------------------------------------------
2141	//---------------------------------------------------------------------
2142	// COMMIT MISS : with RAS in UPFT and UPT
2143	//---------------------------------------------------------------------
2144	//---------------------------------------------------------------------
2145	if (test5)
2146	{
2147	uint32_t context = rand() % _param->_nb_context;
2148	uint32_t have_ufpt_ras = false;
2149	uint32_t have_upt_ras = false;
2150
2151	{
2152	LABEL("PREDICT - fill the queue");
2153	uint32_t port = rand() % _param->_nb_inst_predict;
2154
2155	LABEL(" * context : %d",context);
2156	LABEL(" * port : %d",port);
2157
2158	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2159	{
2160	request_t request;
2161	request.context = context;
2162	request.address_src = rand();
2163	request.address_dest = rand();
2164
2165	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
2166	BRANCH_CONDITION_FLAG_SET;
2167
2168	request.take = 1;
2169	request.take_good = 1;
2170	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2171	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2172	request.is_accurate = true ;
2173	request.miss_ifetch = false;
2174	request.miss_decod = false;
2175	request.miss_commit = false;
2176	request.history = i;
2177	request.ras_address = rand();
2178	request.ras_index = rand()%_param->_size_ras_index[context];
2179	request.ufpt_ptr = ufpt_top [context];
2180	// request.upt_ptr;
2181
2182	bool have_transaction = false;
2183	do
2184	{
2185	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2186	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2187	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2188	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2189	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2190	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2191	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2192	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2193	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2194	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2195
2196	if (_param->_have_port_depth)
2197	{
2198	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2199	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2200	}
2201	SC_START(0); // fct melay
2202
2203	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2204	port,
2205	in_PREDICT_VAL [port]->read(),
2206	out_PREDICT_ACK [port]->read(),
2207	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2208
2209	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2210	{
2211	LABEL("PREDICT [%d] - Transaction accepted",port);
2212	have_transaction = true;
2213
2214	if (_param->_have_port_depth)
2215	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2216
2217	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2218	}
2219
2220	SC_START(1); // transition
2221
2222	} while (not have_transaction);
2223
2224	ufpt.push_back(request); // to update
2225
2226	in_PREDICT_VAL [port]->write(0);
2227
2228	if (_param->_have_port_depth)
2229	{
2230	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2231	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2232	}
2233	}
2234	}
2235
2236	{
2237	LABEL("DECOD");
2238	uint32_t port = rand() % _param->_nb_inst_decod;
2239
2240	LABEL(" * context : %d",context);
2241	LABEL(" * port : %d",port);
2242
2243	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2244	{
2245	request_t request = ufpt.front();
2246
2247	bool have_transaction = false;
2248	do
2249	{
2250	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
2251	in_DECOD_CONTEXT_ID [port]->write(request.context );
2252	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
2253	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2254	in_DECOD_BTB_CONDITION [port]->write(request.condition );
2255	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
2256	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
2257	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
2258	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
2259	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
2260	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
2261	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
2262
2263	have_upt_ras \|= (update_ras(request.condition));
2264
2265	SC_START(0); // fct melay
2266
2267	LABEL("DECOD [%d] %d - %d",
2268	port,
2269	in_DECOD_VAL [port]->read(),
2270	out_DECOD_ACK [port]->read());
2271
2272	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
2273	{
2274	LABEL("DECOD [%d] - Transaction accepted",port);
2275	have_transaction = true;
2276
2277	request.upt_ptr = upt_top [context];
2278	upt.push_back(request);
2279	ufpt.pop_front();
2280
2281	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
2282	}
2283
2284	SC_START(1); // transition
2285
2286	} while (not have_transaction);
2287
2288	in_DECOD_VAL [port]->write(0);
2289
2290	if (_param->_have_port_depth)
2291	{
2292	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2293	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2294	}
2295	}
2296	}
2297
2298	{
2299	LABEL("PREDICT - fill the queue");
2300	uint32_t port = rand() % _param->_nb_inst_predict;
2301
2302	LABEL(" * context : %d",context);
2303	LABEL(" * port : %d",port);
2304
2305	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2306	{
2307	request_t request;
2308	request.context = context;
2309	request.address_src = rand();
2310	request.address_dest = rand();
2311	request.address_good = request.address_dest;
2312	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
2313	BRANCH_CONDITION_FLAG_SET;
2314
2315	have_ufpt_ras \|= (update_ras(request.condition));
2316
2317	request.take = 1;
2318	request.take_good = 1;
2319	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2320	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2321	request.is_accurate = true ;
2322	request.miss_ifetch = false;
2323	request.miss_decod = false;
2324	request.miss_commit = true;
2325	request.history = i;
2326	request.ras_address = rand();
2327	request.ras_index = rand()%_param->_size_ras_index[context];
2328	request.ufpt_ptr = ufpt_top [context];
2329	// request.upt_ptr;
2330
2331	bool have_transaction = false;
2332	do
2333	{
2334	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2335	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2336	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2337	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2338	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2339	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2340	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2341	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2342	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2343	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2344
2345	if (_param->_have_port_depth)
2346	{
2347	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2348	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2349	}
2350	SC_START(0); // fct melay
2351
2352	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2353	port,
2354	in_PREDICT_VAL [port]->read(),
2355	out_PREDICT_ACK [port]->read(),
2356	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2357
2358	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2359	{
2360	LABEL("PREDICT [%d] - Transaction accepted",port);
2361	have_transaction = true;
2362
2363	if (_param->_have_port_depth)
2364	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2365
2366	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2367	}
2368
2369	SC_START(1); // transition
2370
2371	} while (not have_transaction);
2372
2373	ufpt.push_back(request); // to update
2374
2375	in_PREDICT_VAL [port]->write(0);
2376
2377	if (_param->_have_port_depth)
2378	{
2379	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2380	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2381	}
2382	}
2383	}
2384
2385	uint32_t nb_branch_before_event = 0;
2386	{
2387	// middle
2388	std::list<request_t>::iterator it_event = upt.begin();
2389	for (uint32_t i=0; i < (upt.size()>>1); ++i)
2390	{
2391	nb_branch_before_event ++;
2392	it_event ++;
2393	}
2394	for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it)
2395	it->miss_commit = true;
2396
2397	bool have_transaction = false;
2398
2399	do
2400	{
2401	PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event);
2402	PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION);
2403	PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr);
2404
2405	SC_START(0);
2406
2407	if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context]))
2408	{
2409	LABEL("EVENT [%d] - Transaction accepted",context);
2410
2411	have_transaction = true;
2412	}
2413
2414	SC_START(1);
2415	}
2416	while (not have_transaction);
2417	PORT_WRITE(in_EVENT_VAL [context],0);
2418
2419	upt_top_event [it_event->context] = upt_top [it_event->context];
2420	upt_top [it_event->context] = it_event->upt_ptr;
2421	}
2422
2423	{
2424	LABEL("BRANCH_COMPLETE - Hit ifetch");
2425
2426	uint32_t port = rand() % _param->_nb_inst_branch_complete;
2427
2428	LABEL(" * port : %d",port);
2429
2430	std::list<request_t>::iterator it_upt = upt.begin();
2431
2432	for (uint32_t i=0; i<nb_branch_before_event; ++i)
2433	{
2434	bool have_transaction = false;
2435
2436	do
2437	{
2438	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
2439	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
2440	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
2441	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
2442	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
2443
2444	if (_param->_have_port_depth)
2445	{
2446	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2447	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2448	}
2449	SC_START(0);
2450
2451	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
2452
2453	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
2454	{
2455	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
2456	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
2457	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
2458	LABEL(" * CONDITION : %d" ,it_upt->condition );
2459	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
2460	LABEL(" * FLAG : %d" ,it_upt->flag );
2461	LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence );
2462
2463	have_transaction = true;
2464
2465	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
2466	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
2467	it_upt->take_good = it_upt->take;
2468	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
2469	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2470
2471	it_upt++;
2472	}
2473
2474	SC_START(1);
2475
2476	} while (not have_transaction);
2477
2478	in_BRANCH_COMPLETE_VAL [port]->write(0);
2479
2480	if (_param->_have_port_depth)
2481	{
2482	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2483	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2484	}
2485	}
2486	}
2487
2488	if (have_ufpt_ras)
2489	{
2490	LABEL("UPDATE - Update UPFT");
2491
2492	uint32_t port = 0;
2493
2494	LABEL(" * port : %d",port);
2495	std::list<request_t>::iterator it_ufpt = ufpt.end();
2496	-- it_ufpt;
2497
2498	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2499	{
2500	bool have_transaction = false;
2501
2502	do
2503	{
2504	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2505
2506	// if (_param->_have_port_depth)
2507	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2508	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2509
2510	SC_START(0);
2511
2512	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2513
2514	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2515	{
2516	LABEL("UPDATE [%d] - Transaction accepted",port);
2517	have_transaction = true;
2518
2519	if (_param->_have_port_context_id)
2520	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
2521	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
2522	it_ufpt->miss_decod or
2523	it_ufpt->miss_commit ));
2524	// if (update_btb(it_ufpt->condition) or
2525	// update_dir(it_ufpt->condition))
2526	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
2527	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
2528	// if (update_btb(it_ufpt->condition))
2529	// {
2530	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
2531	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
2532	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
2533	// }
2534	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
2535
2536	// if (update_dir(it_ufpt->condition))
2537	// if (_param->_have_port_history)
2538	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
2539	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
2540	if (update_ras(it_ufpt->condition))
2541	{
2542	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2543	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
2544	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
2545	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
2546	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
2547	}
2548	}
2549
2550	SC_START(1);
2551	} while (not have_transaction);
2552
2553	-- it_ufpt;
2554
2555
2556	in_UPDATE_ACK [port]->write(0);
2557	// if (_param->_have_port_depth)
2558	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2559	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2560	}
2561	}
2562	ufpt.clear();
2563
2564	{
2565	LABEL("UPDATE - upt (after event)");
2566
2567	uint32_t port = 0;
2568
2569	LABEL(" * port : %d",port);
2570
2571	std::list<request_t>::iterator it_upt = upt.end();
2572
2573	// for (uint32_t i=0; i<upt.size(); i++)
2574
2575	uint32_t size = upt.size();
2576
2577	LABEL(" * size : %d",size);
2578	LABEL(" * nb_branch_before_event : %d",nb_branch_before_event);
2579
2580	for (uint32_t i=nb_branch_before_event; i<size; ++i)
2581	{
2582	--it_upt;
2583
2584	bool have_transaction = false;
2585
2586	if (need_update(it_upt->condition))
2587	do
2588	{
2589	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2590
2591	// if (_param->_have_port_depth)
2592	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2593	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2594
2595	SC_START(0);
2596
2597	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2598
2599	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2600	{
2601	LABEL("UPDATE [%d] - Transaction accepted",port);
2602	LABEL(" * address_src : %.8x",it_upt->address_src);
2603	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
2604
2605	have_transaction = true;
2606
2607	bool btb_val = ((update_btb(it_upt->condition)));
2608	bool dir_val = (update_dir(it_upt->condition) and
2609	not (it_upt->miss_ifetch or it_upt->miss_decod));
2610	bool ras_val = update_ras(it_upt->condition);
2611
2612	if (_param->_have_port_context_id)
2613	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2614	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2615	// TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
2616
2617	// if (btb_val)
2618	// {
2619	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2620	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2621	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2622	// }
2623	// TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
2624
2625	// if (dir_val)
2626	// {
2627	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2628	// if (_param->_have_port_history)
2629	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2630	// }
2631	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
2632
2633	if (ras_val)
2634	{
2635	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2636	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2637	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2638	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2639	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2640	}
2641	// -- it_upt;
2642	}
2643
2644	SC_START(1);
2645	} while (not have_transaction);
2646
2647	upt.pop_back();
2648	in_UPDATE_ACK [port]->write(0);
2649	// if (_param->_have_port_depth)
2650	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2651	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2652	}
2653	}
2654
2655	/*
2656	{
2657	LABEL("BRANCH_EVENT - have miss decod");
2658
2659	uint32_t port = context;
2660
2661	{
2662	bool have_transaction = false;
2663
2664	do
2665	{
2666	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2667
2668	SC_START(0);
2669
2670	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2671
2672	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2673	{
2674	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2675	have_transaction = true;
2676
2677	LABEL(" * event.address_src : %.8x,",event.address_src );
2678	LABEL(" * event.address_good : %.8x,",event.address_good);
2679	LABEL(" * event.take : %.8x,",event.take );
2680
2681	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2682	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2683	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2684	if (event.take_good)
2685	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2686
2687	event.address_src = 0;
2688	event.take = 0;
2689	event.address_dest = 0;
2690	}
2691
2692	SC_START(1);
2693	} while (not have_transaction);
2694
2695	in_BRANCH_EVENT_ACK [port]->write(0);
2696	}
2697	}
2698
2699	{
2700	LABEL("EVENT_STATE");
2701
2702	SC_START(1);
2703	in_EVENT_VAL [context]->write(1);
2704	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2705
2706	SC_START(1);
2707	in_EVENT_VAL [context]->write(0);
2708	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2709	}
2710	*/
2711
2712	{
2713	LABEL("UPDATE - upt (before event)");
2714
2715	uint32_t port = 0;
2716
2717	LABEL(" * port : %d",port);
2718	LABEL(" * size : %d",upt.size());
2719	std::list<request_t>::iterator it_upt = upt.begin();
2720
2721	for (uint32_t i=0; i<upt.size(); i++)
2722	{
2723	bool have_transaction = false;
2724
2725	do
2726	{
2727	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2728
2729	// if (_param->_have_port_depth)
2730	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2731	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2732
2733	SC_START(0);
2734
2735	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2736
2737	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2738	{
2739	LABEL("UPDATE [%d] - Transaction accepted",port);
2740	have_transaction = true;
2741
2742	if (_param->_have_port_context_id)
2743	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2744	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2745	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2746	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2747	if (update_btb(it_upt->condition))
2748	{
2749	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2750	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2751	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2752	}
2753	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2754
2755	if (update_dir(it_upt->condition))
2756	if (_param->_have_port_history)
2757	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2758	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2759	if (update_ras(it_upt->condition))
2760	{
2761	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2762	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2763	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2764	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2765	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2766	}
2767
2768	++ it_upt;
2769	}
2770
2771	SC_START(1);
2772	} while (not have_transaction);
2773
2774	in_UPDATE_ACK [port]->write(0);
2775	// if (_param->_have_port_depth)
2776	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2777	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2778	}
2779	}
2780
2781	upt.clear();
2782
2783	// Wait Garbage Collector
2784	{
2785	LABEL("GARBAGE COLLECTOR");
2786	LABEL(" * upt bottom : %d",upt_bottom [context]);
2787	LABEL(" * upt top : %d",upt_top [context]);
2788
2789	upt_top [context] = (upt_top_event [context]);
2790	upt_bottom [context] = (upt_top [context]);
2791
2792	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2793	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2794	{
2795	SC_START(1);
2796	}
2797	}
2798	}
2799
2800	}// ITERATION
2801
2802	/********************************************************
2803	* Simulation - End
2804	********************************************************/
2805
2806	TEST_OK ("End of Simulation");
2807	delete _time;
2808
2809	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2810
2811	delete in_CLOCK;
2812	delete in_NRESET;
2813
2814	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2815	delete [] in_PREDICT_VAL ;
2816	delete [] out_PREDICT_ACK ;
2817	delete [] in_PREDICT_CONTEXT_ID ;
2818	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2819	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2820	delete [] in_PREDICT_BTB_CONDITION ;
2821	delete [] in_PREDICT_BTB_LAST_TAKE ;
2822	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2823	delete [] in_PREDICT_DIR_HISTORY ;
2824	delete [] in_PREDICT_RAS_ADDRESS ;
2825	delete [] in_PREDICT_RAS_INDEX ;
2826	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2827
2828	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2829	delete [] in_DECOD_VAL ;
2830	delete [] out_DECOD_ACK ;
2831	delete [] in_DECOD_CONTEXT_ID ;
2832	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2833	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2834	delete [] in_DECOD_BTB_CONDITION ;
2835	delete [] in_DECOD_BTB_LAST_TAKE ;
2836	delete [] in_DECOD_RAS_ADDRESS ;
2837	delete [] in_DECOD_RAS_INDEX ;
2838	delete [] in_DECOD_MISS_DECOD ;
2839	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2840	//delete [] out_DECOD_DEPTH ;
2841	delete [] in_DECOD_IS_ACCURATE ;
2842	delete [] out_DECOD_CAN_CONTINUE ;
2843
2844	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2845	delete [] in_BRANCH_COMPLETE_VAL ;
2846	delete [] out_BRANCH_COMPLETE_ACK ;
2847	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2848	delete [] in_BRANCH_COMPLETE_DEPTH ;
2849	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2850	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2851	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2852	// delete [] out_BRANCH_COMPLETE_TAKE ;
2853	// delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2854	// delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2855
2856	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2857	delete [] out_BRANCH_EVENT_VAL ;
2858	delete [] in_BRANCH_EVENT_ACK ;
2859	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2860	delete [] out_BRANCH_EVENT_DEPTH ;
2861	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2862	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2863	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2864	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2865
2866	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2867	delete [] out_UPDATE_VAL ;
2868	delete [] in_UPDATE_ACK ;
2869	delete [] out_UPDATE_CONTEXT_ID ;
2870	delete [] out_UPDATE_MISS_PREDICTION ;
2871	delete [] out_UPDATE_DIRECTION_GOOD ;
2872	delete [] out_UPDATE_BTB_VAL ;
2873	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2874	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2875	delete [] out_UPDATE_BTB_CONDITION ;
2876	delete [] out_UPDATE_DIR_VAL ;
2877	delete [] out_UPDATE_DIR_HISTORY ;
2878	delete [] out_UPDATE_RAS_VAL ;
2879	delete [] out_UPDATE_RAS_FLUSH ;
2880	delete [] out_UPDATE_RAS_PUSH ;
2881	delete [] out_UPDATE_RAS_ADDRESS ;
2882	delete [] out_UPDATE_RAS_INDEX ;
2883	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2884
2885	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2886	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2887	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2888	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2889
2890	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2891	delete [] out_DEPTH_VAL;
2892	delete [] out_DEPTH_CURRENT;
2893	delete [] out_DEPTH_MIN;
2894	delete [] out_DEPTH_MAX;
2895	delete [] out_DEPTH_FULL;
2896
2897	#endif
2898
2899	delete _Update_Prediction_Table;
2900	#ifdef STATISTICS
2901	delete _parameters_statistics;
2902	#endif
2903	}

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