Ignore:
Timestamp:
Feb 27, 2009, 7:37:40 PM (15 years ago)
Author:
rosiere
Message:

1) Decod_queue : multi implementation (one_fifo, multi_fifo)
2) Issue_queue : multi implementation (in_order, out_of_order)
3) Direction : Add Meta predictor
4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative)
5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction
6) UPT : Fix bug in multi event
7) Prediction_glue : in read_stack case, insert in UPT pc_next
8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp

    r110 r111  
    108108  ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE    ," in_BRANCH_COMPLETE_NO_SEQUENCE    ",Tcontrol_t         ,_param->_nb_inst_branch_complete);
    109109  ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t         ,_param->_nb_inst_branch_complete);
    110   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE           ,"out_BRANCH_COMPLETE_TAKE           ",Tcontrol_t         ,_param->_nb_inst_branch_complete);
    111   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC    ,"out_BRANCH_COMPLETE_ADDRESS_SRC    ",Taddress_t         ,_param->_nb_inst_branch_complete);
    112   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST   ,"out_BRANCH_COMPLETE_ADDRESS_DEST   ",Taddress_t         ,_param->_nb_inst_branch_complete);
     110//   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE           ,"out_BRANCH_COMPLETE_TAKE           ",Tcontrol_t         ,_param->_nb_inst_branch_complete);
     111//   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC    ,"out_BRANCH_COMPLETE_ADDRESS_SRC    ",Taddress_t         ,_param->_nb_inst_branch_complete);
     112//   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST   ,"out_BRANCH_COMPLETE_ADDRESS_DEST   ",Taddress_t         ,_param->_nb_inst_branch_complete);
    113113
    114114  ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL            ,"out_BRANCH_EVENT_VAL            ",Tcontrol_t         ,_param->_nb_context);
    … …  
    202202  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE    ,_param->_nb_inst_branch_complete);
    203203  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
    204   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE           ,_param->_nb_inst_branch_complete);
    205   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC    ,_param->_nb_inst_branch_complete);
    206   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST   ,_param->_nb_inst_branch_complete);
     204//   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE           ,_param->_nb_inst_branch_complete);
     205//   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC    ,_param->_nb_inst_branch_complete);
     206//   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST   ,_param->_nb_inst_branch_complete);
    207207
    208208  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL            ,_param->_nb_context);
    … …  
    519519                     
    520520                      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
    521                       TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
    522                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
    523                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
     521//                    TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
     522//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
     523//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
    524524
    525525                      it_upt ++;
    … …  
    832832                     
    833833                      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
    834                       TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
    835                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
    836                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
     834//                    TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
     835//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
     836//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
    837837
    838838                      it_upt ++;
    … …  
    12001200                     
    12011201                      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
    1202                       TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
    1203                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
    1204                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
     1202//                    TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
     1203//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
     1204//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
    12051205
    12061206                      it_upt ++;
    … …  
    17451745                     
    17461746                      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
    1747                       TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_event->take_good   );
    1748                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_event->address_src );
    1749                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_event->address_good);
     1747//                    TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_event->take_good   );
     1748//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_event->address_src );
     1749//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_event->address_good);
    17501750
    17511751                      upt_top_event [it_event->context] = upt_top [it_event->context];
    … …  
    18091809                     
    18101810                      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
    1811                       TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take        );
     1811//                    TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take        );
    18121812                      it_upt->take_good = it_upt->take;
    1813                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
    1814                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_dest);
     1813//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
     1814//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_dest);
    18151815
    18161816                      it_upt++;
    … …  
    24642464                     
    24652465                      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
    2466                       TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take        );
     2466//                    TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take        );
    24672467                      it_upt->take_good = it_upt->take;
    2468                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
    2469                       TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_dest);
     2468//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
     2469//                    TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_dest);
    24702470
    24712471                      it_upt++;
    … …  
    28502850  delete []  in_BRANCH_COMPLETE_NO_SEQUENCE    ;
    28512851  delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
    2852   delete [] out_BRANCH_COMPLETE_TAKE           ;
    2853   delete [] out_BRANCH_COMPLETE_ADDRESS_SRC    ;
    2854   delete [] out_BRANCH_COMPLETE_ADDRESS_DEST   ;
     2852//   delete [] out_BRANCH_COMPLETE_TAKE           ;
     2853//   delete [] out_BRANCH_COMPLETE_ADDRESS_SRC    ;
     2854//   delete [] out_BRANCH_COMPLETE_ADDRESS_DEST   ;
    28552855
    28562856  // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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