Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
Property svn:keywords set to `Id`
File size: 141.2 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101	ALLOC1_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,"out_DECOD_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
102
103	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
111	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
112	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
113
114	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
115	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
116	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
118	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
121	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
122
123	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,"out_UPDATE_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
139	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
140
141	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
142	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
144	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
145
146	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
147	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
148	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
149	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
150	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
151
152	/********************************************************
153	* Instanciation
154	********************************************************/
155
156	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
157
158	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
159	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
160
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
162	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
163	if (_param->_have_port_context_id)
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
169	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
170	if (_param->_have_port_history)
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
173	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
174	if (_param->_have_port_depth)
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
178	if (_param->_have_port_context_id)
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
187	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
188	if (_param->_have_port_depth)
189	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
190	//if (_param->_have_port_depth)
191	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod);
194
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
196	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
197	if (_param->_have_port_context_id)
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
199	if (_param->_have_port_depth)
200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
204	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
205	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
206	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
207
208	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
209	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
210	//if (_param->_have_port_context_id)
211	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
212	if (_param->_have_port_depth)
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
214	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
215	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
218
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
221	if (_param->_have_port_context_id)
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
227	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
231	if (_param->_have_port_history)
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
238	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
239	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
241	if (_param->_have_port_depth)
242	{
243	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
244	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
247	}
248	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
249	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
250
251	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
252
253	Time * _time = new Time();
254
255	/********************************************************
256	* Simulation - Begin
257	********************************************************/
258
259	// Initialisation
260
261	const uint32_t seed = 0;
262	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
263
264	srand(seed);
265
266	const int32_t percent_transaction_predict = 75;
267	const int32_t percent_transaction_decod = 75;
268	const int32_t percent_transaction_branch_complete = 75;
269	const int32_t percent_transaction_update = 75;
270	const int32_t percent_transaction_branch_event = 75;
271	const int32_t percent_transaction_event = 75;
272
273	const bool test1 = true;
274	const bool test2 = true;
275	const bool test3 = true;
276	const bool test4 = true;
277	const bool test5 = true;
278
279	std::list<request_t> ufpt;
280	std::list<request_t> upt;
281	request_t event;
282
283	SC_START(0);
284	LABEL("Initialisation");
285
286	LABEL("Reset");
287	in_NRESET->write(0);
288	SC_START(5);
289	in_NRESET->write(1);
290
291	Tdepth_t ufpt_bottom [_param->_nb_context];
292	Tdepth_t ufpt_top [_param->_nb_context];
293
294	Tdepth_t upt_bottom [_param->_nb_context];
295	Tdepth_t upt_top [_param->_nb_context];
296	Tdepth_t upt_top_event[_param->_nb_context];
297
298	for (uint32_t i=0; i<_param->_nb_context; ++i)
299	{
300	ufpt_bottom [i] = 0;
301	ufpt_top [i] = 0;
302	upt_bottom [i] = 0;
303	upt_top [i] = 0;
304	upt_top_event[i] = 0;
305	}
306
307	for (uint32_t i=0; i<_param->_nb_context; ++i)
308	{
309	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
310	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
311	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
312	}
313
314	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
315	{
316	LABEL("Iteration %d",iteration);
317
318	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
319	in_PREDICT_VAL [i]->write(0);
320	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
321	in_DECOD_VAL [i]->write(0);
322	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
323	in_BRANCH_COMPLETE_VAL [i]->write(0);
324	for (uint32_t i=0; i<_param->_nb_context; ++i)
325	in_BRANCH_EVENT_ACK [i]->write(0);
326	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
327	in_UPDATE_ACK [i]->write(0);
328	for (uint32_t i=0; i<_param->_nb_context; ++i)
329	in_EVENT_VAL [i]->write(0);
330
331	//---------------------------------------------------------------------
332	//---------------------------------------------------------------------
333	// COMMON CASE
334	//---------------------------------------------------------------------
335	//---------------------------------------------------------------------
336	if (test1)
337	{
338	uint32_t context = rand() % _param->_nb_context;
339
340	{
341	LABEL("PREDICT - fill the queue");
342	uint32_t port = rand() % _param->_nb_inst_predict;
343
344	LABEL(" * context : %d",context);
345	LABEL(" * port : %d",port);
346
347	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
348	{
349	request_t request;
350	request.context = context;
351	request.address_src = 0xdeadbeef+i;
352	request.address_dest = 0x21071981+i;
353	request.address_good = request.address_dest;
354	request.condition = BRANCH_CONDITION_FLAG_SET;
355	request.take = 1;
356	request.take_good = 1;
357	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
358	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
359	request.is_accurate = true;
360	request.miss_ifetch = false;
361	request.miss_decod = false;
362	request.miss_commit = false;
363	request.history = i;
364	request.ras_address = 0xdeaddead+i;
365	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
366	request.ufpt_ptr = ufpt_top [context];
367	// request.upt_ptr;
368
369	bool have_transaction = false;
370	do
371	{
372	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
373	in_PREDICT_CONTEXT_ID [port]->write(request.context );
374	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
375	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
376	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
377	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
378	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
379	in_PREDICT_DIR_HISTORY [port]->write(request.history );
380	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
381	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
382
383	if (_param->_have_port_depth)
384	{
385	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
386	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
387	}
388	SC_START(0); // fct melay
389
390	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
391	port,
392	in_PREDICT_VAL [port]->read(),
393	out_PREDICT_ACK [port]->read(),
394	in_PREDICT_BTB_IS_ACCURATE [port]->read());
395
396	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
397	{
398	LABEL("PREDICT [%d] - Transaction accepted",port);
399	have_transaction = true;
400
401	if (_param->_have_port_depth)
402	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
403
404	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
405	}
406
407	SC_START(1); // transition
408
409	} while (not have_transaction);
410
411	ufpt.push_back(request);
412
413	in_PREDICT_VAL [port]->write(0);
414
415	if (_param->_have_port_depth)
416	{
417	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
418	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
419	}
420	}
421	}
422
423	{
424	LABEL("DECOD");
425	uint32_t port = rand() % _param->_nb_inst_decod;
426
427	LABEL(" * context : %d",context);
428	LABEL(" * port : %d",port);
429
430	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
431	{
432	request_t request = ufpt.front();
433
434	bool have_transaction = false;
435	do
436	{
437	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
438	in_DECOD_CONTEXT_ID [port]->write(request.context );
439	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
440	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
441	in_DECOD_BTB_CONDITION [port]->write(request.condition );
442	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
443	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
444	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
445	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
446	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
447	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
448	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
449
450	SC_START(0); // fct melay
451
452	LABEL("DECOD [%d] %d - %d",
453	port,
454	in_PREDICT_VAL [port]->read(),
455	out_PREDICT_ACK [port]->read());
456
457	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
458	{
459	LABEL("DECOD [%d] - Transaction accepted",port);
460	have_transaction = true;
461
462	request.upt_ptr = upt_top [context];
463	upt.push_back(request);
464	ufpt.pop_front();
465
466	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
467	}
468
469	SC_START(1); // transition
470
471	} while (not have_transaction);
472
473	in_DECOD_VAL [port]->write(0);
474
475	if (_param->_have_port_depth)
476	{
477	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
478	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
479	}
480	}
481	}
482
483	{
484	LABEL("BRANCH_COMPLETE - hit ifetch");
485
486	uint32_t port = rand() % _param->_nb_inst_branch_complete;
487
488	LABEL(" * port : %d",port);
489
490	std::list<request_t>::iterator it_upt = upt.begin();
491
492	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
493	for (uint32_t i=0; i<upt.size(); i++)
494	{
495	bool have_transaction = false;
496
497	do
498	{
499	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
500	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
501	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
502	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
503	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
504
505	if (_param->_have_port_depth)
506	{
507	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
508	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
509	}
510
511	SC_START(0);
512
513	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
514
515	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
516	{
517	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
518	have_transaction = true;
519
520	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
521	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
522	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
523	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
524
525	it_upt ++;
526	}
527
528	SC_START(1);
529	} while (not have_transaction);
530
531	in_BRANCH_COMPLETE_VAL [port]->write(0);
532
533	if (_param->_have_port_depth)
534	{
535	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
536	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
537	}
538	}
539	}
540
541	{
542	LABEL("UPDATE - hit ifetch");
543
544	uint32_t port = 0;
545
546	LABEL(" * port : %d",port);
547	std::list<request_t>::iterator it_upt = upt.begin();
548
549	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
550	for (uint32_t i=0; i<upt.size(); i++)
551	{
552	bool have_transaction = false;
553
554	do
555	{
556	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
557
558	// if (_param->_have_port_depth)
559	// {
560	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
561	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
562	// }
563
564	SC_START(0);
565
566	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
567
568	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
569	{
570	LABEL("UPDATE [%d] - Transaction accepted",port);
571	have_transaction = true;
572
573	if (_param->_have_port_context_id)
574	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
575	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
576	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
577	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
578	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
579	if (update_btb(it_upt->condition))
580	{
581	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
582	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
583	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
584	}
585	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
586	if (update_dir(it_upt->condition))
587	if (_param->_have_port_history)
588	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
589	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
590	if (update_ras(it_upt->condition))
591	{
592	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
593	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
594	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
595	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
596	}
597	++ it_upt;
598	}
599
600	SC_START(1);
601	} while (not have_transaction);
602
603	in_UPDATE_ACK [port]->write(0);
604	// if (_param->_have_port_depth)
605	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
606	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
607	}
608	upt.clear();
609	}
610
611	// Wait Garbage Collector
612	{
613	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
614	// upt_top [context] = (upt_top [context]);
615
616	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
617	(upt_top [context] != out_DEPTH_MAX [context]->read()))
618	SC_START(1);
619
620	}
621	}
622
623	//---------------------------------------------------------------------
624	//---------------------------------------------------------------------
625	// DECOD MISS : no RAS in ifetch
626	//---------------------------------------------------------------------
627	//---------------------------------------------------------------------
628	if (test2)
629	{
630	uint32_t context = rand() % _param->_nb_context;
631
632	{
633	LABEL("PREDICT - fill the queue");
634	uint32_t port = rand() % _param->_nb_inst_predict;
635
636	LABEL(" * context : %d",context);
637	LABEL(" * port : %d",port);
638
639	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
640	{
641	request_t request;
642	request.context = context;
643	request.address_src = 0xdeadbeef+i;
644	request.address_dest = 0x21071981+i;
645	request.address_good = request.address_dest;
646	request.condition = BRANCH_CONDITION_FLAG_SET;
647	request.take = 1;
648	request.take_good = 1;
649	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
650	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
651	request.is_accurate = true;
652	request.miss_ifetch = false;
653	request.miss_decod = false;
654	request.miss_commit = false;
655	request.history = i;
656	request.ras_address = 0xdeaddead+i;
657	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
658	request.ufpt_ptr = ufpt_top [context];
659	// request.upt_ptr;
660
661	bool have_transaction = false;
662	do
663	{
664	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
665	in_PREDICT_CONTEXT_ID [port]->write(request.context );
666	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
667	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
668	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
669	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
670	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
671	in_PREDICT_DIR_HISTORY [port]->write(request.history );
672	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
673	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
674
675	if (_param->_have_port_depth)
676	{
677	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
678	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
679	}
680	SC_START(0); // fct melay
681
682	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
683	port,
684	in_PREDICT_VAL [port]->read(),
685	out_PREDICT_ACK [port]->read(),
686	in_PREDICT_BTB_IS_ACCURATE [port]->read());
687
688	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
689	{
690	LABEL("PREDICT [%d] - Transaction accepted",port);
691	have_transaction = true;
692
693	if (_param->_have_port_depth)
694	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
695
696	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
697	}
698
699	SC_START(1); // transition
700
701	} while (not have_transaction);
702
703	// ufpt.push_back(request);
704
705	in_PREDICT_VAL [port]->write(0);
706
707	if (_param->_have_port_depth)
708	{
709	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
710	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
711	}
712	}
713	}
714
715	{
716	LABEL("DECOD - Miss");
717	uint32_t port = rand() % _param->_nb_inst_decod;
718
719	LABEL(" * context : %d",context);
720	LABEL(" * port : %d",port);
721
722	request_t request;
723	request.context = context;
724	request.address_src = 0x14011959;
725	request.address_dest = 0x25071959; // after = not take
726	request.address_good = request.address_dest;
727	request.condition = BRANCH_CONDITION_FLAG_SET;
728	request.take = 0;
729	request.take_good = 0;
730	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
731	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
732	request.is_accurate = true;
733	request.miss_ifetch = false;
734	request.miss_decod = true ;
735	request.miss_commit = false;
736	request.history = 1;
737	request.ras_address = 0xbabababa;
738	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
739	request.ufpt_ptr = ufpt_top [context];
740	request.upt_ptr = upt_top [context];
741
742	event = request;
743
744	// for (uint32_t i=0; i<upt.size(); i++)
745	// just one
746	{
747	bool have_transaction = false;
748	do
749	{
750	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
751	in_DECOD_CONTEXT_ID [port]->write(request.context );
752	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
753	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
754	in_DECOD_BTB_CONDITION [port]->write(request.condition );
755	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
756	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
757	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
758	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
759	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
760	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
761	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
762
763	SC_START(0); // fct melay
764
765	LABEL("DECOD [%d] %d - %d",
766	port,
767	in_PREDICT_VAL [port]->read(),
768	out_PREDICT_ACK [port]->read());
769
770	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
771	{
772	LABEL("DECOD [%d] - Transaction accepted",port);
773	have_transaction = true;
774
775	request.upt_ptr = upt_top [context];
776	upt.push_back(request);
777	// ufpt.pop_front();
778
779	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
780	}
781
782	SC_START(1); // transition
783
784	} while (not have_transaction);
785
786	in_DECOD_VAL [port]->write(0);
787
788	if (_param->_have_port_depth)
789	{
790	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
791	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
792	}
793	}
794	}
795
796	{
797	LABEL("BRANCH_COMPLETE - hit ifetch");
798
799	uint32_t port = rand() % _param->_nb_inst_branch_complete;
800
801	LABEL(" * port : %d",port);
802
803	std::list<request_t>::iterator it_upt = upt.begin();
804
805	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
806	// for (uint32_t i=0; i<upt.size(); i++)
807	// just one
808	{
809	bool have_transaction = false;
810
811	do
812	{
813	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
814	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
815	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
816	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
817	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
818
819	if (_param->_have_port_depth)
820	{
821	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
822	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
823	}
824	SC_START(0);
825
826	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
827
828	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
829	{
830	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
831	have_transaction = true;
832
833	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
834	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
835	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
836	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
837
838	it_upt ++;
839	}
840
841	SC_START(1);
842	} while (not have_transaction);
843
844	in_BRANCH_COMPLETE_VAL [port]->write(0);
845
846	if (_param->_have_port_depth)
847	{
848	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
849	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
850	}
851	}
852	}
853
854	{
855	LABEL("UPDATE - hit ifetch");
856
857	uint32_t port = 0;
858
859	LABEL(" * port : %d",port);
860	std::list<request_t>::iterator it_upt = upt.begin();
861
862	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
863	// for (uint32_t i=0; i<upt.size(); i++)
864	// just one
865	{
866	bool have_transaction = false;
867
868	do
869	{
870	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
871
872	// if (_param->_have_port_depth)
873	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
874	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
875
876	SC_START(0);
877
878	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
879
880	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
881	{
882	LABEL("UPDATE [%d] - Transaction accepted",port);
883	have_transaction = true;
884
885	if (_param->_have_port_context_id)
886	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
887	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
888	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
889	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
890	if (update_btb(it_upt->condition))
891	{
892	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
893	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
894	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
895	}
896	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
897
898	if (update_dir(it_upt->condition))
899	if (_param->_have_port_history)
900	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
901	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
902	if (update_ras(it_upt->condition))
903	{
904	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
905	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
906	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
907	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
908	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
909	}
910	++ it_upt;
911	}
912
913	SC_START(1);
914	} while (not have_transaction);
915
916	in_UPDATE_ACK [port]->write(0);
917	// if (_param->_have_port_depth)
918	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
919	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
920	}
921	upt.clear();
922	}
923
924	{
925	LABEL("BRANCH_EVENT - have miss decod");
926
927	uint32_t port = context;
928
929	{
930	bool have_transaction = false;
931
932	do
933	{
934	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
935
936	SC_START(0);
937
938	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
939
940	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
941	{
942	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
943	have_transaction = true;
944
945	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
946	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
947	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
948	if (event.take)
949	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
950
951	event.address_src = 0;
952	event.take = 0;
953	event.address_dest = 0;
954	}
955
956	SC_START(1);
957	} while (not have_transaction);
958
959	in_BRANCH_EVENT_ACK [port]->write(0);
960	}
961	}
962
963	{
964	LABEL("EVENT_STATE");
965
966	SC_START(1);
967	in_EVENT_VAL [context]->write(1);
968	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
969
970	SC_START(1);
971	in_EVENT_VAL [context]->write(0);
972	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
973	}
974
975	// Wait Garbage Collector
976	{
977	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
978	// upt_top [context] = (upt_top [context]);
979
980	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
981	(upt_top [context] != out_DEPTH_MAX [context]->read()))
982	SC_START(1);
983
984	}
985	}
986
987	//---------------------------------------------------------------------
988	//---------------------------------------------------------------------
989	// DECOD MISS : with RAS in ifetch
990	//---------------------------------------------------------------------
991	//---------------------------------------------------------------------
992	if (test3)
993	{
994	uint32_t context = rand() % _param->_nb_context;
995	uint32_t have_ras = false;
996	{
997	LABEL("PREDICT - fill the queue");
998	uint32_t port = rand() % _param->_nb_inst_predict;
999
1000	LABEL(" * context : %d",context);
1001	LABEL(" * port : %d",port);
1002
1003	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1004	{
1005	request_t request;
1006	request.context = context;
1007	request.address_src = 0xdeadbeef+i;
1008	request.address_dest = 0x21071981+i;
1009	request.address_good = request.address_dest;
1010	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1011	BRANCH_CONDITION_FLAG_SET;
1012
1013	have_ras \|= (update_ras(request.condition));
1014
1015	request.take = 1;
1016	request.take_good = 1;
1017	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1018	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1019	request.is_accurate = true;
1020	request.miss_ifetch = false;
1021	request.miss_decod = true ;
1022	request.miss_commit = false;
1023	request.history = i;
1024	request.ras_address = 0x12344321+i;
1025	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
1026	request.ufpt_ptr = ufpt_top [context];
1027	// request.upt_ptr;
1028
1029	bool have_transaction = false;
1030	do
1031	{
1032	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1033	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1034	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1035	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1036	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1037	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1038	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1039	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1040	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1041	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1042
1043	if (_param->_have_port_depth)
1044	{
1045	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1046	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1047	}
1048	SC_START(0); // fct melay
1049
1050	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1051	port,
1052	in_PREDICT_VAL [port]->read(),
1053	out_PREDICT_ACK [port]->read(),
1054	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1055
1056	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1057	{
1058	LABEL("PREDICT [%d] - Transaction accepted",port);
1059	have_transaction = true;
1060
1061	if (_param->_have_port_depth)
1062	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1063
1064	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1065	}
1066
1067	SC_START(1); // transition
1068
1069	} while (not have_transaction);
1070
1071	ufpt.push_back(request); // to update
1072
1073	in_PREDICT_VAL [port]->write(0);
1074
1075	if (_param->_have_port_depth)
1076	{
1077	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1078	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1079	}
1080	}
1081	}
1082
1083	{
1084	LABEL("DECOD - Miss");
1085	uint32_t port = rand() % _param->_nb_inst_decod;
1086
1087	LABEL(" * context : %d",context);
1088	LABEL(" * port : %d",port);
1089
1090	request_t request;
1091	request.context = context;
1092	request.address_src = 0x14011959;
1093	request.address_dest = 0x25071959; // after = not take
1094	request.address_good = request.address_dest;
1095	request.condition = BRANCH_CONDITION_FLAG_SET;
1096	request.take = 0;
1097	request.take_good = 0;
1098	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1099	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1100	request.is_accurate = true;
1101	request.miss_ifetch = false;
1102	request.miss_decod = true ;
1103	request.miss_commit = false;
1104	request.history = 1;
1105	request.ras_address = 0xbabababa;
1106	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1107	request.ufpt_ptr = ufpt_top [context];
1108	request.upt_ptr = upt_top [context];
1109
1110	event = request;
1111
1112	// for (uint32_t i=0; i<upt.size(); i++)
1113	// just one
1114	{
1115	bool have_transaction = false;
1116	do
1117	{
1118	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1119	in_DECOD_CONTEXT_ID [port]->write(request.context );
1120	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1121	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1122	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1123	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1124	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1125	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1126	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1127	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1128	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1129	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1130
1131	SC_START(0); // fct melay
1132
1133	LABEL("DECOD [%d] %d - %d",
1134	port,
1135	in_PREDICT_VAL [port]->read(),
1136	out_PREDICT_ACK [port]->read());
1137
1138	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1139	{
1140	LABEL("DECOD [%d] - Transaction accepted",port);
1141	have_transaction = true;
1142
1143	request.upt_ptr = upt_top [context];
1144	upt.push_back(request);
1145	// ufpt.pop_front();
1146
1147	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1148	}
1149
1150	SC_START(1); // transition
1151
1152	} while (not have_transaction);
1153
1154	in_DECOD_VAL [port]->write(0);
1155
1156	if (_param->_have_port_depth)
1157	{
1158	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1159	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1160	}
1161	}
1162	}
1163
1164	{
1165	LABEL("BRANCH_COMPLETE - hit ifetch");
1166
1167	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1168
1169	LABEL(" * port : %d",port);
1170
1171	std::list<request_t>::iterator it_upt = upt.begin();
1172
1173	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1174	// for (uint32_t i=0; i<upt.size(); i++)
1175	// just one
1176	{
1177	bool have_transaction = false;
1178
1179	do
1180	{
1181	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1182	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1183	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1184	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1185	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1186
1187	if (_param->_have_port_depth)
1188	{
1189	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1190	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1191	}
1192	SC_START(0);
1193
1194	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1195
1196	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1197	{
1198	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1199	have_transaction = true;
1200
1201	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1202	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1203	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1204	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1205
1206	it_upt ++;
1207	}
1208
1209	SC_START(1);
1210	} while (not have_transaction);
1211
1212	in_BRANCH_COMPLETE_VAL [port]->write(0);
1213
1214	if (_param->_have_port_depth)
1215	{
1216	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1217	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1218	}
1219	}
1220	}
1221
1222	if (have_ras)
1223	{
1224	LABEL("UPDATE - Update UPFT");
1225
1226	uint32_t port = 0;
1227
1228	LABEL(" * port : %d",port);
1229	std::list<request_t>::iterator it_ufpt = ufpt.end();
1230	-- it_ufpt;
1231
1232	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1233	{
1234	bool have_transaction = false;
1235
1236	do
1237	{
1238	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1239
1240	// if (_param->_have_port_depth)
1241	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1242	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1243
1244	SC_START(0);
1245
1246	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1247
1248	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1249	{
1250	LABEL("UPDATE [%d] - Transaction accepted",port);
1251	have_transaction = true;
1252
1253	if (_param->_have_port_context_id)
1254	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1255	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1256	it_ufpt->miss_decod or
1257	it_ufpt->miss_commit ));
1258	// if (update_btb(it_ufpt->condition) or
1259	// update_dir(it_ufpt->condition))
1260	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1261	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1262	// if (update_btb(it_ufpt->condition))
1263	// {
1264	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1265	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1266	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1267	// }
1268	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1269
1270	// if (update_dir(it_ufpt->condition))
1271	// if (_param->_have_port_history)
1272	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1273	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1274	if (update_ras(it_ufpt->condition))
1275	{
1276	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1277	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1278	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1279	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1280	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1281	}
1282	}
1283
1284	SC_START(1);
1285	} while (not have_transaction);
1286
1287	-- it_ufpt;
1288
1289
1290	in_UPDATE_ACK [port]->write(0);
1291	// if (_param->_have_port_depth)
1292	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1293	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1294	}
1295	}
1296	ufpt.clear();
1297
1298	{
1299	LABEL("UPDATE - hit ifetch");
1300
1301	uint32_t port = 0;
1302
1303	LABEL(" * port : %d",port);
1304	std::list<request_t>::iterator it_upt = upt.begin();
1305
1306	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1307	// for (uint32_t i=0; i<upt.size(); i++)
1308	// just one
1309	{
1310	bool have_transaction = false;
1311
1312	do
1313	{
1314	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1315
1316	// if (_param->_have_port_depth)
1317	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1318	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1319
1320	SC_START(0);
1321
1322	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1323
1324	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1325	{
1326	LABEL("UPDATE [%d] - Transaction accepted",port);
1327	have_transaction = true;
1328
1329	if (_param->_have_port_context_id)
1330	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1331	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1332	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1333	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1334	if (update_btb(it_upt->condition))
1335	{
1336	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1337	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1338	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1339	}
1340	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1341
1342	if (update_dir(it_upt->condition))
1343	if (_param->_have_port_history)
1344	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1345	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1346	if (update_ras(it_upt->condition))
1347	{
1348	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1349	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1350	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1351	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1352	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1353	}
1354	++ it_upt;
1355	}
1356
1357	SC_START(1);
1358	} while (not have_transaction);
1359
1360	in_UPDATE_ACK [port]->write(0);
1361	// if (_param->_have_port_depth)
1362	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1363	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1364	}
1365	}
1366	upt.clear();
1367
1368	{
1369	LABEL("BRANCH_EVENT - have miss decod");
1370
1371	uint32_t port = context;
1372
1373	{
1374	bool have_transaction = false;
1375
1376	do
1377	{
1378	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1379
1380	SC_START(0);
1381
1382	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1383
1384	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1385	{
1386	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1387	have_transaction = true;
1388
1389	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1390	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1391	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1392	if (event.take)
1393	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1394
1395	event.address_src = 0;
1396	event.take = 0;
1397	event.address_dest = 0;
1398	}
1399
1400	SC_START(1);
1401	} while (not have_transaction);
1402
1403	in_BRANCH_EVENT_ACK [port]->write(0);
1404	}
1405	}
1406
1407	{
1408	LABEL("EVENT_STATE");
1409
1410	SC_START(1);
1411	in_EVENT_VAL [context]->write(1);
1412	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
1413
1414	SC_START(1);
1415	in_EVENT_VAL [context]->write(0);
1416	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1417	}
1418
1419	// Wait Garbage Collector
1420	{
1421	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1422	// upt_top [context] = (upt_top [context]);
1423
1424	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1425	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1426	SC_START(1);
1427	}
1428	}
1429
1430	//---------------------------------------------------------------------
1431	//---------------------------------------------------------------------
1432	// COMMIT MISS : with RAS in UPFT and UPT
1433	//---------------------------------------------------------------------
1434	//---------------------------------------------------------------------
1435	if (test4)
1436	{
1437	uint32_t context = rand() % _param->_nb_context;
1438	uint32_t have_ufpt_ras = false;
1439	uint32_t have_upt_ras = false;
1440	{
1441	LABEL("PREDICT - fill the queue");
1442	uint32_t port = rand() % _param->_nb_inst_predict;
1443
1444	LABEL(" * context : %d",context);
1445	LABEL(" * port : %d",port);
1446
1447	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1448	{
1449	request_t request;
1450	request.context = context;
1451	request.address_src = rand();
1452	request.address_dest = rand();
1453
1454	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
1455	BRANCH_CONDITION_FLAG_SET;
1456
1457	request.take = 1;
1458	request.take_good = 1;
1459	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1460	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1461	request.is_accurate = true ;
1462	request.miss_ifetch = false;
1463	request.miss_decod = false;
1464	request.miss_commit = false;
1465	request.history = i;
1466	request.ras_address = rand();
1467	request.ras_index = rand()%_param->_size_ras_index[context];
1468	request.ufpt_ptr = ufpt_top [context];
1469	// request.upt_ptr;
1470
1471	bool have_transaction = false;
1472	do
1473	{
1474	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1475	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1476	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1477	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1478	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1479	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1480	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1481	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1482	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1483	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1484
1485	if (_param->_have_port_depth)
1486	{
1487	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1488	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1489	}
1490	SC_START(0); // fct melay
1491
1492	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1493	port,
1494	in_PREDICT_VAL [port]->read(),
1495	out_PREDICT_ACK [port]->read(),
1496	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1497
1498	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1499	{
1500	LABEL("PREDICT [%d] - Transaction accepted",port);
1501	have_transaction = true;
1502
1503	if (_param->_have_port_depth)
1504	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1505
1506	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1507	}
1508
1509	SC_START(1); // transition
1510
1511	} while (not have_transaction);
1512
1513	ufpt.push_back(request); // to update
1514
1515	in_PREDICT_VAL [port]->write(0);
1516
1517	if (_param->_have_port_depth)
1518	{
1519	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1520	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1521	}
1522	}
1523	}
1524
1525	{
1526	LABEL("DECOD");
1527	uint32_t port = rand() % _param->_nb_inst_decod;
1528
1529	LABEL(" * context : %d",context);
1530	LABEL(" * port : %d",port);
1531
1532	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1533	{
1534	request_t request = ufpt.front();
1535
1536	bool have_transaction = false;
1537	do
1538	{
1539	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1540	in_DECOD_CONTEXT_ID [port]->write(request.context );
1541	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1542	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1543	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1544	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1545	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1546	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1547	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1548	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1549	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1550	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1551
1552	have_upt_ras \|= (update_ras(request.condition));
1553
1554	SC_START(0); // fct melay
1555
1556	LABEL("DECOD [%d] %d - %d",
1557	port,
1558	in_DECOD_VAL [port]->read(),
1559	out_DECOD_ACK [port]->read());
1560
1561	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1562	{
1563	LABEL("DECOD [%d] - Transaction accepted",port);
1564	have_transaction = true;
1565
1566	request.upt_ptr = upt_top [context];
1567	upt.push_back(request);
1568	ufpt.pop_front();
1569
1570	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1571	}
1572
1573	SC_START(1); // transition
1574
1575	} while (not have_transaction);
1576
1577	in_DECOD_VAL [port]->write(0);
1578
1579	if (_param->_have_port_depth)
1580	{
1581	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1582	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1583	}
1584	}
1585	}
1586
1587	{
1588	LABEL("PREDICT - fill the queue");
1589	uint32_t port = rand() % _param->_nb_inst_predict;
1590
1591	LABEL(" * context : %d",context);
1592	LABEL(" * port : %d",port);
1593
1594	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1595	{
1596	request_t request;
1597	request.context = context;
1598	request.address_src = rand();
1599	request.address_dest = rand();
1600	request.address_good = request.address_dest;
1601	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1602	BRANCH_CONDITION_FLAG_SET;
1603
1604	have_ufpt_ras \|= (update_ras(request.condition));
1605
1606	request.take = 1;
1607	request.take_good = 1;
1608	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1609	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1610	request.is_accurate = true ;
1611	request.miss_ifetch = false;
1612	request.miss_decod = false;
1613	request.miss_commit = true;
1614	request.history = i;
1615	request.ras_address = rand();
1616	request.ras_index = rand()%_param->_size_ras_index[context];
1617	request.ufpt_ptr = ufpt_top [context];
1618	// request.upt_ptr;
1619
1620	bool have_transaction = false;
1621	do
1622	{
1623	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1624	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1625	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1626	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1627	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1628	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1629	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1630	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1631	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1632	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1633
1634	if (_param->_have_port_depth)
1635	{
1636	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1637	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1638	}
1639	SC_START(0); // fct melay
1640
1641	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1642	port,
1643	in_PREDICT_VAL [port]->read(),
1644	out_PREDICT_ACK [port]->read(),
1645	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1646
1647	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1648	{
1649	LABEL("PREDICT [%d] - Transaction accepted",port);
1650	have_transaction = true;
1651
1652	if (_param->_have_port_depth)
1653	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1654
1655	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1656	}
1657
1658	SC_START(1); // transition
1659
1660	} while (not have_transaction);
1661
1662	ufpt.push_back(request); // to update
1663
1664	in_PREDICT_VAL [port]->write(0);
1665
1666	if (_param->_have_port_depth)
1667	{
1668	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1669	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1670	}
1671	}
1672	}
1673
1674	std::list<request_t>::iterator it_event;
1675	{
1676	LABEL("BRANCH_COMPLETE - Miss ifetch");
1677
1678	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1679
1680	LABEL(" * port : %d",port);
1681
1682	// middle
1683	it_event = upt.begin();
1684	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1685	it_event ++;
1686
1687	for (std::list<request_t>::iterator it_upt = it_event;
1688	it_upt != upt.end();
1689	++it_upt)
1690	it_upt->miss_commit = true;
1691
1692	if (update_ras(it_event->condition))
1693	{
1694	it_event->address_good = ~(it_event->address_dest);
1695	}
1696	else
1697	{
1698	it_event->address_good = it_event->address_dest;
1699	it_event->flag = not it_event->flag;
1700	it_event->no_sequence = not it_event->no_sequence;
1701	it_event->take_good = not it_event->take_good;
1702	}
1703
1704	event = *it_event;
1705
1706
1707	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1708	// for (uint32_t i=0; i<upt.size(); i++)
1709	// just one
1710	{
1711	bool have_transaction = false;
1712
1713	do
1714	{
1715	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1716	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1717	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1718	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1719	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1720
1721	if (_param->_have_port_depth)
1722	{
1723	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1724	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1725	}
1726
1727	SC_START(0);
1728
1729	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1730
1731	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1732	{
1733	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1734	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1735	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1736	LABEL(" * CONDITION : %d" ,it_event->condition );
1737	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1738	LABEL(" * FLAG : %d" ,it_event->flag );
1739	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1740
1741	have_transaction = true;
1742
1743	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1744	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1745	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1746	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1747
1748	upt_top_event [it_event->context] = upt_top [it_event->context];
1749	upt_top [it_event->context] = it_event->upt_ptr;
1750	}
1751
1752	SC_START(1);
1753	} while (not have_transaction);
1754
1755	in_BRANCH_COMPLETE_VAL [port]->write(0);
1756
1757	if (_param->_have_port_depth)
1758	{
1759	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1760	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1761	}
1762	}
1763	}
1764
1765	{
1766	LABEL("BRANCH_COMPLETE - Hit ifetch");
1767
1768	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1769
1770	LABEL(" * port : %d",port);
1771
1772	std::list<request_t>::iterator it_upt = upt.begin();
1773
1774	while (it_upt != it_event)
1775	{
1776	bool have_transaction = false;
1777
1778	do
1779	{
1780	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1781	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1782	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1783	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1784	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1785
1786	if (_param->_have_port_depth)
1787	{
1788	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1789	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1790	}
1791	SC_START(0);
1792
1793	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1794
1795	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1796	{
1797	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1798	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1799	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1800	LABEL(" * CONDITION : %d" ,it_upt->condition );
1801	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1802	LABEL(" * FLAG : %d" ,it_upt->flag );
1803	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1804
1805	have_transaction = true;
1806
1807	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1808	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1809	it_upt->take_good = it_upt->take;
1810	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1811	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1812
1813	it_upt++;
1814	}
1815
1816	SC_START(1);
1817	} while (not have_transaction);
1818
1819	in_BRANCH_COMPLETE_VAL [port]->write(0);
1820
1821	if (_param->_have_port_depth)
1822	{
1823	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1824	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1825	}
1826	}
1827	}
1828
1829	if (have_ufpt_ras)
1830	{
1831	LABEL("UPDATE - Update UPFT");
1832
1833	uint32_t port = 0;
1834
1835	LABEL(" * port : %d",port);
1836	std::list<request_t>::iterator it_ufpt = ufpt.end();
1837	-- it_ufpt;
1838
1839	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1840	{
1841	bool have_transaction = false;
1842
1843	do
1844	{
1845	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1846
1847	// if (_param->_have_port_depth)
1848	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1849	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1850
1851	SC_START(0);
1852
1853	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1854
1855	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1856	{
1857	LABEL("UPDATE [%d] - Transaction accepted",port);
1858	have_transaction = true;
1859
1860	if (_param->_have_port_context_id)
1861	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1862	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1863	it_ufpt->miss_decod or
1864	it_ufpt->miss_commit ));
1865	// if (update_btb(it_ufpt->condition) or
1866	// update_dir(it_ufpt->condition))
1867	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1868	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1869	// if (update_btb(it_ufpt->condition))
1870	// {
1871	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1872	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1873	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1874	// }
1875	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1876
1877	// if (update_dir(it_ufpt->condition))
1878	// if (_param->_have_port_history)
1879	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1880	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1881	if (update_ras(it_ufpt->condition))
1882	{
1883	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1884	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1885	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1886	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1887	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1888	}
1889	}
1890
1891	SC_START(1);
1892	} while (not have_transaction);
1893
1894	-- it_ufpt;
1895
1896
1897	in_UPDATE_ACK [port]->write(0);
1898	// if (_param->_have_port_depth)
1899	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1900	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1901	}
1902	}
1903	ufpt.clear();
1904
1905	{
1906	LABEL("UPDATE - upt (after event)");
1907
1908	uint32_t port = 0;
1909
1910	LABEL(" * port : %d",port);
1911	std::list<request_t>::iterator it_upt = upt.end();
1912
1913	// for (uint32_t i=0; i<upt.size(); i++)
1914	do
1915	{
1916	--it_upt;
1917
1918	bool have_transaction = false;
1919
1920	if (need_update(it_upt->condition))
1921	do
1922	{
1923	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1924
1925	// if (_param->_have_port_depth)
1926	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1927	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1928
1929	SC_START(0);
1930
1931	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1932
1933	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1934	{
1935	LABEL("UPDATE [%d] - Transaction accepted",port);
1936	LABEL(" * address_src : %.8x",it_upt->address_src);
1937	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1938
1939	have_transaction = true;
1940
1941	bool btb_val = ((it_upt == it_event) and
1942	(update_btb(it_upt->condition)));
1943	bool dir_val = ((it_upt == it_event) and
1944	update_dir(it_upt->condition) and
1945	not (it_upt->miss_ifetch or it_upt->miss_decod));
1946	bool ras_val = update_ras(it_upt->condition);
1947
1948	if (_param->_have_port_context_id)
1949	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1950	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1951	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1952
1953	if (btb_val)
1954	{
1955	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1956	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1957	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1958	}
1959	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1960
1961	if (dir_val)
1962	{
1963	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1964	if (_param->_have_port_history)
1965	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1966	}
1967	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1968
1969	if (ras_val)
1970	{
1971	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1972	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1973	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1974	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1975	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1976	}
1977
1978	// -- it_upt;
1979	}
1980
1981	SC_START(1);
1982	} while (not have_transaction);
1983
1984	upt.pop_back();
1985	in_UPDATE_ACK [port]->write(0);
1986	// if (_param->_have_port_depth)
1987	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1988	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1989	}
1990	while (it_upt != it_event);
1991
1992	}
1993
1994	{
1995	LABEL("BRANCH_EVENT - have miss decod");
1996
1997	uint32_t port = context;
1998
1999	{
2000	bool have_transaction = false;
2001
2002	do
2003	{
2004	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2005
2006	SC_START(0);
2007
2008	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2009
2010	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2011	{
2012	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2013	have_transaction = true;
2014
2015	LABEL(" * event.address_src : %.8x,",event.address_src );
2016	LABEL(" * event.address_good : %.8x,",event.address_good);
2017	LABEL(" * event.take : %.8x,",event.take );
2018
2019	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2020	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2021	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2022	if (event.take_good)
2023	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2024
2025	event.address_src = 0;
2026	event.take = 0;
2027	event.address_dest = 0;
2028	}
2029
2030	SC_START(1);
2031	} while (not have_transaction);
2032
2033	in_BRANCH_EVENT_ACK [port]->write(0);
2034	}
2035	}
2036
2037	{
2038	LABEL("EVENT_STATE");
2039
2040	SC_START(1);
2041	in_EVENT_VAL [context]->write(1);
2042	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2043
2044	SC_START(1);
2045	in_EVENT_VAL [context]->write(0);
2046	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2047	}
2048
2049	{
2050	LABEL("UPDATE - upt (before event)");
2051
2052	uint32_t port = 0;
2053
2054	LABEL(" * port : %d",port);
2055	LABEL(" * size : %d",upt.size());
2056	std::list<request_t>::iterator it_upt = upt.begin();
2057
2058	for (uint32_t i=0; i<upt.size(); i++)
2059	{
2060	bool have_transaction = false;
2061
2062	do
2063	{
2064	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2065
2066	// if (_param->_have_port_depth)
2067	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2068	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2069
2070	SC_START(0);
2071
2072	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2073
2074	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2075	{
2076	LABEL("UPDATE [%d] - Transaction accepted",port);
2077	have_transaction = true;
2078
2079	if (_param->_have_port_context_id)
2080	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2081	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2082	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2083	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2084	if (update_btb(it_upt->condition))
2085	{
2086	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2087	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2088	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2089	}
2090	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2091
2092	if (update_dir(it_upt->condition))
2093	if (_param->_have_port_history)
2094	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2095	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2096	if (update_ras(it_upt->condition))
2097	{
2098	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2099	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2100	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2101	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2102	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2103	}
2104
2105	++ it_upt;
2106	}
2107
2108	SC_START(1);
2109	} while (not have_transaction);
2110
2111	in_UPDATE_ACK [port]->write(0);
2112	// if (_param->_have_port_depth)
2113	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2114	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2115	}
2116	}
2117	upt.clear();
2118
2119	// Wait Garbage Collector
2120	{
2121	LABEL("GARBAGE COLLECTOR");
2122	LABEL(" * upt bottom : %d",upt_bottom [context]);
2123	LABEL(" * upt top : %d",upt_top [context]);
2124
2125	upt_top [context] = (upt_top_event [context]);
2126	upt_bottom [context] = (upt_top [context]);
2127
2128	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2129	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2130	{
2131	SC_START(1);
2132	}
2133
2134	}
2135	}
2136
2137	//---------------------------------------------------------------------
2138	//---------------------------------------------------------------------
2139	// COMMIT MISS : with RAS in UPFT and UPT
2140	//---------------------------------------------------------------------
2141	//---------------------------------------------------------------------
2142	if (test5)
2143	{
2144	uint32_t context = rand() % _param->_nb_context;
2145	uint32_t have_ufpt_ras = false;
2146	uint32_t have_upt_ras = false;
2147
2148	{
2149	LABEL("PREDICT - fill the queue");
2150	uint32_t port = rand() % _param->_nb_inst_predict;
2151
2152	LABEL(" * context : %d",context);
2153	LABEL(" * port : %d",port);
2154
2155	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2156	{
2157	request_t request;
2158	request.context = context;
2159	request.address_src = rand();
2160	request.address_dest = rand();
2161
2162	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
2163	BRANCH_CONDITION_FLAG_SET;
2164
2165	request.take = 1;
2166	request.take_good = 1;
2167	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2168	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2169	request.is_accurate = true ;
2170	request.miss_ifetch = false;
2171	request.miss_decod = false;
2172	request.miss_commit = false;
2173	request.history = i;
2174	request.ras_address = rand();
2175	request.ras_index = rand()%_param->_size_ras_index[context];
2176	request.ufpt_ptr = ufpt_top [context];
2177	// request.upt_ptr;
2178
2179	bool have_transaction = false;
2180	do
2181	{
2182	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2183	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2184	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2185	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2186	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2187	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2188	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2189	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2190	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2191	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2192
2193	if (_param->_have_port_depth)
2194	{
2195	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2196	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2197	}
2198	SC_START(0); // fct melay
2199
2200	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2201	port,
2202	in_PREDICT_VAL [port]->read(),
2203	out_PREDICT_ACK [port]->read(),
2204	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2205
2206	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2207	{
2208	LABEL("PREDICT [%d] - Transaction accepted",port);
2209	have_transaction = true;
2210
2211	if (_param->_have_port_depth)
2212	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2213
2214	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2215	}
2216
2217	SC_START(1); // transition
2218
2219	} while (not have_transaction);
2220
2221	ufpt.push_back(request); // to update
2222
2223	in_PREDICT_VAL [port]->write(0);
2224
2225	if (_param->_have_port_depth)
2226	{
2227	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2228	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2229	}
2230	}
2231	}
2232
2233	{
2234	LABEL("DECOD");
2235	uint32_t port = rand() % _param->_nb_inst_decod;
2236
2237	LABEL(" * context : %d",context);
2238	LABEL(" * port : %d",port);
2239
2240	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2241	{
2242	request_t request = ufpt.front();
2243
2244	bool have_transaction = false;
2245	do
2246	{
2247	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
2248	in_DECOD_CONTEXT_ID [port]->write(request.context );
2249	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
2250	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2251	in_DECOD_BTB_CONDITION [port]->write(request.condition );
2252	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
2253	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
2254	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
2255	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
2256	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
2257	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
2258	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
2259
2260	have_upt_ras \|= (update_ras(request.condition));
2261
2262	SC_START(0); // fct melay
2263
2264	LABEL("DECOD [%d] %d - %d",
2265	port,
2266	in_DECOD_VAL [port]->read(),
2267	out_DECOD_ACK [port]->read());
2268
2269	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
2270	{
2271	LABEL("DECOD [%d] - Transaction accepted",port);
2272	have_transaction = true;
2273
2274	request.upt_ptr = upt_top [context];
2275	upt.push_back(request);
2276	ufpt.pop_front();
2277
2278	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
2279	}
2280
2281	SC_START(1); // transition
2282
2283	} while (not have_transaction);
2284
2285	in_DECOD_VAL [port]->write(0);
2286
2287	if (_param->_have_port_depth)
2288	{
2289	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2290	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2291	}
2292	}
2293	}
2294
2295	{
2296	LABEL("PREDICT - fill the queue");
2297	uint32_t port = rand() % _param->_nb_inst_predict;
2298
2299	LABEL(" * context : %d",context);
2300	LABEL(" * port : %d",port);
2301
2302	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2303	{
2304	request_t request;
2305	request.context = context;
2306	request.address_src = rand();
2307	request.address_dest = rand();
2308	request.address_good = request.address_dest;
2309	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
2310	BRANCH_CONDITION_FLAG_SET;
2311
2312	have_ufpt_ras \|= (update_ras(request.condition));
2313
2314	request.take = 1;
2315	request.take_good = 1;
2316	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2317	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2318	request.is_accurate = true ;
2319	request.miss_ifetch = false;
2320	request.miss_decod = false;
2321	request.miss_commit = true;
2322	request.history = i;
2323	request.ras_address = rand();
2324	request.ras_index = rand()%_param->_size_ras_index[context];
2325	request.ufpt_ptr = ufpt_top [context];
2326	// request.upt_ptr;
2327
2328	bool have_transaction = false;
2329	do
2330	{
2331	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2332	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2333	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2334	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2335	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2336	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2337	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2338	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2339	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2340	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2341
2342	if (_param->_have_port_depth)
2343	{
2344	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2345	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2346	}
2347	SC_START(0); // fct melay
2348
2349	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2350	port,
2351	in_PREDICT_VAL [port]->read(),
2352	out_PREDICT_ACK [port]->read(),
2353	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2354
2355	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2356	{
2357	LABEL("PREDICT [%d] - Transaction accepted",port);
2358	have_transaction = true;
2359
2360	if (_param->_have_port_depth)
2361	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2362
2363	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2364	}
2365
2366	SC_START(1); // transition
2367
2368	} while (not have_transaction);
2369
2370	ufpt.push_back(request); // to update
2371
2372	in_PREDICT_VAL [port]->write(0);
2373
2374	if (_param->_have_port_depth)
2375	{
2376	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2377	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2378	}
2379	}
2380	}
2381
2382	uint32_t nb_branch_before_event = 0;
2383	{
2384	// middle
2385	std::list<request_t>::iterator it_event = upt.begin();
2386	for (uint32_t i=0; i < (upt.size()>>1); ++i)
2387	{
2388	nb_branch_before_event ++;
2389	it_event ++;
2390	}
2391	for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it)
2392	it->miss_commit = true;
2393
2394	bool have_transaction = false;
2395
2396	do
2397	{
2398	PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event);
2399	PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION);
2400	PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr);
2401
2402	SC_START(0);
2403
2404	if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context]))
2405	{
2406	LABEL("EVENT [%d] - Transaction accepted",context);
2407
2408	have_transaction = true;
2409	}
2410
2411	SC_START(1);
2412	}
2413	while (not have_transaction);
2414	PORT_WRITE(in_EVENT_VAL [context],0);
2415
2416	upt_top_event [it_event->context] = upt_top [it_event->context];
2417	upt_top [it_event->context] = it_event->upt_ptr;
2418	}
2419
2420	{
2421	LABEL("BRANCH_COMPLETE - Hit ifetch");
2422
2423	uint32_t port = rand() % _param->_nb_inst_branch_complete;
2424
2425	LABEL(" * port : %d",port);
2426
2427	std::list<request_t>::iterator it_upt = upt.begin();
2428
2429	for (uint32_t i=0; i<nb_branch_before_event; ++i)
2430	{
2431	bool have_transaction = false;
2432
2433	do
2434	{
2435	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
2436	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
2437	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
2438	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
2439	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
2440
2441	if (_param->_have_port_depth)
2442	{
2443	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2444	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2445	}
2446	SC_START(0);
2447
2448	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
2449
2450	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
2451	{
2452	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
2453	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
2454	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
2455	LABEL(" * CONDITION : %d" ,it_upt->condition );
2456	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
2457	LABEL(" * FLAG : %d" ,it_upt->flag );
2458	LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence );
2459
2460	have_transaction = true;
2461
2462	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
2463	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
2464	it_upt->take_good = it_upt->take;
2465	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
2466	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2467
2468	it_upt++;
2469	}
2470
2471	SC_START(1);
2472
2473	} while (not have_transaction);
2474
2475	in_BRANCH_COMPLETE_VAL [port]->write(0);
2476
2477	if (_param->_have_port_depth)
2478	{
2479	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2480	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2481	}
2482	}
2483	}
2484
2485	if (have_ufpt_ras)
2486	{
2487	LABEL("UPDATE - Update UPFT");
2488
2489	uint32_t port = 0;
2490
2491	LABEL(" * port : %d",port);
2492	std::list<request_t>::iterator it_ufpt = ufpt.end();
2493	-- it_ufpt;
2494
2495	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2496	{
2497	bool have_transaction = false;
2498
2499	do
2500	{
2501	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2502
2503	// if (_param->_have_port_depth)
2504	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2505	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2506
2507	SC_START(0);
2508
2509	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2510
2511	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2512	{
2513	LABEL("UPDATE [%d] - Transaction accepted",port);
2514	have_transaction = true;
2515
2516	if (_param->_have_port_context_id)
2517	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
2518	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
2519	it_ufpt->miss_decod or
2520	it_ufpt->miss_commit ));
2521	// if (update_btb(it_ufpt->condition) or
2522	// update_dir(it_ufpt->condition))
2523	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
2524	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
2525	// if (update_btb(it_ufpt->condition))
2526	// {
2527	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
2528	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
2529	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
2530	// }
2531	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
2532
2533	// if (update_dir(it_ufpt->condition))
2534	// if (_param->_have_port_history)
2535	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
2536	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
2537	if (update_ras(it_ufpt->condition))
2538	{
2539	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2540	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
2541	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
2542	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
2543	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
2544	}
2545	}
2546
2547	SC_START(1);
2548	} while (not have_transaction);
2549
2550	-- it_ufpt;
2551
2552
2553	in_UPDATE_ACK [port]->write(0);
2554	// if (_param->_have_port_depth)
2555	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2556	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2557	}
2558	}
2559	ufpt.clear();
2560
2561	{
2562	LABEL("UPDATE - upt (after event)");
2563
2564	uint32_t port = 0;
2565
2566	LABEL(" * port : %d",port);
2567
2568	std::list<request_t>::iterator it_upt = upt.end();
2569
2570	// for (uint32_t i=0; i<upt.size(); i++)
2571
2572	uint32_t size = upt.size();
2573
2574	LABEL(" * size : %d",size);
2575	LABEL(" * nb_branch_before_event : %d",nb_branch_before_event);
2576
2577	for (uint32_t i=nb_branch_before_event; i<size; ++i)
2578	{
2579	--it_upt;
2580
2581	bool have_transaction = false;
2582
2583	if (need_update(it_upt->condition))
2584	do
2585	{
2586	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2587
2588	// if (_param->_have_port_depth)
2589	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2590	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2591
2592	SC_START(0);
2593
2594	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2595
2596	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2597	{
2598	LABEL("UPDATE [%d] - Transaction accepted",port);
2599	LABEL(" * address_src : %.8x",it_upt->address_src);
2600	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
2601
2602	have_transaction = true;
2603
2604	bool btb_val = ((update_btb(it_upt->condition)));
2605	bool dir_val = (update_dir(it_upt->condition) and
2606	not (it_upt->miss_ifetch or it_upt->miss_decod));
2607	bool ras_val = update_ras(it_upt->condition);
2608
2609	if (_param->_have_port_context_id)
2610	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2611	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2612	// TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
2613
2614	// if (btb_val)
2615	// {
2616	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2617	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2618	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2619	// }
2620	// TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
2621
2622	// if (dir_val)
2623	// {
2624	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2625	// if (_param->_have_port_history)
2626	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2627	// }
2628	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
2629
2630	if (ras_val)
2631	{
2632	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2633	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2634	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2635	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2636	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2637	}
2638	// -- it_upt;
2639	}
2640
2641	SC_START(1);
2642	} while (not have_transaction);
2643
2644	upt.pop_back();
2645	in_UPDATE_ACK [port]->write(0);
2646	// if (_param->_have_port_depth)
2647	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2648	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2649	}
2650	}
2651
2652	/*
2653	{
2654	LABEL("BRANCH_EVENT - have miss decod");
2655
2656	uint32_t port = context;
2657
2658	{
2659	bool have_transaction = false;
2660
2661	do
2662	{
2663	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2664
2665	SC_START(0);
2666
2667	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2668
2669	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2670	{
2671	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2672	have_transaction = true;
2673
2674	LABEL(" * event.address_src : %.8x,",event.address_src );
2675	LABEL(" * event.address_good : %.8x,",event.address_good);
2676	LABEL(" * event.take : %.8x,",event.take );
2677
2678	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2679	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2680	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2681	if (event.take_good)
2682	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2683
2684	event.address_src = 0;
2685	event.take = 0;
2686	event.address_dest = 0;
2687	}
2688
2689	SC_START(1);
2690	} while (not have_transaction);
2691
2692	in_BRANCH_EVENT_ACK [port]->write(0);
2693	}
2694	}
2695
2696	{
2697	LABEL("EVENT_STATE");
2698
2699	SC_START(1);
2700	in_EVENT_VAL [context]->write(1);
2701	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2702
2703	SC_START(1);
2704	in_EVENT_VAL [context]->write(0);
2705	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2706	}
2707	*/
2708
2709	{
2710	LABEL("UPDATE - upt (before event)");
2711
2712	uint32_t port = 0;
2713
2714	LABEL(" * port : %d",port);
2715	LABEL(" * size : %d",upt.size());
2716	std::list<request_t>::iterator it_upt = upt.begin();
2717
2718	for (uint32_t i=0; i<upt.size(); i++)
2719	{
2720	bool have_transaction = false;
2721
2722	do
2723	{
2724	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2725
2726	// if (_param->_have_port_depth)
2727	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2728	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2729
2730	SC_START(0);
2731
2732	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2733
2734	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2735	{
2736	LABEL("UPDATE [%d] - Transaction accepted",port);
2737	have_transaction = true;
2738
2739	if (_param->_have_port_context_id)
2740	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2741	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2742	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2743	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2744	if (update_btb(it_upt->condition))
2745	{
2746	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2747	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2748	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2749	}
2750	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2751
2752	if (update_dir(it_upt->condition))
2753	if (_param->_have_port_history)
2754	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2755	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2756	if (update_ras(it_upt->condition))
2757	{
2758	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2759	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2760	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2761	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2762	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2763	}
2764
2765	++ it_upt;
2766	}
2767
2768	SC_START(1);
2769	} while (not have_transaction);
2770
2771	in_UPDATE_ACK [port]->write(0);
2772	// if (_param->_have_port_depth)
2773	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2774	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2775	}
2776	}
2777
2778	upt.clear();
2779
2780	// Wait Garbage Collector
2781	{
2782	LABEL("GARBAGE COLLECTOR");
2783	LABEL(" * upt bottom : %d",upt_bottom [context]);
2784	LABEL(" * upt top : %d",upt_top [context]);
2785
2786	upt_top [context] = (upt_top_event [context]);
2787	upt_bottom [context] = (upt_top [context]);
2788
2789	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2790	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2791	{
2792	SC_START(1);
2793	}
2794	}
2795	}
2796
2797	}// ITERATION
2798
2799	/********************************************************
2800	* Simulation - End
2801	********************************************************/
2802
2803	TEST_OK ("End of Simulation");
2804	delete _time;
2805
2806	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2807
2808	delete in_CLOCK;
2809	delete in_NRESET;
2810
2811	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2812	delete [] in_PREDICT_VAL ;
2813	delete [] out_PREDICT_ACK ;
2814	delete [] in_PREDICT_CONTEXT_ID ;
2815	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2816	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2817	delete [] in_PREDICT_BTB_CONDITION ;
2818	delete [] in_PREDICT_BTB_LAST_TAKE ;
2819	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2820	delete [] in_PREDICT_DIR_HISTORY ;
2821	delete [] in_PREDICT_RAS_ADDRESS ;
2822	delete [] in_PREDICT_RAS_INDEX ;
2823	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2824
2825	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2826	delete [] in_DECOD_VAL ;
2827	delete [] out_DECOD_ACK ;
2828	delete [] in_DECOD_CONTEXT_ID ;
2829	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2830	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2831	delete [] in_DECOD_BTB_CONDITION ;
2832	delete [] in_DECOD_BTB_LAST_TAKE ;
2833	delete [] in_DECOD_RAS_ADDRESS ;
2834	delete [] in_DECOD_RAS_INDEX ;
2835	delete [] in_DECOD_MISS_DECOD ;
2836	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2837	//delete [] out_DECOD_DEPTH ;
2838	delete [] in_DECOD_IS_ACCURATE ;
2839	delete [] out_DECOD_CAN_CONTINUE ;
2840
2841	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2842	delete [] in_BRANCH_COMPLETE_VAL ;
2843	delete [] out_BRANCH_COMPLETE_ACK ;
2844	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2845	delete [] in_BRANCH_COMPLETE_DEPTH ;
2846	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2847	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2848	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2849	// delete [] out_BRANCH_COMPLETE_TAKE ;
2850	// delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2851	// delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2852
2853	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2854	delete [] out_BRANCH_EVENT_VAL ;
2855	delete [] in_BRANCH_EVENT_ACK ;
2856	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2857	delete [] out_BRANCH_EVENT_DEPTH ;
2858	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2859	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2860	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2861	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2862
2863	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2864	delete [] out_UPDATE_VAL ;
2865	delete [] in_UPDATE_ACK ;
2866	delete [] out_UPDATE_CONTEXT_ID ;
2867	delete [] out_UPDATE_MISS_PREDICTION ;
2868	delete [] out_UPDATE_DIRECTION_GOOD ;
2869	delete [] out_UPDATE_PREDICTION_IFETCH ;
2870	delete [] out_UPDATE_BTB_VAL ;
2871	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2872	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2873	delete [] out_UPDATE_BTB_CONDITION ;
2874	delete [] out_UPDATE_DIR_VAL ;
2875	delete [] out_UPDATE_DIR_HISTORY ;
2876	delete [] out_UPDATE_RAS_VAL ;
2877	delete [] out_UPDATE_RAS_FLUSH ;
2878	delete [] out_UPDATE_RAS_PUSH ;
2879	delete [] out_UPDATE_RAS_ADDRESS ;
2880	delete [] out_UPDATE_RAS_INDEX ;
2881
2882	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2883	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2884	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2885	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2886
2887	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2888	delete [] out_DEPTH_VAL;
2889	delete [] out_DEPTH_CURRENT;
2890	delete [] out_DEPTH_MIN;
2891	delete [] out_DEPTH_MAX;
2892	delete [] out_DEPTH_FULL;
2893
2894	#endif
2895
2896	delete _Update_Prediction_Table;
2897	#ifdef STATISTICS
2898	delete _parameters_statistics;
2899	#endif
2900	}

Note: See TracBrowser for help on using the repository browser.

Download in other formats: