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test.cpp @ 119

Last change on this file since 119 was 119, checked in by rosiere, 15 years ago
1) Prediction unit : static prediction not blocking
Property svn:keywords set to `Id`
File size: 141.9 KB

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1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101	ALLOC1_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,"out_DECOD_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
102
103	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
111	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
112	// ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
113
114	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
115	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
116	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
118	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
121	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
122	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CAN_CONTINUE ,"out_BRANCH_EVENT_CAN_CONTINUE" ,Tcontrol_t ,_param->_nb_context);
123
124	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,"out_UPDATE_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
139	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
140	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
141
142	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
144	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
145	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
146
147	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
148	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
149	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
150	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
151	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
152
153	/********************************************************
154	* Instanciation
155	********************************************************/
156
157	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
158
159	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
160	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
161
162	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
164	if (_param->_have_port_context_id)
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
169	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
171	if (_param->_have_port_history)
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
173	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
175	if (_param->_have_port_depth)
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
177	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
179	if (_param->_have_port_context_id)
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
187	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
189	if (_param->_have_port_depth)
190	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
191	//if (_param->_have_port_depth)
192	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
194	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod);
195
196	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
198	if (_param->_have_port_context_id)
199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
200	if (_param->_have_port_depth)
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
204	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
205	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
206	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
207	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
208
209	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
211	//if (_param->_have_port_context_id)
212	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
213	if (_param->_have_port_depth)
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
215	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
218	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CAN_CONTINUE ,_param->_nb_context);
220
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
223	if (_param->_have_port_context_id)
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
227	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update);
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
233	if (_param->_have_port_history)
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
238	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
239	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
241	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
242	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
243	if (_param->_have_port_depth)
244	{
245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
247	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
248	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
249	}
250	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
251	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
252
253	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
254
255	Time * _time = new Time();
256
257	/********************************************************
258	* Simulation - Begin
259	********************************************************/
260
261	// Initialisation
262
263	const uint32_t seed = 0;
264	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
265
266	srand(seed);
267
268	const int32_t percent_transaction_predict = 75;
269	const int32_t percent_transaction_decod = 75;
270	const int32_t percent_transaction_branch_complete = 75;
271	const int32_t percent_transaction_update = 75;
272	const int32_t percent_transaction_branch_event = 75;
273	const int32_t percent_transaction_event = 75;
274
275	const bool test1 = true;
276	const bool test2 = true;
277	const bool test3 = true;
278	const bool test4 = true;
279	const bool test5 = true;
280
281	std::list<request_t> ufpt;
282	std::list<request_t> upt;
283	request_t event;
284
285	SC_START(0);
286	LABEL("Initialisation");
287
288	LABEL("Reset");
289	in_NRESET->write(0);
290	SC_START(5);
291	in_NRESET->write(1);
292
293	Tdepth_t ufpt_bottom [_param->_nb_context];
294	Tdepth_t ufpt_top [_param->_nb_context];
295
296	Tdepth_t upt_bottom [_param->_nb_context];
297	Tdepth_t upt_top [_param->_nb_context];
298	Tdepth_t upt_top_event[_param->_nb_context];
299
300	for (uint32_t i=0; i<_param->_nb_context; ++i)
301	{
302	ufpt_bottom [i] = 0;
303	ufpt_top [i] = 0;
304	upt_bottom [i] = 0;
305	upt_top [i] = 0;
306	upt_top_event[i] = 0;
307	}
308
309	for (uint32_t i=0; i<_param->_nb_context; ++i)
310	{
311	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
312	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
313	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
314	}
315
316	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
317	{
318	LABEL("Iteration %d",iteration);
319
320	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
321	in_PREDICT_VAL [i]->write(0);
322	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
323	in_DECOD_VAL [i]->write(0);
324	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
325	in_BRANCH_COMPLETE_VAL [i]->write(0);
326	for (uint32_t i=0; i<_param->_nb_context; ++i)
327	in_BRANCH_EVENT_ACK [i]->write(0);
328	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
329	in_UPDATE_ACK [i]->write(0);
330	for (uint32_t i=0; i<_param->_nb_context; ++i)
331	in_EVENT_VAL [i]->write(0);
332
333	//---------------------------------------------------------------------
334	//---------------------------------------------------------------------
335	// COMMON CASE
336	//---------------------------------------------------------------------
337	//---------------------------------------------------------------------
338	if (test1)
339	{
340	uint32_t context = rand() % _param->_nb_context;
341
342	{
343	LABEL("PREDICT - fill the queue");
344	uint32_t port = rand() % _param->_nb_inst_predict;
345
346	LABEL(" * context : %d",context);
347	LABEL(" * port : %d",port);
348
349	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
350	{
351	request_t request;
352	request.context = context;
353	request.address_src = 0xdeadbeef+i;
354	request.address_dest = 0x21071981+i;
355	request.address_good = request.address_dest;
356	request.condition = BRANCH_CONDITION_FLAG_SET;
357	request.take = 1;
358	request.take_good = 1;
359	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
360	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
361	request.is_accurate = true;
362	request.miss_ifetch = false;
363	request.miss_decod = false;
364	request.miss_commit = false;
365	request.history = i;
366	request.ras_address = 0xdeaddead+i;
367	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
368	request.ufpt_ptr = ufpt_top [context];
369	// request.upt_ptr;
370
371	bool have_transaction = false;
372	do
373	{
374	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
375	in_PREDICT_CONTEXT_ID [port]->write(request.context );
376	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
377	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
378	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
379	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
380	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
381	in_PREDICT_DIR_HISTORY [port]->write(request.history );
382	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
383	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
384
385	if (_param->_have_port_depth)
386	{
387	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
388	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
389	}
390	SC_START(0); // fct melay
391
392	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
393	port,
394	in_PREDICT_VAL [port]->read(),
395	out_PREDICT_ACK [port]->read(),
396	in_PREDICT_BTB_IS_ACCURATE [port]->read());
397
398	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
399	{
400	LABEL("PREDICT [%d] - Transaction accepted",port);
401	have_transaction = true;
402
403	if (_param->_have_port_depth)
404	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
405
406	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
407	}
408
409	SC_START(1); // transition
410
411	} while (not have_transaction);
412
413	ufpt.push_back(request);
414
415	in_PREDICT_VAL [port]->write(0);
416
417	if (_param->_have_port_depth)
418	{
419	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
420	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
421	}
422	}
423	}
424
425	{
426	LABEL("DECOD");
427	uint32_t port = rand() % _param->_nb_inst_decod;
428
429	LABEL(" * context : %d",context);
430	LABEL(" * port : %d",port);
431
432	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
433	{
434	request_t request = ufpt.front();
435
436	bool have_transaction = false;
437	do
438	{
439	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
440	in_DECOD_CONTEXT_ID [port]->write(request.context );
441	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
442	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
443	in_DECOD_BTB_CONDITION [port]->write(request.condition );
444	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
445	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
446	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
447	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
448	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
449	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
450	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
451
452	SC_START(0); // fct melay
453
454	LABEL("DECOD [%d] %d - %d",
455	port,
456	in_PREDICT_VAL [port]->read(),
457	out_PREDICT_ACK [port]->read());
458
459	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
460	{
461	LABEL("DECOD [%d] - Transaction accepted",port);
462	have_transaction = true;
463
464	request.upt_ptr = upt_top [context];
465	upt.push_back(request);
466	ufpt.pop_front();
467
468	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
469	}
470
471	SC_START(1); // transition
472
473	} while (not have_transaction);
474
475	in_DECOD_VAL [port]->write(0);
476
477	if (_param->_have_port_depth)
478	{
479	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
480	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
481	}
482	}
483	}
484
485	{
486	LABEL("BRANCH_COMPLETE - hit ifetch");
487
488	uint32_t port = rand() % _param->_nb_inst_branch_complete;
489
490	LABEL(" * port : %d",port);
491
492	std::list<request_t>::iterator it_upt = upt.begin();
493
494	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
495	for (uint32_t i=0; i<upt.size(); i++)
496	{
497	bool have_transaction = false;
498
499	do
500	{
501	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
502	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
503	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
504	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
505	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
506
507	if (_param->_have_port_depth)
508	{
509	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
510	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
511	}
512
513	SC_START(0);
514
515	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
516
517	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
518	{
519	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
520	have_transaction = true;
521
522	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
523	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
524	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
525	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
526
527	it_upt ++;
528	}
529
530	SC_START(1);
531	} while (not have_transaction);
532
533	in_BRANCH_COMPLETE_VAL [port]->write(0);
534
535	if (_param->_have_port_depth)
536	{
537	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
538	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
539	}
540	}
541	}
542
543	{
544	LABEL("UPDATE - hit ifetch");
545
546	uint32_t port = 0;
547
548	LABEL(" * port : %d",port);
549	std::list<request_t>::iterator it_upt = upt.begin();
550
551	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
552	for (uint32_t i=0; i<upt.size(); i++)
553	{
554	bool have_transaction = false;
555
556	do
557	{
558	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
559
560	// if (_param->_have_port_depth)
561	// {
562	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
563	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
564	// }
565
566	SC_START(0);
567
568	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
569
570	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
571	{
572	LABEL("UPDATE [%d] - Transaction accepted",port);
573	have_transaction = true;
574
575	if (_param->_have_port_context_id)
576	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
577	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
578	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
579	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
580	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
581	if (update_btb(it_upt->condition))
582	{
583	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
584	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
585	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
586	}
587	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
588	if (update_dir(it_upt->condition))
589	if (_param->_have_port_history)
590	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
591	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
592	if (update_ras(it_upt->condition))
593	{
594	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
595	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
596	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
597	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
598	}
599	++ it_upt;
600	}
601
602	SC_START(1);
603	} while (not have_transaction);
604
605	in_UPDATE_ACK [port]->write(0);
606	// if (_param->_have_port_depth)
607	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
608	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
609	}
610	upt.clear();
611	}
612
613	// Wait Garbage Collector
614	{
615	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
616	// upt_top [context] = (upt_top [context]);
617
618	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
619	(upt_top [context] != out_DEPTH_MAX [context]->read()))
620	SC_START(1);
621
622	}
623	}
624
625	//---------------------------------------------------------------------
626	//---------------------------------------------------------------------
627	// DECOD MISS : no RAS in ifetch
628	//---------------------------------------------------------------------
629	//---------------------------------------------------------------------
630	if (test2)
631	{
632	uint32_t context = rand() % _param->_nb_context;
633
634	{
635	LABEL("PREDICT - fill the queue");
636	uint32_t port = rand() % _param->_nb_inst_predict;
637
638	LABEL(" * context : %d",context);
639	LABEL(" * port : %d",port);
640
641	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
642	{
643	request_t request;
644	request.context = context;
645	request.address_src = 0xdeadbeef+i;
646	request.address_dest = 0x21071981+i;
647	request.address_good = request.address_dest;
648	request.condition = BRANCH_CONDITION_FLAG_SET;
649	request.take = 1;
650	request.take_good = 1;
651	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
652	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
653	request.is_accurate = true;
654	request.miss_ifetch = false;
655	request.miss_decod = false;
656	request.miss_commit = false;
657	request.history = i;
658	request.ras_address = 0xdeaddead+i;
659	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
660	request.ufpt_ptr = ufpt_top [context];
661	// request.upt_ptr;
662
663	bool have_transaction = false;
664	do
665	{
666	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
667	in_PREDICT_CONTEXT_ID [port]->write(request.context );
668	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
669	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
670	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
671	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
672	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
673	in_PREDICT_DIR_HISTORY [port]->write(request.history );
674	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
675	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
676
677	if (_param->_have_port_depth)
678	{
679	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
680	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
681	}
682	SC_START(0); // fct melay
683
684	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
685	port,
686	in_PREDICT_VAL [port]->read(),
687	out_PREDICT_ACK [port]->read(),
688	in_PREDICT_BTB_IS_ACCURATE [port]->read());
689
690	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
691	{
692	LABEL("PREDICT [%d] - Transaction accepted",port);
693	have_transaction = true;
694
695	if (_param->_have_port_depth)
696	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
697
698	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
699	}
700
701	SC_START(1); // transition
702
703	} while (not have_transaction);
704
705	// ufpt.push_back(request);
706
707	in_PREDICT_VAL [port]->write(0);
708
709	if (_param->_have_port_depth)
710	{
711	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
712	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
713	}
714	}
715	}
716
717	{
718	LABEL("DECOD - Miss");
719	uint32_t port = rand() % _param->_nb_inst_decod;
720
721	LABEL(" * context : %d",context);
722	LABEL(" * port : %d",port);
723
724	request_t request;
725	request.context = context;
726	request.address_src = 0x14011959;
727	request.address_dest = 0x25071959; // after = not take
728	request.address_good = request.address_dest;
729	request.condition = BRANCH_CONDITION_FLAG_SET;
730	request.take = 0;
731	request.take_good = 0;
732	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
733	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
734	request.is_accurate = true;
735	request.miss_ifetch = false;
736	request.miss_decod = true ;
737	request.miss_commit = false;
738	request.history = 1;
739	request.ras_address = 0xbabababa;
740	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
741	request.ufpt_ptr = ufpt_top [context];
742	request.upt_ptr = upt_top [context];
743
744	event = request;
745
746	// for (uint32_t i=0; i<upt.size(); i++)
747	// just one
748	{
749	bool have_transaction = false;
750	do
751	{
752	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
753	in_DECOD_CONTEXT_ID [port]->write(request.context );
754	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
755	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
756	in_DECOD_BTB_CONDITION [port]->write(request.condition );
757	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
758	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
759	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
760	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
761	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
762	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
763	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
764
765	SC_START(0); // fct melay
766
767	LABEL("DECOD [%d] %d - %d",
768	port,
769	in_PREDICT_VAL [port]->read(),
770	out_PREDICT_ACK [port]->read());
771
772	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
773	{
774	LABEL("DECOD [%d] - Transaction accepted",port);
775	have_transaction = true;
776
777	request.upt_ptr = upt_top [context];
778	upt.push_back(request);
779	// ufpt.pop_front();
780
781	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
782	}
783
784	SC_START(1); // transition
785
786	} while (not have_transaction);
787
788	in_DECOD_VAL [port]->write(0);
789
790	if (_param->_have_port_depth)
791	{
792	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
793	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
794	}
795	}
796	}
797
798	{
799	LABEL("BRANCH_COMPLETE - hit ifetch");
800
801	uint32_t port = rand() % _param->_nb_inst_branch_complete;
802
803	LABEL(" * port : %d",port);
804
805	std::list<request_t>::iterator it_upt = upt.begin();
806
807	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
808	// for (uint32_t i=0; i<upt.size(); i++)
809	// just one
810	{
811	bool have_transaction = false;
812
813	do
814	{
815	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
816	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
817	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
818	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
819	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
820
821	if (_param->_have_port_depth)
822	{
823	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
824	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
825	}
826	SC_START(0);
827
828	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
829
830	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
831	{
832	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
833	have_transaction = true;
834
835	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
836	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
837	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
838	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
839
840	it_upt ++;
841	}
842
843	SC_START(1);
844	} while (not have_transaction);
845
846	in_BRANCH_COMPLETE_VAL [port]->write(0);
847
848	if (_param->_have_port_depth)
849	{
850	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
851	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
852	}
853	}
854	}
855
856	{
857	LABEL("UPDATE - hit ifetch");
858
859	uint32_t port = 0;
860
861	LABEL(" * port : %d",port);
862	std::list<request_t>::iterator it_upt = upt.begin();
863
864	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
865	// for (uint32_t i=0; i<upt.size(); i++)
866	// just one
867	{
868	bool have_transaction = false;
869
870	do
871	{
872	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
873
874	// if (_param->_have_port_depth)
875	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
876	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
877
878	SC_START(0);
879
880	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
881
882	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
883	{
884	LABEL("UPDATE [%d] - Transaction accepted",port);
885	have_transaction = true;
886
887	if (_param->_have_port_context_id)
888	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
889	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
890	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
891	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
892	if (update_btb(it_upt->condition))
893	{
894	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
895	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
896	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
897	}
898	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
899
900	if (update_dir(it_upt->condition))
901	if (_param->_have_port_history)
902	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
903	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
904	if (update_ras(it_upt->condition))
905	{
906	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
907	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
908	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
909	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
910	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
911	}
912	++ it_upt;
913	}
914
915	SC_START(1);
916	} while (not have_transaction);
917
918	in_UPDATE_ACK [port]->write(0);
919	// if (_param->_have_port_depth)
920	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
921	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
922	}
923	upt.clear();
924	}
925
926	{
927	LABEL("BRANCH_EVENT - have miss decod");
928
929	uint32_t port = context;
930
931	{
932	bool have_transaction = false;
933
934	do
935	{
936	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
937
938	SC_START(0);
939
940	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
941
942	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
943	{
944	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
945	have_transaction = true;
946
947	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
948	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
949	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
950	if (event.take)
951	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
952	TEST(Taddress_t,out_BRANCH_EVENT_CAN_CONTINUE [port]->read(),not event.miss_commit);
953
954	event.address_src = 0;
955	event.take = 0;
956	event.address_dest = 0;
957	}
958
959	SC_START(1);
960	} while (not have_transaction);
961
962	in_BRANCH_EVENT_ACK [port]->write(0);
963	}
964	}
965
966	{
967	LABEL("EVENT_STATE");
968
969	SC_START(1);
970	in_EVENT_VAL [context]->write(1);
971	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
972
973	SC_START(1);
974	in_EVENT_VAL [context]->write(0);
975	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
976	}
977
978	// Wait Garbage Collector
979	{
980	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
981	// upt_top [context] = (upt_top [context]);
982
983	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
984	(upt_top [context] != out_DEPTH_MAX [context]->read()))
985	SC_START(1);
986
987	}
988	}
989
990	//---------------------------------------------------------------------
991	//---------------------------------------------------------------------
992	// DECOD MISS : with RAS in ifetch
993	//---------------------------------------------------------------------
994	//---------------------------------------------------------------------
995	if (test3)
996	{
997	uint32_t context = rand() % _param->_nb_context;
998	uint32_t have_ras = false;
999	{
1000	LABEL("PREDICT - fill the queue");
1001	uint32_t port = rand() % _param->_nb_inst_predict;
1002
1003	LABEL(" * context : %d",context);
1004	LABEL(" * port : %d",port);
1005
1006	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1007	{
1008	request_t request;
1009	request.context = context;
1010	request.address_src = 0xdeadbeef+i;
1011	request.address_dest = 0x21071981+i;
1012	request.address_good = request.address_dest;
1013	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1014	BRANCH_CONDITION_FLAG_SET;
1015
1016	have_ras \|= (update_ras(request.condition));
1017
1018	request.take = 1;
1019	request.take_good = 1;
1020	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1021	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1022	request.is_accurate = true;
1023	request.miss_ifetch = false;
1024	request.miss_decod = true ;
1025	request.miss_commit = false;
1026	request.history = i;
1027	request.ras_address = 0x12344321+i;
1028	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
1029	request.ufpt_ptr = ufpt_top [context];
1030	// request.upt_ptr;
1031
1032	bool have_transaction = false;
1033	do
1034	{
1035	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1036	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1037	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1038	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1039	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1040	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1041	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1042	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1043	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1044	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1045
1046	if (_param->_have_port_depth)
1047	{
1048	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1049	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1050	}
1051	SC_START(0); // fct melay
1052
1053	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1054	port,
1055	in_PREDICT_VAL [port]->read(),
1056	out_PREDICT_ACK [port]->read(),
1057	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1058
1059	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1060	{
1061	LABEL("PREDICT [%d] - Transaction accepted",port);
1062	have_transaction = true;
1063
1064	if (_param->_have_port_depth)
1065	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1066
1067	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1068	}
1069
1070	SC_START(1); // transition
1071
1072	} while (not have_transaction);
1073
1074	ufpt.push_back(request); // to update
1075
1076	in_PREDICT_VAL [port]->write(0);
1077
1078	if (_param->_have_port_depth)
1079	{
1080	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1081	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1082	}
1083	}
1084	}
1085
1086	{
1087	LABEL("DECOD - Miss");
1088	uint32_t port = rand() % _param->_nb_inst_decod;
1089
1090	LABEL(" * context : %d",context);
1091	LABEL(" * port : %d",port);
1092
1093	request_t request;
1094	request.context = context;
1095	request.address_src = 0x14011959;
1096	request.address_dest = 0x25071959; // after = not take
1097	request.address_good = request.address_dest;
1098	request.condition = BRANCH_CONDITION_FLAG_SET;
1099	request.take = 0;
1100	request.take_good = 0;
1101	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1102	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1103	request.is_accurate = true;
1104	request.miss_ifetch = false;
1105	request.miss_decod = true ;
1106	request.miss_commit = false;
1107	request.history = 1;
1108	request.ras_address = 0xbabababa;
1109	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1110	request.ufpt_ptr = ufpt_top [context];
1111	request.upt_ptr = upt_top [context];
1112
1113	event = request;
1114
1115	// for (uint32_t i=0; i<upt.size(); i++)
1116	// just one
1117	{
1118	bool have_transaction = false;
1119	do
1120	{
1121	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1122	in_DECOD_CONTEXT_ID [port]->write(request.context );
1123	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1124	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1125	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1126	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1127	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1128	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1129	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1130	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1131	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1132	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1133
1134	SC_START(0); // fct melay
1135
1136	LABEL("DECOD [%d] %d - %d",
1137	port,
1138	in_PREDICT_VAL [port]->read(),
1139	out_PREDICT_ACK [port]->read());
1140
1141	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1142	{
1143	LABEL("DECOD [%d] - Transaction accepted",port);
1144	have_transaction = true;
1145
1146	request.upt_ptr = upt_top [context];
1147	upt.push_back(request);
1148	// ufpt.pop_front();
1149
1150	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1151	}
1152
1153	SC_START(1); // transition
1154
1155	} while (not have_transaction);
1156
1157	in_DECOD_VAL [port]->write(0);
1158
1159	if (_param->_have_port_depth)
1160	{
1161	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1162	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1163	}
1164	}
1165	}
1166
1167	{
1168	LABEL("BRANCH_COMPLETE - hit ifetch");
1169
1170	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1171
1172	LABEL(" * port : %d",port);
1173
1174	std::list<request_t>::iterator it_upt = upt.begin();
1175
1176	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1177	// for (uint32_t i=0; i<upt.size(); i++)
1178	// just one
1179	{
1180	bool have_transaction = false;
1181
1182	do
1183	{
1184	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1185	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1186	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1187	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1188	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1189
1190	if (_param->_have_port_depth)
1191	{
1192	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1193	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1194	}
1195	SC_START(0);
1196
1197	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1198
1199	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1200	{
1201	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1202	have_transaction = true;
1203
1204	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1205	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1206	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1207	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1208
1209	it_upt ++;
1210	}
1211
1212	SC_START(1);
1213	} while (not have_transaction);
1214
1215	in_BRANCH_COMPLETE_VAL [port]->write(0);
1216
1217	if (_param->_have_port_depth)
1218	{
1219	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1220	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1221	}
1222	}
1223	}
1224
1225	if (have_ras)
1226	{
1227	LABEL("UPDATE - Update UPFT");
1228
1229	uint32_t port = 0;
1230
1231	LABEL(" * port : %d",port);
1232	std::list<request_t>::iterator it_ufpt = ufpt.end();
1233	-- it_ufpt;
1234
1235	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1236	{
1237	bool have_transaction = false;
1238
1239	do
1240	{
1241	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1242
1243	// if (_param->_have_port_depth)
1244	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1245	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1246
1247	SC_START(0);
1248
1249	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1250
1251	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1252	{
1253	LABEL("UPDATE [%d] - Transaction accepted",port);
1254	have_transaction = true;
1255
1256	if (_param->_have_port_context_id)
1257	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1258	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1259	it_ufpt->miss_decod or
1260	it_ufpt->miss_commit ));
1261	// if (update_btb(it_ufpt->condition) or
1262	// update_dir(it_ufpt->condition))
1263	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1264	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1265	// if (update_btb(it_ufpt->condition))
1266	// {
1267	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1268	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1269	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1270	// }
1271	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1272
1273	// if (update_dir(it_ufpt->condition))
1274	// if (_param->_have_port_history)
1275	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1276	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1277	if (update_ras(it_ufpt->condition))
1278	{
1279	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1280	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1281	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1282	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1283	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1284	}
1285	}
1286
1287	SC_START(1);
1288	} while (not have_transaction);
1289
1290	-- it_ufpt;
1291
1292
1293	in_UPDATE_ACK [port]->write(0);
1294	// if (_param->_have_port_depth)
1295	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1296	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1297	}
1298	}
1299	ufpt.clear();
1300
1301	{
1302	LABEL("UPDATE - hit ifetch");
1303
1304	uint32_t port = 0;
1305
1306	LABEL(" * port : %d",port);
1307	std::list<request_t>::iterator it_upt = upt.begin();
1308
1309	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1310	// for (uint32_t i=0; i<upt.size(); i++)
1311	// just one
1312	{
1313	bool have_transaction = false;
1314
1315	do
1316	{
1317	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1318
1319	// if (_param->_have_port_depth)
1320	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1321	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1322
1323	SC_START(0);
1324
1325	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1326
1327	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1328	{
1329	LABEL("UPDATE [%d] - Transaction accepted",port);
1330	have_transaction = true;
1331
1332	if (_param->_have_port_context_id)
1333	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1334	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1335	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1336	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1337	if (update_btb(it_upt->condition))
1338	{
1339	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1340	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1341	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1342	}
1343	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1344
1345	if (update_dir(it_upt->condition))
1346	if (_param->_have_port_history)
1347	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1348	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1349	if (update_ras(it_upt->condition))
1350	{
1351	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1352	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1353	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1354	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1355	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1356	}
1357	++ it_upt;
1358	}
1359
1360	SC_START(1);
1361	} while (not have_transaction);
1362
1363	in_UPDATE_ACK [port]->write(0);
1364	// if (_param->_have_port_depth)
1365	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1366	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1367	}
1368	}
1369	upt.clear();
1370
1371	{
1372	LABEL("BRANCH_EVENT - have miss decod");
1373
1374	uint32_t port = context;
1375
1376	{
1377	bool have_transaction = false;
1378
1379	do
1380	{
1381	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1382
1383	SC_START(0);
1384
1385	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1386
1387	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1388	{
1389	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1390	have_transaction = true;
1391
1392	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1393	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1394	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1395	if (event.take)
1396	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1397	TEST(Taddress_t,out_BRANCH_EVENT_CAN_CONTINUE [port]->read(),not event.miss_commit);
1398
1399	event.address_src = 0;
1400	event.take = 0;
1401	event.address_dest = 0;
1402	}
1403
1404	SC_START(1);
1405	} while (not have_transaction);
1406
1407	in_BRANCH_EVENT_ACK [port]->write(0);
1408	}
1409	}
1410
1411	{
1412	LABEL("EVENT_STATE");
1413
1414	SC_START(1);
1415	in_EVENT_VAL [context]->write(1);
1416	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
1417
1418	SC_START(1);
1419	in_EVENT_VAL [context]->write(0);
1420	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1421	}
1422
1423	// Wait Garbage Collector
1424	{
1425	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1426	// upt_top [context] = (upt_top [context]);
1427
1428	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1429	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1430	SC_START(1);
1431	}
1432	}
1433
1434	//---------------------------------------------------------------------
1435	//---------------------------------------------------------------------
1436	// COMMIT MISS : with RAS in UPFT and UPT
1437	//---------------------------------------------------------------------
1438	//---------------------------------------------------------------------
1439	if (test4)
1440	{
1441	uint32_t context = rand() % _param->_nb_context;
1442	uint32_t have_ufpt_ras = false;
1443	uint32_t have_upt_ras = false;
1444	{
1445	LABEL("PREDICT - fill the queue");
1446	uint32_t port = rand() % _param->_nb_inst_predict;
1447
1448	LABEL(" * context : %d",context);
1449	LABEL(" * port : %d",port);
1450
1451	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1452	{
1453	request_t request;
1454	request.context = context;
1455	request.address_src = rand();
1456	request.address_dest = rand();
1457
1458	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
1459	BRANCH_CONDITION_FLAG_SET;
1460
1461	request.take = 1;
1462	request.take_good = 1;
1463	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1464	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1465	request.is_accurate = true ;
1466	request.miss_ifetch = false;
1467	request.miss_decod = false;
1468	request.miss_commit = false;
1469	request.history = i;
1470	request.ras_address = rand();
1471	request.ras_index = rand()%_param->_size_ras_index[context];
1472	request.ufpt_ptr = ufpt_top [context];
1473	// request.upt_ptr;
1474
1475	bool have_transaction = false;
1476	do
1477	{
1478	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1479	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1480	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1481	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1482	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1483	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1484	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1485	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1486	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1487	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1488
1489	if (_param->_have_port_depth)
1490	{
1491	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1492	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1493	}
1494	SC_START(0); // fct melay
1495
1496	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1497	port,
1498	in_PREDICT_VAL [port]->read(),
1499	out_PREDICT_ACK [port]->read(),
1500	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1501
1502	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1503	{
1504	LABEL("PREDICT [%d] - Transaction accepted",port);
1505	have_transaction = true;
1506
1507	if (_param->_have_port_depth)
1508	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1509
1510	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1511	}
1512
1513	SC_START(1); // transition
1514
1515	} while (not have_transaction);
1516
1517	ufpt.push_back(request); // to update
1518
1519	in_PREDICT_VAL [port]->write(0);
1520
1521	if (_param->_have_port_depth)
1522	{
1523	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1524	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1525	}
1526	}
1527	}
1528
1529	{
1530	LABEL("DECOD");
1531	uint32_t port = rand() % _param->_nb_inst_decod;
1532
1533	LABEL(" * context : %d",context);
1534	LABEL(" * port : %d",port);
1535
1536	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1537	{
1538	request_t request = ufpt.front();
1539
1540	bool have_transaction = false;
1541	do
1542	{
1543	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1544	in_DECOD_CONTEXT_ID [port]->write(request.context );
1545	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1546	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1547	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1548	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1549	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1550	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1551	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1552	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1553	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1554	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1555
1556	have_upt_ras \|= (update_ras(request.condition));
1557
1558	SC_START(0); // fct melay
1559
1560	LABEL("DECOD [%d] %d - %d",
1561	port,
1562	in_DECOD_VAL [port]->read(),
1563	out_DECOD_ACK [port]->read());
1564
1565	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1566	{
1567	LABEL("DECOD [%d] - Transaction accepted",port);
1568	have_transaction = true;
1569
1570	request.upt_ptr = upt_top [context];
1571	upt.push_back(request);
1572	ufpt.pop_front();
1573
1574	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1575	}
1576
1577	SC_START(1); // transition
1578
1579	} while (not have_transaction);
1580
1581	in_DECOD_VAL [port]->write(0);
1582
1583	if (_param->_have_port_depth)
1584	{
1585	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1586	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1587	}
1588	}
1589	}
1590
1591	{
1592	LABEL("PREDICT - fill the queue");
1593	uint32_t port = rand() % _param->_nb_inst_predict;
1594
1595	LABEL(" * context : %d",context);
1596	LABEL(" * port : %d",port);
1597
1598	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1599	{
1600	request_t request;
1601	request.context = context;
1602	request.address_src = rand();
1603	request.address_dest = rand();
1604	request.address_good = request.address_dest;
1605	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1606	BRANCH_CONDITION_FLAG_SET;
1607
1608	have_ufpt_ras \|= (update_ras(request.condition));
1609
1610	request.take = 1;
1611	request.take_good = 1;
1612	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1613	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1614	request.is_accurate = true ;
1615	request.miss_ifetch = false;
1616	request.miss_decod = false;
1617	request.miss_commit = true;
1618	request.history = i;
1619	request.ras_address = rand();
1620	request.ras_index = rand()%_param->_size_ras_index[context];
1621	request.ufpt_ptr = ufpt_top [context];
1622	// request.upt_ptr;
1623
1624	bool have_transaction = false;
1625	do
1626	{
1627	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1628	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1629	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1630	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1631	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1632	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1633	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1634	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1635	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1636	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1637
1638	if (_param->_have_port_depth)
1639	{
1640	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1641	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1642	}
1643	SC_START(0); // fct melay
1644
1645	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1646	port,
1647	in_PREDICT_VAL [port]->read(),
1648	out_PREDICT_ACK [port]->read(),
1649	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1650
1651	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1652	{
1653	LABEL("PREDICT [%d] - Transaction accepted",port);
1654	have_transaction = true;
1655
1656	if (_param->_have_port_depth)
1657	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1658
1659	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1660	}
1661
1662	SC_START(1); // transition
1663
1664	} while (not have_transaction);
1665
1666	ufpt.push_back(request); // to update
1667
1668	in_PREDICT_VAL [port]->write(0);
1669
1670	if (_param->_have_port_depth)
1671	{
1672	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1673	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1674	}
1675	}
1676	}
1677
1678	std::list<request_t>::iterator it_event;
1679	{
1680	LABEL("BRANCH_COMPLETE - Miss ifetch");
1681
1682	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1683
1684	LABEL(" * port : %d",port);
1685
1686	// middle
1687	it_event = upt.begin();
1688	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1689	it_event ++;
1690
1691	for (std::list<request_t>::iterator it_upt = it_event;
1692	it_upt != upt.end();
1693	++it_upt)
1694	it_upt->miss_commit = true;
1695
1696	if (update_ras(it_event->condition))
1697	{
1698	it_event->address_good = ~(it_event->address_dest);
1699	}
1700	else
1701	{
1702	it_event->address_good = it_event->address_dest;
1703	it_event->flag = not it_event->flag;
1704	it_event->no_sequence = not it_event->no_sequence;
1705	it_event->take_good = not it_event->take_good;
1706	}
1707
1708	event = *it_event;
1709
1710
1711	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1712	// for (uint32_t i=0; i<upt.size(); i++)
1713	// just one
1714	{
1715	bool have_transaction = false;
1716
1717	do
1718	{
1719	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1720	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1721	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1722	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1723	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1724
1725	if (_param->_have_port_depth)
1726	{
1727	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1728	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1729	}
1730
1731	SC_START(0);
1732
1733	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1734
1735	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1736	{
1737	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1738	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1739	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1740	LABEL(" * CONDITION : %d" ,it_event->condition );
1741	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1742	LABEL(" * FLAG : %d" ,it_event->flag );
1743	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1744
1745	have_transaction = true;
1746
1747	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1748	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1749	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1750	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1751
1752	upt_top_event [it_event->context] = upt_top [it_event->context];
1753	upt_top [it_event->context] = it_event->upt_ptr;
1754	}
1755
1756	SC_START(1);
1757	} while (not have_transaction);
1758
1759	in_BRANCH_COMPLETE_VAL [port]->write(0);
1760
1761	if (_param->_have_port_depth)
1762	{
1763	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1764	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1765	}
1766	}
1767	}
1768
1769	{
1770	LABEL("BRANCH_COMPLETE - Hit ifetch");
1771
1772	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1773
1774	LABEL(" * port : %d",port);
1775
1776	std::list<request_t>::iterator it_upt = upt.begin();
1777
1778	while (it_upt != it_event)
1779	{
1780	bool have_transaction = false;
1781
1782	do
1783	{
1784	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1785	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1786	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1787	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1788	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1789
1790	if (_param->_have_port_depth)
1791	{
1792	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1793	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1794	}
1795	SC_START(0);
1796
1797	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1798
1799	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1800	{
1801	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1802	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1803	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1804	LABEL(" * CONDITION : %d" ,it_upt->condition );
1805	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1806	LABEL(" * FLAG : %d" ,it_upt->flag );
1807	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1808
1809	have_transaction = true;
1810
1811	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1812	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1813	it_upt->take_good = it_upt->take;
1814	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1815	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1816
1817	it_upt++;
1818	}
1819
1820	SC_START(1);
1821	} while (not have_transaction);
1822
1823	in_BRANCH_COMPLETE_VAL [port]->write(0);
1824
1825	if (_param->_have_port_depth)
1826	{
1827	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1828	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1829	}
1830	}
1831	}
1832
1833	if (have_ufpt_ras)
1834	{
1835	LABEL("UPDATE - Update UPFT");
1836
1837	uint32_t port = 0;
1838
1839	LABEL(" * port : %d",port);
1840	std::list<request_t>::iterator it_ufpt = ufpt.end();
1841	-- it_ufpt;
1842
1843	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1844	{
1845	bool have_transaction = false;
1846
1847	do
1848	{
1849	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1850
1851	// if (_param->_have_port_depth)
1852	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1853	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1854
1855	SC_START(0);
1856
1857	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1858
1859	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1860	{
1861	LABEL("UPDATE [%d] - Transaction accepted",port);
1862	have_transaction = true;
1863
1864	if (_param->_have_port_context_id)
1865	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1866	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1867	it_ufpt->miss_decod or
1868	it_ufpt->miss_commit ));
1869	// if (update_btb(it_ufpt->condition) or
1870	// update_dir(it_ufpt->condition))
1871	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1872	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1873	// if (update_btb(it_ufpt->condition))
1874	// {
1875	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1876	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1877	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1878	// }
1879	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1880
1881	// if (update_dir(it_ufpt->condition))
1882	// if (_param->_have_port_history)
1883	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1884	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1885	if (update_ras(it_ufpt->condition))
1886	{
1887	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1888	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1889	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1890	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1891	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1892	}
1893	}
1894
1895	SC_START(1);
1896	} while (not have_transaction);
1897
1898	-- it_ufpt;
1899
1900
1901	in_UPDATE_ACK [port]->write(0);
1902	// if (_param->_have_port_depth)
1903	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1904	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1905	}
1906	}
1907	ufpt.clear();
1908
1909	{
1910	LABEL("UPDATE - upt (after event)");
1911
1912	uint32_t port = 0;
1913
1914	LABEL(" * port : %d",port);
1915	std::list<request_t>::iterator it_upt = upt.end();
1916
1917	// for (uint32_t i=0; i<upt.size(); i++)
1918	do
1919	{
1920	--it_upt;
1921
1922	bool have_transaction = false;
1923
1924	if (need_update(it_upt->condition))
1925	do
1926	{
1927	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1928
1929	// if (_param->_have_port_depth)
1930	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1931	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1932
1933	SC_START(0);
1934
1935	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1936
1937	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1938	{
1939	LABEL("UPDATE [%d] - Transaction accepted",port);
1940	LABEL(" * address_src : %.8x",it_upt->address_src);
1941	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1942
1943	have_transaction = true;
1944
1945	bool btb_val = ((it_upt == it_event) and
1946	(update_btb(it_upt->condition)));
1947	bool dir_val = ((it_upt == it_event) and
1948	update_dir(it_upt->condition) and
1949	not (it_upt->miss_ifetch or it_upt->miss_decod));
1950	bool ras_val = update_ras(it_upt->condition);
1951
1952	if (_param->_have_port_context_id)
1953	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1954	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1955	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1956
1957	if (btb_val)
1958	{
1959	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1960	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1961	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1962	}
1963	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1964
1965	if (dir_val)
1966	{
1967	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1968	if (_param->_have_port_history)
1969	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1970	}
1971	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1972
1973	if (ras_val)
1974	{
1975	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1976	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1977	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1978	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1979	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1980	}
1981
1982	// -- it_upt;
1983	}
1984
1985	SC_START(1);
1986	} while (not have_transaction);
1987
1988	upt.pop_back();
1989	in_UPDATE_ACK [port]->write(0);
1990	// if (_param->_have_port_depth)
1991	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1992	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1993	}
1994	while (it_upt != it_event);
1995
1996	}
1997
1998	{
1999	LABEL("BRANCH_EVENT - have miss decod");
2000
2001	uint32_t port = context;
2002
2003	{
2004	bool have_transaction = false;
2005
2006	do
2007	{
2008	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2009
2010	SC_START(0);
2011
2012	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2013
2014	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2015	{
2016	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2017	have_transaction = true;
2018
2019	LABEL(" * event.address_src : %.8x,",event.address_src );
2020	LABEL(" * event.address_good : %.8x,",event.address_good);
2021	LABEL(" * event.take : %.8x,",event.take );
2022
2023	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2024	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2025	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2026	if (event.take_good)
2027	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2028	TEST(Taddress_t,out_BRANCH_EVENT_CAN_CONTINUE [port]->read(),not event.miss_commit);
2029
2030	event.address_src = 0;
2031	event.take = 0;
2032	event.address_dest = 0;
2033	}
2034
2035	SC_START(1);
2036	} while (not have_transaction);
2037
2038	in_BRANCH_EVENT_ACK [port]->write(0);
2039	}
2040	}
2041
2042	{
2043	LABEL("EVENT_STATE");
2044
2045	SC_START(1);
2046	in_EVENT_VAL [context]->write(1);
2047	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2048
2049	SC_START(1);
2050	in_EVENT_VAL [context]->write(0);
2051	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2052	}
2053
2054	{
2055	LABEL("UPDATE - upt (before event)");
2056
2057	uint32_t port = 0;
2058
2059	LABEL(" * port : %d",port);
2060	LABEL(" * size : %d",upt.size());
2061	std::list<request_t>::iterator it_upt = upt.begin();
2062
2063	for (uint32_t i=0; i<upt.size(); i++)
2064	{
2065	bool have_transaction = false;
2066
2067	do
2068	{
2069	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2070
2071	// if (_param->_have_port_depth)
2072	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2073	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2074
2075	SC_START(0);
2076
2077	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2078
2079	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2080	{
2081	LABEL("UPDATE [%d] - Transaction accepted",port);
2082	have_transaction = true;
2083
2084	if (_param->_have_port_context_id)
2085	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2086	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2087	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2088	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2089	if (update_btb(it_upt->condition))
2090	{
2091	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2092	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2093	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2094	}
2095	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2096
2097	if (update_dir(it_upt->condition))
2098	if (_param->_have_port_history)
2099	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2100	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2101	if (update_ras(it_upt->condition))
2102	{
2103	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2104	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2105	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2106	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2107	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2108	}
2109
2110	++ it_upt;
2111	}
2112
2113	SC_START(1);
2114	} while (not have_transaction);
2115
2116	in_UPDATE_ACK [port]->write(0);
2117	// if (_param->_have_port_depth)
2118	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2119	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2120	}
2121	}
2122	upt.clear();
2123
2124	// Wait Garbage Collector
2125	{
2126	LABEL("GARBAGE COLLECTOR");
2127	LABEL(" * upt bottom : %d",upt_bottom [context]);
2128	LABEL(" * upt top : %d",upt_top [context]);
2129
2130	upt_top [context] = (upt_top_event [context]);
2131	upt_bottom [context] = (upt_top [context]);
2132
2133	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2134	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2135	{
2136	SC_START(1);
2137	}
2138
2139	}
2140	}
2141
2142	//---------------------------------------------------------------------
2143	//---------------------------------------------------------------------
2144	// COMMIT MISS : with RAS in UPFT and UPT
2145	//---------------------------------------------------------------------
2146	//---------------------------------------------------------------------
2147	if (test5)
2148	{
2149	uint32_t context = rand() % _param->_nb_context;
2150	uint32_t have_ufpt_ras = false;
2151	uint32_t have_upt_ras = false;
2152
2153	{
2154	LABEL("PREDICT - fill the queue");
2155	uint32_t port = rand() % _param->_nb_inst_predict;
2156
2157	LABEL(" * context : %d",context);
2158	LABEL(" * port : %d",port);
2159
2160	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2161	{
2162	request_t request;
2163	request.context = context;
2164	request.address_src = rand();
2165	request.address_dest = rand();
2166
2167	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
2168	BRANCH_CONDITION_FLAG_SET;
2169
2170	request.take = 1;
2171	request.take_good = 1;
2172	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2173	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2174	request.is_accurate = true ;
2175	request.miss_ifetch = false;
2176	request.miss_decod = false;
2177	request.miss_commit = false;
2178	request.history = i;
2179	request.ras_address = rand();
2180	request.ras_index = rand()%_param->_size_ras_index[context];
2181	request.ufpt_ptr = ufpt_top [context];
2182	// request.upt_ptr;
2183
2184	bool have_transaction = false;
2185	do
2186	{
2187	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2188	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2189	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2190	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2191	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2192	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2193	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2194	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2195	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2196	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2197
2198	if (_param->_have_port_depth)
2199	{
2200	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2201	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2202	}
2203	SC_START(0); // fct melay
2204
2205	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2206	port,
2207	in_PREDICT_VAL [port]->read(),
2208	out_PREDICT_ACK [port]->read(),
2209	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2210
2211	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2212	{
2213	LABEL("PREDICT [%d] - Transaction accepted",port);
2214	have_transaction = true;
2215
2216	if (_param->_have_port_depth)
2217	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2218
2219	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2220	}
2221
2222	SC_START(1); // transition
2223
2224	} while (not have_transaction);
2225
2226	ufpt.push_back(request); // to update
2227
2228	in_PREDICT_VAL [port]->write(0);
2229
2230	if (_param->_have_port_depth)
2231	{
2232	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2233	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2234	}
2235	}
2236	}
2237
2238	{
2239	LABEL("DECOD");
2240	uint32_t port = rand() % _param->_nb_inst_decod;
2241
2242	LABEL(" * context : %d",context);
2243	LABEL(" * port : %d",port);
2244
2245	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2246	{
2247	request_t request = ufpt.front();
2248
2249	bool have_transaction = false;
2250	do
2251	{
2252	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
2253	in_DECOD_CONTEXT_ID [port]->write(request.context );
2254	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
2255	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2256	in_DECOD_BTB_CONDITION [port]->write(request.condition );
2257	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
2258	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
2259	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
2260	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
2261	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
2262	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
2263	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
2264
2265	have_upt_ras \|= (update_ras(request.condition));
2266
2267	SC_START(0); // fct melay
2268
2269	LABEL("DECOD [%d] %d - %d",
2270	port,
2271	in_DECOD_VAL [port]->read(),
2272	out_DECOD_ACK [port]->read());
2273
2274	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
2275	{
2276	LABEL("DECOD [%d] - Transaction accepted",port);
2277	have_transaction = true;
2278
2279	request.upt_ptr = upt_top [context];
2280	upt.push_back(request);
2281	ufpt.pop_front();
2282
2283	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
2284	}
2285
2286	SC_START(1); // transition
2287
2288	} while (not have_transaction);
2289
2290	in_DECOD_VAL [port]->write(0);
2291
2292	if (_param->_have_port_depth)
2293	{
2294	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2295	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2296	}
2297	}
2298	}
2299
2300	{
2301	LABEL("PREDICT - fill the queue");
2302	uint32_t port = rand() % _param->_nb_inst_predict;
2303
2304	LABEL(" * context : %d",context);
2305	LABEL(" * port : %d",port);
2306
2307	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2308	{
2309	request_t request;
2310	request.context = context;
2311	request.address_src = rand();
2312	request.address_dest = rand();
2313	request.address_good = request.address_dest;
2314	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
2315	BRANCH_CONDITION_FLAG_SET;
2316
2317	have_ufpt_ras \|= (update_ras(request.condition));
2318
2319	request.take = 1;
2320	request.take_good = 1;
2321	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2322	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2323	request.is_accurate = true ;
2324	request.miss_ifetch = false;
2325	request.miss_decod = false;
2326	request.miss_commit = true;
2327	request.history = i;
2328	request.ras_address = rand();
2329	request.ras_index = rand()%_param->_size_ras_index[context];
2330	request.ufpt_ptr = ufpt_top [context];
2331	// request.upt_ptr;
2332
2333	bool have_transaction = false;
2334	do
2335	{
2336	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2337	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2338	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2339	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2340	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2341	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2342	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2343	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2344	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2345	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2346
2347	if (_param->_have_port_depth)
2348	{
2349	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2350	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2351	}
2352	SC_START(0); // fct melay
2353
2354	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2355	port,
2356	in_PREDICT_VAL [port]->read(),
2357	out_PREDICT_ACK [port]->read(),
2358	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2359
2360	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2361	{
2362	LABEL("PREDICT [%d] - Transaction accepted",port);
2363	have_transaction = true;
2364
2365	if (_param->_have_port_depth)
2366	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2367
2368	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2369	}
2370
2371	SC_START(1); // transition
2372
2373	} while (not have_transaction);
2374
2375	ufpt.push_back(request); // to update
2376
2377	in_PREDICT_VAL [port]->write(0);
2378
2379	if (_param->_have_port_depth)
2380	{
2381	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2382	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2383	}
2384	}
2385	}
2386
2387	uint32_t nb_branch_before_event = 0;
2388	{
2389	// middle
2390	std::list<request_t>::iterator it_event = upt.begin();
2391	for (uint32_t i=0; i < (upt.size()>>1); ++i)
2392	{
2393	nb_branch_before_event ++;
2394	it_event ++;
2395	}
2396	for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it)
2397	it->miss_commit = true;
2398
2399	bool have_transaction = false;
2400
2401	do
2402	{
2403	PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event);
2404	PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION);
2405	PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr);
2406
2407	SC_START(0);
2408
2409	if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context]))
2410	{
2411	LABEL("EVENT [%d] - Transaction accepted",context);
2412
2413	have_transaction = true;
2414	}
2415
2416	SC_START(1);
2417	}
2418	while (not have_transaction);
2419	PORT_WRITE(in_EVENT_VAL [context],0);
2420
2421	upt_top_event [it_event->context] = upt_top [it_event->context];
2422	upt_top [it_event->context] = it_event->upt_ptr;
2423	}
2424
2425	{
2426	LABEL("BRANCH_COMPLETE - Hit ifetch");
2427
2428	uint32_t port = rand() % _param->_nb_inst_branch_complete;
2429
2430	LABEL(" * port : %d",port);
2431
2432	std::list<request_t>::iterator it_upt = upt.begin();
2433
2434	for (uint32_t i=0; i<nb_branch_before_event; ++i)
2435	{
2436	bool have_transaction = false;
2437
2438	do
2439	{
2440	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
2441	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
2442	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
2443	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
2444	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
2445
2446	if (_param->_have_port_depth)
2447	{
2448	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2449	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2450	}
2451	SC_START(0);
2452
2453	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
2454
2455	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
2456	{
2457	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
2458	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
2459	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
2460	LABEL(" * CONDITION : %d" ,it_upt->condition );
2461	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
2462	LABEL(" * FLAG : %d" ,it_upt->flag );
2463	LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence );
2464
2465	have_transaction = true;
2466
2467	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
2468	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
2469	it_upt->take_good = it_upt->take;
2470	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
2471	// TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2472
2473	it_upt++;
2474	}
2475
2476	SC_START(1);
2477
2478	} while (not have_transaction);
2479
2480	in_BRANCH_COMPLETE_VAL [port]->write(0);
2481
2482	if (_param->_have_port_depth)
2483	{
2484	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2485	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2486	}
2487	}
2488	}
2489
2490	if (have_ufpt_ras)
2491	{
2492	LABEL("UPDATE - Update UPFT");
2493
2494	uint32_t port = 0;
2495
2496	LABEL(" * port : %d",port);
2497	std::list<request_t>::iterator it_ufpt = ufpt.end();
2498	-- it_ufpt;
2499
2500	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2501	{
2502	bool have_transaction = false;
2503
2504	do
2505	{
2506	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2507
2508	// if (_param->_have_port_depth)
2509	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2510	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2511
2512	SC_START(0);
2513
2514	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2515
2516	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2517	{
2518	LABEL("UPDATE [%d] - Transaction accepted",port);
2519	have_transaction = true;
2520
2521	if (_param->_have_port_context_id)
2522	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
2523	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
2524	it_ufpt->miss_decod or
2525	it_ufpt->miss_commit ));
2526	// if (update_btb(it_ufpt->condition) or
2527	// update_dir(it_ufpt->condition))
2528	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
2529	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
2530	// if (update_btb(it_ufpt->condition))
2531	// {
2532	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
2533	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
2534	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
2535	// }
2536	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
2537
2538	// if (update_dir(it_ufpt->condition))
2539	// if (_param->_have_port_history)
2540	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
2541	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
2542	if (update_ras(it_ufpt->condition))
2543	{
2544	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2545	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
2546	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
2547	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
2548	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
2549	}
2550	}
2551
2552	SC_START(1);
2553	} while (not have_transaction);
2554
2555	-- it_ufpt;
2556
2557
2558	in_UPDATE_ACK [port]->write(0);
2559	// if (_param->_have_port_depth)
2560	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2561	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2562	}
2563	}
2564	ufpt.clear();
2565
2566	{
2567	LABEL("UPDATE - upt (after event)");
2568
2569	uint32_t port = 0;
2570
2571	LABEL(" * port : %d",port);
2572
2573	std::list<request_t>::iterator it_upt = upt.end();
2574
2575	// for (uint32_t i=0; i<upt.size(); i++)
2576
2577	uint32_t size = upt.size();
2578
2579	LABEL(" * size : %d",size);
2580	LABEL(" * nb_branch_before_event : %d",nb_branch_before_event);
2581
2582	for (uint32_t i=nb_branch_before_event; i<size; ++i)
2583	{
2584	--it_upt;
2585
2586	bool have_transaction = false;
2587
2588	if (need_update(it_upt->condition))
2589	do
2590	{
2591	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2592
2593	// if (_param->_have_port_depth)
2594	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2595	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2596
2597	SC_START(0);
2598
2599	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2600
2601	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2602	{
2603	LABEL("UPDATE [%d] - Transaction accepted",port);
2604	LABEL(" * address_src : %.8x",it_upt->address_src);
2605	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
2606
2607	have_transaction = true;
2608
2609	bool btb_val = ((update_btb(it_upt->condition)));
2610	bool dir_val = (update_dir(it_upt->condition) and
2611	not (it_upt->miss_ifetch or it_upt->miss_decod));
2612	bool ras_val = update_ras(it_upt->condition);
2613
2614	if (_param->_have_port_context_id)
2615	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2616	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2617	// TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
2618
2619	// if (btb_val)
2620	// {
2621	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2622	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2623	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2624	// }
2625	// TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
2626
2627	// if (dir_val)
2628	// {
2629	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2630	// if (_param->_have_port_history)
2631	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2632	// }
2633	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
2634
2635	if (ras_val)
2636	{
2637	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2638	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2639	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2640	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2641	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2642	}
2643	// -- it_upt;
2644	}
2645
2646	SC_START(1);
2647	} while (not have_transaction);
2648
2649	upt.pop_back();
2650	in_UPDATE_ACK [port]->write(0);
2651	// if (_param->_have_port_depth)
2652	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2653	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2654	}
2655	}
2656
2657	/*
2658	{
2659	LABEL("BRANCH_EVENT - have miss decod");
2660
2661	uint32_t port = context;
2662
2663	{
2664	bool have_transaction = false;
2665
2666	do
2667	{
2668	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2669
2670	SC_START(0);
2671
2672	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2673
2674	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2675	{
2676	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2677	have_transaction = true;
2678
2679	LABEL(" * event.address_src : %.8x,",event.address_src );
2680	LABEL(" * event.address_good : %.8x,",event.address_good);
2681	LABEL(" * event.take : %.8x,",event.take );
2682
2683	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2684	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2685	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2686	if (event.take_good)
2687	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2688	TEST(Taddress_t,out_BRANCH_EVENT_CAN_CONTINUE [port]->read(),not event.miss_commit);
2689
2690	event.address_src = 0;
2691	event.take = 0;
2692	event.address_dest = 0;
2693	}
2694
2695	SC_START(1);
2696	} while (not have_transaction);
2697
2698	in_BRANCH_EVENT_ACK [port]->write(0);
2699	}
2700	}
2701
2702	{
2703	LABEL("EVENT_STATE");
2704
2705	SC_START(1);
2706	in_EVENT_VAL [context]->write(1);
2707	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2708
2709	SC_START(1);
2710	in_EVENT_VAL [context]->write(0);
2711	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2712	}
2713	*/
2714
2715	{
2716	LABEL("UPDATE - upt (before event)");
2717
2718	uint32_t port = 0;
2719
2720	LABEL(" * port : %d",port);
2721	LABEL(" * size : %d",upt.size());
2722	std::list<request_t>::iterator it_upt = upt.begin();
2723
2724	for (uint32_t i=0; i<upt.size(); i++)
2725	{
2726	bool have_transaction = false;
2727
2728	do
2729	{
2730	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2731
2732	// if (_param->_have_port_depth)
2733	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2734	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2735
2736	SC_START(0);
2737
2738	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2739
2740	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2741	{
2742	LABEL("UPDATE [%d] - Transaction accepted",port);
2743	have_transaction = true;
2744
2745	if (_param->_have_port_context_id)
2746	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2747	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2748	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2749	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2750	if (update_btb(it_upt->condition))
2751	{
2752	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2753	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2754	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2755	}
2756	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2757
2758	if (update_dir(it_upt->condition))
2759	if (_param->_have_port_history)
2760	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2761	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2762	if (update_ras(it_upt->condition))
2763	{
2764	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2765	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2766	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2767	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2768	TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2769	}
2770
2771	++ it_upt;
2772	}
2773
2774	SC_START(1);
2775	} while (not have_transaction);
2776
2777	in_UPDATE_ACK [port]->write(0);
2778	// if (_param->_have_port_depth)
2779	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2780	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2781	}
2782	}
2783
2784	upt.clear();
2785
2786	// Wait Garbage Collector
2787	{
2788	LABEL("GARBAGE COLLECTOR");
2789	LABEL(" * upt bottom : %d",upt_bottom [context]);
2790	LABEL(" * upt top : %d",upt_top [context]);
2791
2792	upt_top [context] = (upt_top_event [context]);
2793	upt_bottom [context] = (upt_top [context]);
2794
2795	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2796	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2797	{
2798	SC_START(1);
2799	}
2800	}
2801	}
2802
2803	}// ITERATION
2804
2805	/********************************************************
2806	* Simulation - End
2807	********************************************************/
2808
2809	TEST_OK ("End of Simulation");
2810	delete _time;
2811
2812	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2813
2814	delete in_CLOCK;
2815	delete in_NRESET;
2816
2817	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2818	delete [] in_PREDICT_VAL ;
2819	delete [] out_PREDICT_ACK ;
2820	delete [] in_PREDICT_CONTEXT_ID ;
2821	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2822	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2823	delete [] in_PREDICT_BTB_CONDITION ;
2824	delete [] in_PREDICT_BTB_LAST_TAKE ;
2825	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2826	delete [] in_PREDICT_DIR_HISTORY ;
2827	delete [] in_PREDICT_RAS_ADDRESS ;
2828	delete [] in_PREDICT_RAS_INDEX ;
2829	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2830
2831	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2832	delete [] in_DECOD_VAL ;
2833	delete [] out_DECOD_ACK ;
2834	delete [] in_DECOD_CONTEXT_ID ;
2835	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2836	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2837	delete [] in_DECOD_BTB_CONDITION ;
2838	delete [] in_DECOD_BTB_LAST_TAKE ;
2839	delete [] in_DECOD_RAS_ADDRESS ;
2840	delete [] in_DECOD_RAS_INDEX ;
2841	delete [] in_DECOD_MISS_DECOD ;
2842	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2843	//delete [] out_DECOD_DEPTH ;
2844	delete [] in_DECOD_IS_ACCURATE ;
2845	delete [] out_DECOD_CAN_CONTINUE ;
2846
2847	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2848	delete [] in_BRANCH_COMPLETE_VAL ;
2849	delete [] out_BRANCH_COMPLETE_ACK ;
2850	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2851	delete [] in_BRANCH_COMPLETE_DEPTH ;
2852	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2853	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2854	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2855	// delete [] out_BRANCH_COMPLETE_TAKE ;
2856	// delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2857	// delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2858
2859	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2860	delete [] out_BRANCH_EVENT_VAL ;
2861	delete [] in_BRANCH_EVENT_ACK ;
2862	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2863	delete [] out_BRANCH_EVENT_DEPTH ;
2864	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2865	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2866	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2867	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2868	delete [] out_BRANCH_EVENT_CAN_CONTINUE ;
2869
2870	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2871	delete [] out_UPDATE_VAL ;
2872	delete [] in_UPDATE_ACK ;
2873	delete [] out_UPDATE_CONTEXT_ID ;
2874	delete [] out_UPDATE_MISS_PREDICTION ;
2875	delete [] out_UPDATE_DIRECTION_GOOD ;
2876	delete [] out_UPDATE_PREDICTION_IFETCH ;
2877	delete [] out_UPDATE_BTB_VAL ;
2878	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2879	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2880	delete [] out_UPDATE_BTB_CONDITION ;
2881	delete [] out_UPDATE_DIR_VAL ;
2882	delete [] out_UPDATE_DIR_HISTORY ;
2883	delete [] out_UPDATE_RAS_VAL ;
2884	delete [] out_UPDATE_RAS_FLUSH ;
2885	delete [] out_UPDATE_RAS_PUSH ;
2886	delete [] out_UPDATE_RAS_ADDRESS ;
2887	delete [] out_UPDATE_RAS_INDEX ;
2888
2889	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2890	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2891	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2892	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2893
2894	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2895	delete [] out_DEPTH_VAL;
2896	delete [] out_DEPTH_CURRENT;
2897	delete [] out_DEPTH_MIN;
2898	delete [] out_DEPTH_MAX;
2899	delete [] out_DEPTH_FULL;
2900
2901	#endif
2902
2903	delete _Update_Prediction_Table;
2904	#ifdef STATISTICS
2905	delete _parameters_statistics;
2906	#endif
2907	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 119

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