[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_transition.cpp 106 2009-02-09 22:55:26Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace commit_unit { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::transition" |
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| 21 | void Commit_unit::transition (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[100] | 28 | // Clear all bank |
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[88] | 29 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 30 | { |
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| 31 | _rob [i].clear(); |
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| 32 | reg_BANK_PTR [i] = 0; |
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| 33 | } |
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| 34 | |
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[100] | 35 | // Reset pointer |
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[88] | 36 | reg_NUM_BANK_HEAD = 0; |
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| 37 | reg_NUM_BANK_TAIL = 0; |
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| 38 | |
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[100] | 39 | // Reset counter |
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[88] | 40 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 41 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 42 | { |
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[104] | 43 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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| 44 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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| 45 | |
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| 46 | reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; |
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| 47 | reg_EVENT_FLUSH [i][j] = false; |
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[100] | 48 | |
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[104] | 49 | // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; |
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| 50 | reg_PC_CURRENT [i][j] = (0x100 )>>2; |
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| 51 | reg_PC_CURRENT_IS_DS [i][j] = 0; |
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| 52 | reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; |
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[105] | 53 | reg_PC_NEXT [i][j] = (0x100+4)>>2; |
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[88] | 54 | } |
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| 55 | |
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[100] | 56 | // Reset priority algorithm |
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[88] | 57 | _priority_insert->reset(); |
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| 58 | } |
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| 59 | else |
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| 60 | { |
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[100] | 61 | // Compute next priority |
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[88] | 62 | _priority_insert->transition(); |
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| 63 | |
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| 64 | // =================================================================== |
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[100] | 65 | // =====[ GARBAGE COLLECTOR ]========================================= |
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| 66 | // =================================================================== |
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| 67 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 68 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 69 | switch (reg_EVENT_STATE [i][j]) |
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| 70 | { |
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[104] | 71 | case EVENT_STATE_EVENT : |
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| 72 | { |
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| 73 | if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) |
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| 74 | reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; |
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| 75 | break; |
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| 76 | } |
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| 77 | case EVENT_STATE_WAITEND : |
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| 78 | { |
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| 79 | if (reg_NB_INST_COMMIT_ALL [i][j] == 0) |
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| 80 | { |
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| 81 | reg_EVENT_STATE [i][j] = EVENT_STATE_END; |
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| 82 | reg_EVENT_FLUSH [i][j] = false; |
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| 83 | } |
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| 84 | break; |
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| 85 | } |
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| 86 | case EVENT_STATE_END : |
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| 87 | { |
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| 88 | reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; |
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| 89 | break; |
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| 90 | } |
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[100] | 91 | // case EVENT_STATE_NO_EVENT : |
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| 92 | default : break; |
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| 93 | } |
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| 94 | |
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| 95 | // =================================================================== |
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[88] | 96 | // =====[ INSERT ]==================================================== |
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| 97 | // =================================================================== |
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| 98 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 99 | if (internal_BANK_INSERT_VAL [i]) |
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| 100 | { |
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[100] | 101 | // get rename unit source and instruction. |
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[88] | 102 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; |
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| 103 | uint32_t y = internal_BANK_INSERT_NUM_INST [i]; |
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| 104 | |
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| 105 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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| 106 | { |
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| 107 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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| 108 | |
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| 109 | #ifdef STATISTICS |
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| 110 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 111 | (*_stat_nb_inst_insert [x]) ++; |
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| 112 | #endif |
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| 113 | |
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[100] | 114 | // get information |
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[88] | 115 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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| 116 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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| 117 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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| 118 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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[100] | 119 | bool is_store = is_operation_memory_store(operation); |
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| 120 | |
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[88] | 121 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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| 122 | |
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| 123 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 124 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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[97] | 125 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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[88] | 126 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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| 127 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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[100] | 128 | |
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| 129 | // Create new entry. |
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[88] | 130 | entry_t * entry = new entry_t; |
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| 131 | |
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| 132 | entry->ptr = reg_BANK_PTR [i]; |
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| 133 | entry->front_end_id = front_end_id; |
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| 134 | entry->context_id = context_id ; |
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| 135 | entry->rename_unit_id = x; |
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| 136 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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| 137 | entry->type = type; |
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| 138 | entry->operation = operation; |
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| 139 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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[105] | 140 | // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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[88] | 141 | entry->exception = exception; |
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| 142 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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[100] | 143 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store); |
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| 144 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store); |
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[88] | 145 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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| 146 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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| 147 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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| 148 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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| 149 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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| 150 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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| 151 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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| 152 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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| 153 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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| 154 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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| 155 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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| 156 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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| 157 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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| 158 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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| 159 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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| 160 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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| 161 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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| 162 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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| 163 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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[105] | 164 | entry->no_sequence = type == TYPE_BRANCH; |
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| 165 | entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); |
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[88] | 166 | |
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[100] | 167 | // Test if exception : |
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| 168 | // * yes : no execute instruction, wait ROB Head |
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| 169 | // * no : test type |
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| 170 | // * BRANCH : l.j -> branch is ended |
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| 171 | // other -> wait the execution end of branchment |
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| 172 | // * MEMORY : store -> wait store is at head of ROB |
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| 173 | // other -> wait end of instruction |
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| 174 | // * OTHER |
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[88] | 175 | if (exception == EXCEPTION_NONE) |
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| 176 | { |
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| 177 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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| 178 | // no_execute : l.j, l.nop, l.rfe |
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| 179 | |
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| 180 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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| 181 | |
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| 182 | switch (type) |
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| 183 | { |
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| 184 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} |
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[100] | 185 | case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} |
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[88] | 186 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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| 187 | } |
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| 188 | } |
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| 189 | else |
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| 190 | { |
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[100] | 191 | // Have an exception : wait head of ROB |
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| 192 | |
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[88] | 193 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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| 194 | |
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| 195 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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| 196 | } |
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| 197 | |
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[100] | 198 | // Push in rob |
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[88] | 199 | _rob[i].push_back(entry); |
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| 200 | |
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[100] | 201 | // Update counter and pointer |
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[88] | 202 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
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| 203 | if (type == TYPE_MEMORY) |
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| 204 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
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| 205 | |
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| 206 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank; |
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| 207 | reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank; |
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| 208 | } |
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| 209 | } |
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| 210 | |
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| 211 | // =================================================================== |
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| 212 | // =====[ COMMIT ]==================================================== |
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| 213 | // =================================================================== |
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| 214 | |
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| 215 | #ifdef STATISTICS |
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| 216 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 217 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
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| 218 | #endif |
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| 219 | |
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| 220 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 221 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
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| 222 | if (internal_BANK_COMMIT_VAL [i][j]) |
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| 223 | { |
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[100] | 224 | // An instruction is executed. Change state of this instruction |
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| 225 | |
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[88] | 226 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
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| 227 | |
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| 228 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
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| 229 | { |
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| 230 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
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| 231 | |
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| 232 | #ifdef STATISTICS |
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| 233 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 234 | (*_stat_nb_inst_commit) ++; |
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| 235 | #endif |
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| 236 | |
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| 237 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
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| 238 | |
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| 239 | // find the good entry !!! |
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[100] | 240 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
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| 241 | |
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| 242 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
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| 243 | //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); |
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| 244 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
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[88] | 245 | |
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[100] | 246 | rob_state_t state = entry->state; |
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| 247 | Tcontext_t front_end_id = entry->front_end_id; |
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| 248 | Tcontext_t context_id = entry->context_id; |
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[88] | 249 | |
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[100] | 250 | // change state : test exception_use |
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[88] | 251 | // * test if exception : exception and mask |
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| 252 | |
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[100] | 253 | bool have_exception = false; |
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| 254 | bool have_miss_speculation = false; |
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| 255 | |
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[88] | 256 | if (exception != EXCEPTION_NONE) |
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[100] | 257 | { |
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| 258 | // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) |
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| 259 | have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); |
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[88] | 260 | |
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[100] | 261 | switch (entry->exception_use) |
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| 262 | { |
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| 263 | // Have overflow exception if bit overflow enable is set. |
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| 264 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
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| 265 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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| 266 | (exception == EXCEPTION_DATA_TLB ) or |
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| 267 | (exception == EXCEPTION_DATA_PAGE) or |
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| 268 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
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| 269 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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| 270 | (exception == EXCEPTION_DATA_TLB ) or |
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| 271 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
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| 272 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
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| 273 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
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| 274 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
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| 275 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
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| 276 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
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| 277 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
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| 278 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
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| 279 | // Case already manage (decod stage -> in insert in ROB) |
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| 280 | case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 281 | case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 282 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 283 | case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 284 | default : |
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| 285 | { |
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| 286 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
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| 287 | break; |
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| 288 | } |
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| 289 | } |
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| 290 | } |
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| 291 | |
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| 292 | switch (state) |
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| 293 | { |
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| 294 | // Branch ... |
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| 295 | case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} |
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| 296 | // Store KO |
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| 297 | case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} |
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| 298 | // Store OK, Load and other instruction |
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[105] | 299 | case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} |
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[100] | 300 | default : |
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| 301 | { |
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| 302 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); |
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| 303 | break; |
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| 304 | } |
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| 305 | } |
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[88] | 306 | |
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| 307 | // update Re Order Buffer |
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[105] | 308 | entry->state = state; |
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| 309 | entry->exception = exception; |
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| 310 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
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| 311 | entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
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| 312 | // jalr, jr : address_dest is in register |
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| 313 | if ((entry->type == TYPE_BRANCH) and |
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| 314 | (entry->operation == OPERATION_BRANCH_L_JALR) and |
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| 315 | (entry->read_rb)) |
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| 316 | entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); |
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[88] | 317 | } |
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| 318 | } |
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| 319 | |
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| 320 | // =================================================================== |
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| 321 | // =====[ RETIRE ]==================================================== |
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| 322 | // =================================================================== |
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| 323 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 324 | if (internal_BANK_RETIRE_VAL [i]) |
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| 325 | { |
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| 326 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i]; |
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| 327 | uint32_t y = internal_BANK_RETIRE_NUM_INST [i]; |
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| 328 | |
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| 329 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
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| 330 | |
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| 331 | #ifdef DEBUG_TEST |
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| 332 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
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| 333 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
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| 334 | #endif |
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| 335 | |
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[98] | 336 | entry_t * entry = _rob [i].front(); |
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[100] | 337 | rob_state_t state = entry->state; |
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| 338 | |
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[98] | 339 | #ifdef STATISTICS |
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| 340 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 341 | { |
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| 342 | if (state == ROB_END_OK) |
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| 343 | (*_stat_nb_inst_retire_ok [x]) ++; |
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| 344 | else |
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| 345 | (*_stat_nb_inst_retire_ko [x]) ++; |
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| 346 | } |
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| 347 | #endif |
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[88] | 348 | |
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| 349 | Tcontext_t front_end_id = entry->front_end_id; |
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| 350 | Tcontext_t context_id = entry->context_id ; |
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| 351 | Ttype_t type = entry->type ; |
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[100] | 352 | |
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[105] | 353 | if ((state == ROB_END_OK ) or // LOAD_MISS |
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| 354 | // (state == ROB_END_KO ) or |
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| 355 | (state == ROB_END_BRANCH_MISS)// or |
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| 356 | // (state == ROB_END_LOAD_MISS ) or |
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| 357 | // (state == ROB_END_MISS ) or |
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| 358 | // (state == ROB_END_EXCEPTION ) |
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| 359 | ) |
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[100] | 360 | { |
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[105] | 361 | // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; |
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| 362 | reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; |
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| 363 | reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; |
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| 364 | reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; |
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| 365 | reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); |
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[106] | 366 | |
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| 367 | // if (entry->address_next != reg_PC_NEXT [front_end_id][context_id]) |
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| 368 | // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); |
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[105] | 369 | } |
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| 370 | |
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| 371 | if ((state == ROB_END_BRANCH_MISS) or |
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| 372 | (state == ROB_END_LOAD_MISS)) |
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| 373 | { |
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[100] | 374 | reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; |
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[104] | 375 | reg_EVENT_FLUSH [front_end_id][context_id] = true; |
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[100] | 376 | } |
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[88] | 377 | |
---|
| 378 | // Update nb_inst |
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| 379 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
---|
| 380 | if (type == TYPE_MEMORY) |
---|
| 381 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
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[100] | 382 | |
---|
[88] | 383 | reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; |
---|
| 384 | |
---|
| 385 | _rob [i].pop_front(); |
---|
| 386 | delete entry; |
---|
| 387 | } |
---|
| 388 | |
---|
| 389 | // =================================================================== |
---|
| 390 | // =====[ REEXECUTE ]================================================= |
---|
| 391 | // =================================================================== |
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| 392 | if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) |
---|
| 393 | { |
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[101] | 394 | log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]"); |
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| 395 | |
---|
[88] | 396 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; |
---|
| 397 | |
---|
| 398 | entry_t * entry = _rob [num_bank].front(); |
---|
| 399 | rob_state_t state = entry->state; |
---|
| 400 | |
---|
| 401 | switch (state) |
---|
| 402 | { |
---|
| 403 | case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } |
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| 404 | case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; } |
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| 405 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
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| 406 | } |
---|
| 407 | |
---|
| 408 | entry->state = state; |
---|
| 409 | } |
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| 410 | |
---|
| 411 | // =================================================================== |
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| 412 | // =====[ BRANCH_COMPLETE ]=========================================== |
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| 413 | // =================================================================== |
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| 414 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 415 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
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| 416 | { |
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[101] | 417 | log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
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| 418 | log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])); |
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| 419 | |
---|
[88] | 420 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
---|
| 421 | |
---|
| 422 | entry_t * entry = _rob [num_bank].front(); |
---|
| 423 | |
---|
| 424 | #ifdef DEBUG_TEST |
---|
| 425 | rob_state_t state = entry->state; |
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| 426 | if (state != ROB_BRANCH_COMPLETE) |
---|
| 427 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
---|
| 428 | #endif |
---|
| 429 | |
---|
[101] | 430 | entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; |
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[100] | 431 | // entry->state = ROB_END_OK_SPECULATIVE; |
---|
[88] | 432 | } |
---|
| 433 | |
---|
| 434 | // =================================================================== |
---|
[100] | 435 | // =====[ UPDATE ]==================================================== |
---|
| 436 | // =================================================================== |
---|
[105] | 437 | if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) |
---|
| 438 | { |
---|
| 439 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); |
---|
[100] | 440 | |
---|
[105] | 441 | entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); |
---|
| 442 | |
---|
| 443 | switch (entry->state) |
---|
| 444 | { |
---|
| 445 | // case ROB_END_EXCEPTION_UPDATE : |
---|
| 446 | // { |
---|
| 447 | // entry->state = ROB_END_KO; |
---|
| 448 | // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); |
---|
| 449 | // break; |
---|
| 450 | // } |
---|
| 451 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 452 | { |
---|
| 453 | log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); |
---|
| 454 | |
---|
| 455 | entry->state = ROB_END_LOAD_MISS; |
---|
| 456 | break; |
---|
| 457 | } |
---|
| 458 | default : |
---|
| 459 | { |
---|
| 460 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); |
---|
| 461 | break; |
---|
| 462 | } |
---|
| 463 | } |
---|
| 464 | |
---|
| 465 | } |
---|
| 466 | |
---|
[100] | 467 | // =================================================================== |
---|
[88] | 468 | // =====[ EVENT ]===================================================== |
---|
| 469 | // =================================================================== |
---|
[100] | 470 | { |
---|
| 471 | // Not yet implemented |
---|
| 472 | } |
---|
[88] | 473 | |
---|
| 474 | // =================================================================== |
---|
| 475 | // =====[ DEPTH - HEAD ]============================================== |
---|
| 476 | // =================================================================== |
---|
| 477 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 478 | if (not _rob[i].empty()) |
---|
| 479 | { |
---|
| 480 | // Scan all instruction in windows and test if instruction is speculative |
---|
| 481 | entry_t * entry = _rob [i].front(); |
---|
| 482 | |
---|
| 483 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 484 | Tcontext_t context_id = entry->context_id ; |
---|
| 485 | rob_state_t state = entry->state; |
---|
| 486 | Tdepth_t depth = entry->depth; |
---|
| 487 | |
---|
[101] | 488 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; |
---|
[105] | 489 | Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; |
---|
| 490 | Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); |
---|
[88] | 491 | |
---|
| 492 | // is a valid instruction ? |
---|
| 493 | // If DEPTH_CURRENT : |
---|
| 494 | // equal at DEPTH_MIN -> not speculative |
---|
[101] | 495 | // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss |
---|
| 496 | // include ]DEPTH_MIN:DEPTH_MAX] -> speculative |
---|
[88] | 497 | |
---|
| 498 | // All case |
---|
| 499 | // ....... min ...X... max ....... OK |
---|
| 500 | // ....... min ....... max ...X... KO |
---|
| 501 | // ...X... min ....... max ....... KO |
---|
| 502 | // ....... max ....... min ...X... OK |
---|
| 503 | // ...X... max ....... min ....... OK |
---|
| 504 | // ....... max ...X... min ....... KO |
---|
| 505 | |
---|
[104] | 506 | bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
---|
| 507 | |
---|
[105] | 508 | Tcontrol_t is_valid = (((depth == depth_min) or |
---|
| 509 | depth_full or |
---|
| 510 | ((depth_min <= depth_max)? |
---|
| 511 | ((depth >= depth_min) and (depth <=depth_max)): |
---|
| 512 | ((depth >= depth_min) or (depth <=depth_max)))) |
---|
| 513 | and not flush); |
---|
| 514 | |
---|
| 515 | // Tcontrol_t is_valid = ((depth == depth_min) and not flush); |
---|
| 516 | |
---|
[101] | 517 | log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); |
---|
[105] | 518 | log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); |
---|
[101] | 519 | log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); |
---|
| 520 | log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); |
---|
[105] | 521 | log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); |
---|
| 522 | log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); |
---|
[104] | 523 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
[101] | 524 | |
---|
[88] | 525 | //------------------------------------------------------ |
---|
| 526 | // test if instruction is miss speculative |
---|
| 527 | //------------------------------------------------------ |
---|
| 528 | if (not is_valid) |
---|
| 529 | { |
---|
| 530 | switch (state) |
---|
| 531 | { |
---|
[100] | 532 | case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} |
---|
| 533 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
---|
| 534 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[105] | 535 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[100] | 536 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} |
---|
| 537 | //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} |
---|
| 538 | case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} |
---|
| 539 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 540 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 541 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
---|
| 542 | |
---|
| 543 | // don't change |
---|
| 544 | case ROB_STORE_HEAD_KO : {break;} |
---|
| 545 | case ROB_MISS_WAIT_END : {break;} |
---|
| 546 | case ROB_END_MISS : {break;} |
---|
| 547 | |
---|
| 548 | // can't have miss speculation |
---|
| 549 | case ROB_STORE_HEAD_OK : |
---|
| 550 | case ROB_END_OK : |
---|
| 551 | case ROB_END_KO : |
---|
| 552 | case ROB_END_BRANCH_MISS : |
---|
[105] | 553 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 554 | case ROB_END_LOAD_MISS : |
---|
| 555 | case ROB_END_EXCEPTION_UPDATE : |
---|
[100] | 556 | case ROB_END_EXCEPTION : |
---|
| 557 | default : |
---|
[88] | 558 | { |
---|
| 559 | throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); |
---|
| 560 | break; |
---|
| 561 | } |
---|
| 562 | } |
---|
| 563 | } |
---|
| 564 | |
---|
| 565 | //------------------------------------------------------ |
---|
| 566 | // test if instruction is not speculative |
---|
| 567 | //------------------------------------------------------ |
---|
| 568 | if (entry->depth == depth_min) |
---|
| 569 | { |
---|
| 570 | switch (state) |
---|
| 571 | { |
---|
[100] | 572 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
---|
| 573 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
---|
| 574 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
[105] | 575 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
[88] | 576 | default : {break;} |
---|
| 577 | } |
---|
| 578 | } |
---|
| 579 | |
---|
| 580 | //------------------------------------------------------ |
---|
| 581 | // test if instruction is store and head |
---|
| 582 | //------------------------------------------------------ |
---|
| 583 | if (i == reg_NUM_BANK_HEAD) |
---|
| 584 | { |
---|
| 585 | switch (state) |
---|
| 586 | { |
---|
[105] | 587 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
---|
| 588 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} |
---|
[88] | 589 | default : {break;} |
---|
| 590 | } |
---|
| 591 | } |
---|
| 592 | |
---|
| 593 | entry->state = state; |
---|
| 594 | } |
---|
| 595 | } |
---|
| 596 | |
---|
| 597 | // =================================================================== |
---|
| 598 | // =====[ OTHER ]===================================================== |
---|
| 599 | // =================================================================== |
---|
| 600 | |
---|
| 601 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
---|
| 602 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
---|
| 603 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
---|
| 604 | |
---|
| 605 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 606 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[104] | 607 | { |
---|
| 608 | log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); |
---|
[105] | 609 | log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); |
---|
| 610 | log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); |
---|
[106] | 611 | log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); |
---|
| 612 | log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); |
---|
[104] | 613 | } |
---|
[88] | 614 | |
---|
| 615 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 616 | { |
---|
[104] | 617 | log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); |
---|
[88] | 618 | |
---|
| 619 | #ifdef STATISTICS |
---|
| 620 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 621 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
---|
| 622 | #endif |
---|
| 623 | |
---|
| 624 | uint32_t x=0; |
---|
| 625 | for (std::list<entry_t*>::iterator it=_rob[i].begin(); |
---|
| 626 | it!=_rob[i].end(); |
---|
| 627 | it++) |
---|
| 628 | { |
---|
[105] | 629 | log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", |
---|
[88] | 630 | x, |
---|
[97] | 631 | (*it)->front_end_id , |
---|
| 632 | (*it)->context_id , |
---|
| 633 | (*it)->rename_unit_id , |
---|
| 634 | (*it)->depth , |
---|
| 635 | (*it)->type , |
---|
| 636 | (*it)->operation , |
---|
[105] | 637 | // (*it)->address , |
---|
| 638 | // (*it)->address << 2 , |
---|
[97] | 639 | (*it)->is_delay_slot , |
---|
| 640 | (*it)->use_store_queue , |
---|
| 641 | (*it)->store_queue_ptr_write , |
---|
| 642 | (*it)->use_load_queue , |
---|
| 643 | (*it)->load_queue_ptr_write , |
---|
| 644 | toString((*it)->state).c_str() , |
---|
| 645 | (*it)->ptr ); |
---|
[101] | 646 | log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", |
---|
[97] | 647 | (*it)->read_ra , |
---|
| 648 | (*it)->num_reg_ra_log , |
---|
| 649 | (*it)->num_reg_ra_phy , |
---|
| 650 | (*it)->read_rb , |
---|
| 651 | (*it)->num_reg_rb_log , |
---|
| 652 | (*it)->num_reg_rb_phy , |
---|
| 653 | (*it)->read_rc , |
---|
| 654 | (*it)->num_reg_rc_log , |
---|
| 655 | (*it)->num_reg_rc_phy , |
---|
| 656 | (*it)->write_rd , |
---|
| 657 | (*it)->num_reg_rd_log , |
---|
| 658 | (*it)->num_reg_rd_phy_old , |
---|
| 659 | (*it)->num_reg_rd_phy_new , |
---|
| 660 | (*it)->write_re , |
---|
| 661 | (*it)->num_reg_re_log , |
---|
| 662 | (*it)->num_reg_re_phy_old , |
---|
| 663 | (*it)->num_reg_re_phy_new ); |
---|
| 664 | |
---|
[105] | 665 | log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x (%.8x)", |
---|
[101] | 666 | (*it)->exception_use , |
---|
[97] | 667 | (*it)->exception , |
---|
| 668 | (*it)->flags , |
---|
| 669 | (*it)->no_sequence , |
---|
[105] | 670 | (*it)->address_next , |
---|
| 671 | (*it)->address_next<<2 |
---|
[97] | 672 | ); |
---|
| 673 | |
---|
[88] | 674 | x++; |
---|
| 675 | } |
---|
| 676 | } |
---|
| 677 | |
---|
| 678 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 679 | end_cycle (); |
---|
| 680 | #endif |
---|
| 681 | |
---|
| 682 | log_end(Commit_unit,FUNCTION); |
---|
| 683 | }; |
---|
| 684 | |
---|
| 685 | }; // end namespace commit_unit |
---|
| 686 | }; // end namespace ooo_engine |
---|
| 687 | }; // end namespace multi_ooo_engine |
---|
| 688 | }; // end namespace core |
---|
| 689 | |
---|
| 690 | }; // end namespace behavioural |
---|
| 691 | }; // end namespace morpheo |
---|
| 692 | #endif |
---|