Changeset 100 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
Legend:
- Unmodified
- Added
- Removed
-
trunk
-
Property
svn:ignore
set to
Makefile.flags
Makefile.tools
Makefile.tools_path
-
Property
svn:ignore
set to
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r98 r100 26 26 if (PORT_READ(in_NRESET) == 0) 27 27 { 28 // Clear all bank 28 29 for (uint32_t i=0; i<_param->_nb_bank; i++) 29 30 { … … 32 33 } 33 34 35 // Reset pointer 34 36 reg_NUM_BANK_HEAD = 0; 35 37 reg_NUM_BANK_TAIL = 0; 36 38 39 // Reset counter 37 40 for (uint32_t i=0; i<_param->_nb_front_end; i++) 38 41 for (uint32_t j=0; j<_param->_nb_context [i]; j++) … … 40 43 reg_NB_INST_COMMIT_ALL [i][j] = 0; 41 44 reg_NB_INST_COMMIT_MEM [i][j] = 0; 45 46 reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; 42 47 } 43 48 49 // Reset priority algorithm 44 50 _priority_insert->reset(); 45 51 } 46 52 else 47 53 { 48 // next priority54 // Compute next priority 49 55 _priority_insert->transition(); 56 57 // =================================================================== 58 // =====[ GARBAGE COLLECTOR ]========================================= 59 // =================================================================== 60 for (uint32_t i=0; i<_param->_nb_front_end; i++) 61 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 62 switch (reg_EVENT_STATE [i][j]) 63 { 64 case EVENT_STATE_EVENT : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break; 65 case EVENT_STATE_END : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break; 66 // case EVENT_STATE_NO_EVENT : 67 // case EVENT_STATE_WAITEND : 68 default : break; 69 } 50 70 51 71 // =================================================================== … … 55 75 if (internal_BANK_INSERT_VAL [i]) 56 76 { 77 // get rename unit source and instruction. 57 78 uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; 58 79 uint32_t y = internal_BANK_INSERT_NUM_INST [i]; … … 67 88 #endif 68 89 90 // get information 69 91 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; 70 92 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; 71 93 Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); 72 94 Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); 95 bool is_store = is_operation_memory_store(operation); 96 73 97 Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); 74 98 … … 78 102 log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); 79 103 log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); 80 104 105 // Create new entry. 81 106 entry_t * entry = new entry_t; 82 107 … … 92 117 entry->exception = exception; 93 118 entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); 94 entry->use_store_queue = (type == TYPE_MEMORY) and ( is_ operation_memory_store(operation));95 entry->use_load_queue = (type == TYPE_MEMORY) and (not is_ operation_memory_store(operation));119 entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store); 120 entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store); 96 121 entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); 97 122 entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; … … 114 139 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 115 140 141 // Test if exception : 142 // * yes : no execute instruction, wait ROB Head 143 // * no : test type 144 // * BRANCH : l.j -> branch is ended 145 // other -> wait the execution end of branchment 146 // * MEMORY : store -> wait store is at head of ROB 147 // other -> wait end of instruction 148 // * OTHER 116 149 if (exception == EXCEPTION_NONE) 117 150 { … … 124 157 { 125 158 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} 126 case TYPE_MEMORY : {entry->state= ROB_STORE_WAIT_HEAD_OK; break;}159 case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} 127 160 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 128 161 } … … 130 163 else 131 164 { 165 // Have an exception : wait head of ROB 166 132 167 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 133 168 … … 135 170 } 136 171 172 // Push in rob 137 173 _rob[i].push_back(entry); 138 174 139 // Update nb_inst175 // Update counter and pointer 140 176 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; 141 177 if (type == TYPE_MEMORY) … … 160 196 if (internal_BANK_COMMIT_VAL [i][j]) 161 197 { 198 // An instruction is executed. Change state of this instruction 199 162 200 uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; 163 201 … … 171 209 #endif 172 210 173 // Tpacket_t packet_id = (_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0;174 175 211 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); 176 // log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",(_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0);177 // log_printf(TRACE,Commit_unit,FUNCTION," * num_entry : %d",packet_id);178 179 // test pandex with ptr_write.180 // Tpacket_t index = (packet_id<reg_BANK_PTR [i])?(reg_BANK_PTR [i]-packet_id):(_param->_size_bank+reg_BANK_PTR [i]-packet_id);181 212 182 213 // find the good entry !!! 183 entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];184 185 //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);186 //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);187 Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);188 189 rob_state_t state = entry->state;190 Tcontext_t front_end_id = entry->front_end_id;191 Tcontext_t context_id = entry->context_id;192 193 // change state 214 entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; 215 216 //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); 217 //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); 218 Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); 219 220 rob_state_t state = entry->state; 221 Tcontext_t front_end_id = entry->front_end_id; 222 Tcontext_t context_id = entry->context_id; 223 224 // change state : test exception_use 194 225 // * test if exception : exception and mask 195 226 196 bool have_exception = false; 197 227 bool have_exception = false; 228 bool have_miss_speculation = false; 229 198 230 if (exception != EXCEPTION_NONE) 199 switch (entry->exception_use) 200 { 201 case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} 202 case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 203 (exception == EXCEPTION_DATA_TLB ) or 204 (exception == EXCEPTION_DATA_PAGE) or 205 (exception == EXCEPTION_ALIGNMENT)); break;}; 206 case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 207 (exception == EXCEPTION_DATA_TLB ) or 208 (exception == EXCEPTION_DATA_PAGE)); break;}; 209 case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 210 case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 211 case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 212 case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 213 case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 214 case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 215 case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 216 case EXCEPTION_USE_TRAP : {have_exception = false; break;}; 217 case EXCEPTION_USE_NONE : {have_exception = false; break;}; 218 case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; break;}; 219 case EXCEPTION_USE_SYSCALL : {have_exception = false; break;}; 220 default : 221 { 222 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); 223 break; 224 } 225 } 226 227 if (not have_exception) 228 { 229 switch (state) 230 { 231 case ROB_OTHER_WAIT_END : {state = ROB_END_OK_SPECULATIVE; break;} 232 case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE ; break;} 233 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 234 default : 235 { 236 throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); 237 break; 238 } 239 } 240 // can have an exception, but this instruction is not sensible a this exception 241 exception = EXCEPTION_NONE; 242 } 243 else 244 { 245 #ifdef DEBUG_TEST 246 if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) 247 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n")); 248 #endif 249 250 switch (state) 251 { 252 case ROB_OTHER_WAIT_END : 253 case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;} 254 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE ; break;} 255 default : 256 { 257 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n")); 258 break; 259 } 260 } 261 } 231 { 232 // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) 233 have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); 234 235 switch (entry->exception_use) 236 { 237 // Have overflow exception if bit overflow enable is set. 238 case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} 239 case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 240 (exception == EXCEPTION_DATA_TLB ) or 241 (exception == EXCEPTION_DATA_PAGE) or 242 (exception == EXCEPTION_ALIGNMENT)); break;}; 243 case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 244 (exception == EXCEPTION_DATA_TLB ) or 245 (exception == EXCEPTION_DATA_PAGE)); break;}; 246 case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 247 case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 248 case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 249 case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 250 case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 251 case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 252 case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 253 // Case already manage (decod stage -> in insert in ROB) 254 case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; 255 case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; 256 case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; 257 case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; 258 default : 259 { 260 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); 261 break; 262 } 263 } 264 } 265 266 switch (state) 267 { 268 // Branch ... 269 case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} 270 // Store KO 271 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 272 // Store OK, Load and other instruction 273 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;} 274 default : 275 { 276 throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); 277 break; 278 } 279 } 262 280 263 281 // update Re Order Buffer … … 287 305 288 306 entry_t * entry = _rob [i].front(); 307 rob_state_t state = entry->state; 308 289 309 #ifdef STATISTICS 290 310 if (usage_is_set(_usage,USE_STATISTICS)) 291 311 { 292 rob_state_t state = entry->state;293 294 312 if (state == ROB_END_OK) 295 313 (*_stat_nb_inst_retire_ok [x]) ++; … … 302 320 Tcontext_t context_id = entry->context_id ; 303 321 Ttype_t type = entry->type ; 322 323 if (state == ROB_END_BRANCH_MISS) 324 { 325 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 326 327 // !!!!!!!!!!! Compute address 328 } 304 329 305 330 // Update nb_inst … … 307 332 if (type == TYPE_MEMORY) 308 333 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 309 334 335 if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0) 336 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END; 337 310 338 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; 311 339 … … 350 378 #endif 351 379 352 entry->state = ROB_END_OK_SPECULATIVE; 380 entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE; 381 // entry->state = ROB_END_OK_SPECULATIVE; 353 382 } 354 383 355 384 // =================================================================== 385 // =====[ UPDATE ]==================================================== 386 // =================================================================== 387 { 388 // Not yet implemented 389 } 390 391 // =================================================================== 356 392 // =====[ EVENT ]===================================================== 357 393 // =================================================================== 394 { 395 // Not yet implemented 396 } 358 397 359 398 // =================================================================== … … 400 439 switch (state) 401 440 { 402 case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 403 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 404 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 405 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 406 case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 407 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 408 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 409 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 410 411 // don't change 412 case ROB_STORE_HEAD_KO : {break;} 413 case ROB_MISS_WAIT_END : {break;} 414 case ROB_END_MISS : {break;} 415 416 // can't have miss speculation 417 case ROB_STORE_HEAD_OK : 418 case ROB_END_OK : 419 case ROB_END_KO : 420 case ROB_END_EXCEPTION : 421 default : 441 case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 442 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 443 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 444 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 445 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 446 case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 447 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 448 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 449 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 450 451 // don't change 452 case ROB_STORE_HEAD_KO : {break;} 453 case ROB_MISS_WAIT_END : {break;} 454 case ROB_END_MISS : {break;} 455 456 // can't have miss speculation 457 case ROB_STORE_HEAD_OK : 458 case ROB_END_OK : 459 case ROB_END_KO : 460 case ROB_END_BRANCH_MISS : 461 case ROB_END_EXCEPTION : 462 default : 422 463 { 423 464 throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); … … 434 475 switch (state) 435 476 { 436 case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} 437 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 477 case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} 478 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 479 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 438 480 default : {break;} 439 481 } … … 519 561 (*it)->num_reg_re_phy_new ); 520 562 521 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x %s",563 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x", 522 564 (*it)->exception , 523 565 (*it)->exception_use , 524 566 (*it)->flags , 525 567 (*it)->no_sequence , 526 (*it)->data_commit , 527 toString((*it)->event_state).c_str() 568 (*it)->data_commit 528 569 ); 529 570
Note: See TracChangeset
for help on using the changeset viewer.