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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 100

Last change on this file since 100 was 100, checked in by rosiere, 15 years ago
1) Bug fix (Operation, Instruction) 2) Modif Return Address Stack 3) Add Soft Test 4) Add Soc Test
Property svn:keywords set to `Id`
File size: 26.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 100 2009-01-08 13:06:27Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace commit_unit {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::transition"
21	void Commit_unit::transition (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Clear all bank
29	for (uint32_t i=0; i<_param->_nb_bank; i++)
30	{
31	_rob [i].clear();
32	reg_BANK_PTR [i] = 0;
33	}
34
35	// Reset pointer
36	reg_NUM_BANK_HEAD = 0;
37	reg_NUM_BANK_TAIL = 0;
38
39	// Reset counter
40	for (uint32_t i=0; i<_param->_nb_front_end; i++)
41	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
42	{
43	reg_NB_INST_COMMIT_ALL [i][j] = 0;
44	reg_NB_INST_COMMIT_MEM [i][j] = 0;
45
46	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
47	}
48
49	// Reset priority algorithm
50	_priority_insert->reset();
51	}
52	else
53	{
54	// Compute next priority
55	_priority_insert->transition();
56
57	// ===================================================================
58	// =====[ GARBAGE COLLECTOR ]=========================================
59	// ===================================================================
60	for (uint32_t i=0; i<_param->_nb_front_end; i++)
61	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
62	switch (reg_EVENT_STATE [i][j])
63	{
64	case EVENT_STATE_EVENT : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break;
65	case EVENT_STATE_END : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break;
66	// case EVENT_STATE_NO_EVENT :
67	// case EVENT_STATE_WAITEND :
68	default : break;
69	}
70
71	// ===================================================================
72	// =====[ INSERT ]====================================================
73	// ===================================================================
74	for (uint32_t i=0; i<_param->_nb_bank; i++)
75	if (internal_BANK_INSERT_VAL [i])
76	{
77	// get rename unit source and instruction.
78	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
79	uint32_t y = internal_BANK_INSERT_NUM_INST [i];
80
81	if (PORT_READ(in_INSERT_VAL [x][y]))
82	{
83	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
84
85	#ifdef STATISTICS
86	if (usage_is_set(_usage,USE_STATISTICS))
87	(*_stat_nb_inst_insert [x]) ++;
88	#endif
89
90	// get information
91	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
92	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
93	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
94	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
95	bool is_store = is_operation_memory_store(operation);
96
97	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
98
99	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
100	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
101	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
102	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
103	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
104
105	// Create new entry.
106	entry_t * entry = new entry_t;
107
108	entry->ptr = reg_BANK_PTR [i];
109	entry->front_end_id = front_end_id;
110	entry->context_id = context_id ;
111	entry->rename_unit_id = x;
112	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
113	entry->type = type;
114	entry->operation = operation;
115	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
116	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
117	entry->exception = exception;
118	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
119	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store);
120	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store);
121	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
122	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
123	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
124	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
125	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
126	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
127	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
128	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
129	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
130	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
131	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
132	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
133	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
134	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
135	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
136	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
137	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
138	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
139	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
140
141	// Test if exception :
142	// * yes : no execute instruction, wait ROB Head
143	// * no : test type
144	// * BRANCH : l.j -> branch is ended
145	// other -> wait the execution end of branchment
146	// * MEMORY : store -> wait store is at head of ROB
147	// other -> wait end of instruction
148	// * OTHER
149	if (exception == EXCEPTION_NONE)
150	{
151	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
152	// no_execute : l.j, l.nop, l.rfe
153
154	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
155
156	switch (type)
157	{
158	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;}
159	case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
160	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
161	}
162	}
163	else
164	{
165	// Have an exception : wait head of ROB
166
167	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
168
169	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
170	}
171
172	// Push in rob
173	_rob[i].push_back(entry);
174
175	// Update counter and pointer
176	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
177	if (type == TYPE_MEMORY)
178	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
179
180	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
181	reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank;
182	}
183	}
184
185	// ===================================================================
186	// =====[ COMMIT ]====================================================
187	// ===================================================================
188
189	#ifdef STATISTICS
190	if (usage_is_set(_usage,USE_STATISTICS))
191	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
192	#endif
193
194	for (uint32_t i=0; i<_param->_nb_bank; i++)
195	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
196	if (internal_BANK_COMMIT_VAL [i][j])
197	{
198	// An instruction is executed. Change state of this instruction
199
200	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
201
202	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
203	{
204	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
205
206	#ifdef STATISTICS
207	if (usage_is_set(_usage,USE_STATISTICS))
208	(*_stat_nb_inst_commit) ++;
209	#endif
210
211	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
212
213	// find the good entry !!!
214	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
215
216	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
217	//Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);
218	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
219
220	rob_state_t state = entry->state;
221	Tcontext_t front_end_id = entry->front_end_id;
222	Tcontext_t context_id = entry->context_id;
223
224	// change state : test exception_use
225	// * test if exception : exception and mask
226
227	bool have_exception = false;
228	bool have_miss_speculation = false;
229
230	if (exception != EXCEPTION_NONE)
231	{
232	// Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
233	have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
234
235	switch (entry->exception_use)
236	{
237	// Have overflow exception if bit overflow enable is set.
238	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
239	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
240	(exception == EXCEPTION_DATA_TLB ) or
241	(exception == EXCEPTION_DATA_PAGE) or
242	(exception == EXCEPTION_ALIGNMENT)); break;};
243	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
244	(exception == EXCEPTION_DATA_TLB ) or
245	(exception == EXCEPTION_DATA_PAGE)); break;};
246	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
247	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
248	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
249	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
250	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
251	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
252	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
253	// Case already manage (decod stage -> in insert in ROB)
254	case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;};
255	case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;};
256	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;};
257	case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;};
258	default :
259	{
260	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
261	break;
262	}
263	}
264	}
265
266	switch (state)
267	{
268	// Branch ...
269	case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
270	// Store KO
271	case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;}
272	// Store OK, Load and other instruction
273	case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;}
274	default :
275	{
276	throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
277	break;
278	}
279	}
280
281	// update Re Order Buffer
282	entry->state = state;
283	entry->exception = exception;
284	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
285	entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
286	entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]);
287	}
288	}
289
290	// ===================================================================
291	// =====[ RETIRE ]====================================================
292	// ===================================================================
293	for (uint32_t i=0; i<_param->_nb_bank; i++)
294	if (internal_BANK_RETIRE_VAL [i])
295	{
296	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i];
297	uint32_t y = internal_BANK_RETIRE_NUM_INST [i];
298
299	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
300
301	#ifdef DEBUG_TEST
302	if (not PORT_READ(in_RETIRE_ACK [x][y]))
303	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
304	#endif
305
306	entry_t * entry = _rob [i].front();
307	rob_state_t state = entry->state;
308
309	#ifdef STATISTICS
310	if (usage_is_set(_usage,USE_STATISTICS))
311	{
312	if (state == ROB_END_OK)
313	(*_stat_nb_inst_retire_ok [x]) ++;
314	else
315	(*_stat_nb_inst_retire_ko [x]) ++;
316	}
317	#endif
318
319	Tcontext_t front_end_id = entry->front_end_id;
320	Tcontext_t context_id = entry->context_id ;
321	Ttype_t type = entry->type ;
322
323	if (state == ROB_END_BRANCH_MISS)
324	{
325	reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
326
327	// !!!!!!!!!!! Compute address
328	}
329
330	// Update nb_inst
331	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
332	if (type == TYPE_MEMORY)
333	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
334
335	if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0)
336	reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END;
337
338	reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
339
340	_rob [i].pop_front();
341	delete entry;
342	}
343
344	// ===================================================================
345	// =====[ REEXECUTE ]=================================================
346	// ===================================================================
347	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
348	{
349	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
350
351	entry_t * entry = _rob [num_bank].front();
352	rob_state_t state = entry->state;
353
354	switch (state)
355	{
356	case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
357	case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; }
358	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
359	}
360
361	entry->state = state;
362	}
363
364	// ===================================================================
365	// =====[ BRANCH_COMPLETE ]===========================================
366	// ===================================================================
367	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
368	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
369	{
370	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
371
372	entry_t * entry = _rob [num_bank].front();
373
374	#ifdef DEBUG_TEST
375	rob_state_t state = entry->state;
376	if (state != ROB_BRANCH_COMPLETE)
377	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
378	#endif
379
380	entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE;
381	// entry->state = ROB_END_OK_SPECULATIVE;
382	}
383
384	// ===================================================================
385	// =====[ UPDATE ]====================================================
386	// ===================================================================
387	{
388	// Not yet implemented
389	}
390
391	// ===================================================================
392	// =====[ EVENT ]=====================================================
393	// ===================================================================
394	{
395	// Not yet implemented
396	}
397
398	// ===================================================================
399	// =====[ DEPTH - HEAD ]==============================================
400	// ===================================================================
401	for (uint32_t i=0; i<_param->_nb_bank; i++)
402	if (not _rob[i].empty())
403	{
404	// Scan all instruction in windows and test if instruction is speculative
405	entry_t * entry = _rob [i].front();
406
407	Tcontext_t front_end_id = entry->front_end_id;
408	Tcontext_t context_id = entry->context_id ;
409	rob_state_t state = entry->state;
410	Tdepth_t depth = entry->depth;
411
412	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [front_end_id][context_id]):0;
413	Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[front_end_id][context_id]);
414
415	// is a valid instruction ?
416	// If DEPTH_CURRENT :
417	// equal at DEPTH_MIN -> not speculative
418	// not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss
419	// include ]DEPTH_MIN:DEPTH_MAX[ -> speculative
420
421	// All case
422	// ....... min ...X... max ....... OK
423	// ....... min ....... max ...X... KO
424	// ...X... min ....... max ....... KO
425	// ....... max ....... min ...X... OK
426	// ...X... max ....... min ....... OK
427	// ....... max ...X... min ....... KO
428
429	Tcontrol_t is_valid = ((depth == depth_min) or
430	((depth_min < depth_max)?
431	(depth<depth_max):
432	((depth > depth_min) or (depth < depth_max))));
433
434	//------------------------------------------------------
435	// test if instruction is miss speculative
436	//------------------------------------------------------
437	if (not is_valid)
438	{
439	switch (state)
440	{
441	case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
442	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
443	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
444	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;}
445	//case ROB_STORE_WAIT_HEAD_KO : {state = ; break;}
446	case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
447	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
448	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
449	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
450
451	// don't change
452	case ROB_STORE_HEAD_KO : {break;}
453	case ROB_MISS_WAIT_END : {break;}
454	case ROB_END_MISS : {break;}
455
456	// can't have miss speculation
457	case ROB_STORE_HEAD_OK :
458	case ROB_END_OK :
459	case ROB_END_KO :
460	case ROB_END_BRANCH_MISS :
461	case ROB_END_EXCEPTION :
462	default :
463	{
464	throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n"));
465	break;
466	}
467	}
468	}
469
470	//------------------------------------------------------
471	// test if instruction is not speculative
472	//------------------------------------------------------
473	if (entry->depth == depth_min)
474	{
475	switch (state)
476	{
477	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
478	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
479	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
480	default : {break;}
481	}
482	}
483
484	//------------------------------------------------------
485	// test if instruction is store and head
486	//------------------------------------------------------
487	if (i == reg_NUM_BANK_HEAD)
488	{
489	switch (state)
490	{
491	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
492	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;}
493	default : {break;}
494	}
495	}
496
497	entry->state = state;
498	}
499	}
500
501	// ===================================================================
502	// =====[ OTHER ]=====================================================
503	// ===================================================================
504
505	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
506	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
507	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
508
509	for (uint32_t i=0; i<_param->_nb_front_end; i++)
510	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
511	log_printf(TRACE,Commit_unit,FUNCTION," * num_inst[%d][%d] all : %d, mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]);
512
513	for (uint32_t i=0; i<_param->_nb_bank; i++)
514	{
515	log_printf(TRACE,Commit_unit,FUNCTION," * Bank[%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]);
516
517	#ifdef STATISTICS
518	if (usage_is_set(_usage,USE_STATISTICS))
519	*(_stat_bank_nb_inst [i]) += _rob[i].size();
520	#endif
521
522	uint32_t x=0;
523	for (std::list<entry_t*>::iterator it=_rob[i].begin();
524	it!=_rob[i].end();
525	it++)
526	{
527	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
528	x,
529	(*it)->front_end_id ,
530	(*it)->context_id ,
531	(*it)->rename_unit_id ,
532	(*it)->depth ,
533	(*it)->type ,
534	(*it)->operation ,
535	(*it)->address ,
536	(*it)->address << 2 ,
537	(*it)->is_delay_slot ,
538	(*it)->use_store_queue ,
539	(*it)->store_queue_ptr_write ,
540	(*it)->use_load_queue ,
541	(*it)->load_queue_ptr_write ,
542	toString((*it)->state).c_str() ,
543	(*it)->ptr );
544	log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.1d %.6d %.6d, %.1d %.1d %.6d %.6d ",
545	(*it)->read_ra ,
546	(*it)->num_reg_ra_log ,
547	(*it)->num_reg_ra_phy ,
548	(*it)->read_rb ,
549	(*it)->num_reg_rb_log ,
550	(*it)->num_reg_rb_phy ,
551	(*it)->read_rc ,
552	(*it)->num_reg_rc_log ,
553	(*it)->num_reg_rc_phy ,
554	(*it)->write_rd ,
555	(*it)->num_reg_rd_log ,
556	(*it)->num_reg_rd_phy_old ,
557	(*it)->num_reg_rd_phy_new ,
558	(*it)->write_re ,
559	(*it)->num_reg_re_log ,
560	(*it)->num_reg_re_phy_old ,
561	(*it)->num_reg_re_phy_new );
562
563	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x",
564	(*it)->exception ,
565	(*it)->exception_use ,
566	(*it)->flags ,
567	(*it)->no_sequence ,
568	(*it)->data_commit
569	);
570
571	x++;
572	}
573	}
574
575	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
576	end_cycle ();
577	#endif
578
579	log_end(Commit_unit,FUNCTION);
580	};
581
582	}; // end namespace commit_unit
583	}; // end namespace ooo_engine
584	}; // end namespace multi_ooo_engine
585	}; // end namespace core
586
587	}; // end namespace behavioural
588	}; // end namespace morpheo
589	#endif

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