1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Dependency_checking_unit_genMealy.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Dependency_checking_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace rename_unit { |
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17 | namespace register_translation_unit { |
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18 | namespace dependency_checking_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Dependency_checking_unit::genMealy" |
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23 | void Dependency_checking_unit::genMealy (void) |
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24 | { |
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25 | log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); |
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26 | |
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27 | // Tcontrol_t val [_param->_nb_inst_insert]; |
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28 | // Tcontrol_t ack [_param->_nb_inst_insert]; |
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29 | Tcontext_t front_end_id [_param->_nb_inst_insert]; |
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30 | Tcontext_t context_id [_param->_nb_inst_insert]; |
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31 | Tcontrol_t read_ra [_param->_nb_inst_insert]; |
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32 | Tgeneral_address_t num_reg_ra_log [_param->_nb_inst_insert]; |
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33 | Tgeneral_address_t num_reg_ra_phy [_param->_nb_inst_insert]; |
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34 | Tcontrol_t read_rb [_param->_nb_inst_insert]; |
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35 | Tgeneral_address_t num_reg_rb_log [_param->_nb_inst_insert]; |
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36 | Tgeneral_address_t num_reg_rb_phy [_param->_nb_inst_insert]; |
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37 | Tcontrol_t read_rc [_param->_nb_inst_insert]; |
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38 | Tspecial_address_t num_reg_rc_log [_param->_nb_inst_insert]; |
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39 | Tspecial_address_t num_reg_rc_phy [_param->_nb_inst_insert]; |
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40 | Tcontrol_t write_rd [_param->_nb_inst_insert]; |
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41 | Tgeneral_address_t num_reg_rd_log [_param->_nb_inst_insert]; |
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42 | Tgeneral_address_t num_reg_rd_phy_old [_param->_nb_inst_insert]; |
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43 | Tgeneral_address_t num_reg_rd_phy_new [_param->_nb_inst_insert]; |
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44 | Tcontrol_t write_re [_param->_nb_inst_insert]; |
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45 | Tspecial_address_t num_reg_re_log [_param->_nb_inst_insert]; |
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46 | Tspecial_address_t num_reg_re_phy_old [_param->_nb_inst_insert]; |
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47 | Tspecial_address_t num_reg_re_phy_new [_param->_nb_inst_insert]; |
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48 | |
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49 | // 4 dependency : |
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50 | // * Read after Read : it's a false dependency |
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51 | // * Write after Read : it's inhibt by rename process |
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52 | // * Write after Write : for the num_reg_old |
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53 | // * Read after Write : dependency |
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54 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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55 | { |
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56 | // =====[ Input ]================================================== |
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57 | // val [i] = PORT_READ(in_RENAME_IN_VAL [i]); |
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58 | // ack [i] = PORT_READ(in_RENAME_OUT_ACK [i]); |
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59 | front_end_id [i] = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [i]):0; |
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60 | context_id [i] = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [i]):0; |
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61 | read_ra [i] = PORT_READ(in_RENAME_IN_READ_RA [i]); |
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62 | num_reg_ra_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_LOG [i]); |
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63 | num_reg_ra_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_PHY [i]); |
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64 | read_rb [i] = PORT_READ(in_RENAME_IN_READ_RB [i]); |
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65 | num_reg_rb_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_LOG [i]); |
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66 | num_reg_rb_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_PHY [i]); |
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67 | read_rc [i] = PORT_READ(in_RENAME_IN_READ_RC [i]); |
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68 | num_reg_rc_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_LOG [i]); |
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69 | num_reg_rc_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_PHY [i]); |
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70 | write_rd [i] = PORT_READ(in_RENAME_IN_WRITE_RD [i]); |
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71 | num_reg_rd_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_LOG [i]); |
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72 | num_reg_rd_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_OLD [i]); |
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73 | num_reg_rd_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_NEW [i]); |
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74 | write_re [i] = PORT_READ(in_RENAME_IN_WRITE_RE [i]); |
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75 | num_reg_re_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_LOG [i]); |
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76 | num_reg_re_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_OLD [i]); |
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77 | num_reg_re_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_NEW [i]); |
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78 | |
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79 | // ================================================================ |
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80 | // =====[ Write after Write ]====================================== |
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81 | // ================================================================ |
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82 | if (write_rd [i]) |
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83 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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84 | for (int32_t j=i-1; j>=0; j--) |
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85 | if ((write_rd [j] == 1 ) and |
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86 | (num_reg_rd_log [j] == num_reg_rd_log [i]) and |
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87 | (front_end_id [j] == front_end_id [i]) and |
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88 | (context_id [j] == context_id [i]) ) |
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89 | { |
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90 | num_reg_rd_phy_old [i] = num_reg_rd_phy_new [j]; |
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91 | break; // find the most recently dependency |
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92 | } |
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93 | |
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94 | if (write_re [i]) |
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95 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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96 | for (int32_t j=i-1; j>=0; j--) |
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97 | if ((write_re [j] == 1 ) and |
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98 | (num_reg_re_log [j] == num_reg_re_log [i]) and |
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99 | (front_end_id [j] == front_end_id [i]) and |
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100 | (context_id [j] == context_id [i]) ) |
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101 | { |
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102 | num_reg_re_phy_old [i] = num_reg_re_phy_new [j]; |
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103 | break; // find the most recently dependency |
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104 | } |
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105 | // ================================================================ |
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106 | // =====[ Read after Write ]====================================== |
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107 | // ================================================================ |
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108 | if (read_ra [i]) |
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109 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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110 | for (int32_t j=i-1; j>=0; j--) |
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111 | if ((write_rd [j] == 1 ) and |
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112 | (num_reg_rd_log [j] == num_reg_ra_log [i]) and |
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113 | (front_end_id [j] == front_end_id [i]) and |
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114 | (context_id [j] == context_id [i]) ) |
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115 | { |
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116 | num_reg_ra_phy [i] = num_reg_rd_phy_new [j]; |
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117 | break; // find the most recently dependency |
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118 | } |
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119 | |
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120 | if (read_rb [i]) |
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121 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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122 | for (int32_t j=i-1; j>=0; j--) |
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123 | if ((write_rd [j] == 1 ) and |
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124 | (num_reg_rd_log [j] == num_reg_rb_log [i]) and |
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125 | (front_end_id [j] == front_end_id [i]) and |
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126 | (context_id [j] == context_id [i]) ) |
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127 | { |
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128 | num_reg_rb_phy [i] = num_reg_rd_phy_new [j]; |
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129 | break; // find the most recently dependency |
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130 | } |
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131 | |
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132 | if (read_rc [i]) |
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133 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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134 | for (int32_t j=i-1; j>=0; j--) |
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135 | if ((write_re [j] == 1 ) and |
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136 | (num_reg_re_log [j] == num_reg_rc_log [i]) and |
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137 | (front_end_id [j] == front_end_id [i]) and |
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138 | (context_id [j] == context_id [i]) ) |
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139 | { |
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140 | num_reg_rc_phy [i] = num_reg_re_phy_new [j]; |
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141 | break; // find the most recently dependency |
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142 | } |
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143 | |
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144 | // =====[ Output ]================================================= |
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145 | // PORT_WRITE(out_RENAME_OUT_VAL [i], val [i]); |
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146 | // PORT_WRITE(out_RENAME_IN_ACK [i], ack [i]); |
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147 | if (_param->_have_port_front_end_id) |
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148 | PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i], front_end_id [i]); |
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149 | if (_param->_have_port_context_id) |
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150 | PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i], context_id [i]); |
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151 | PORT_WRITE(out_RENAME_OUT_READ_RA [i], read_ra [i]); |
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152 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_LOG [i], num_reg_ra_log [i]); |
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153 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_PHY [i], num_reg_ra_phy [i]); |
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154 | PORT_WRITE(out_RENAME_OUT_READ_RB [i], read_rb [i]); |
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155 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_LOG [i], num_reg_rb_log [i]); |
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156 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_PHY [i], num_reg_rb_phy [i]); |
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157 | PORT_WRITE(out_RENAME_OUT_READ_RC [i], read_rc [i]); |
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158 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_LOG [i], num_reg_rc_log [i]); |
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159 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_PHY [i], num_reg_rc_phy [i]); |
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160 | PORT_WRITE(out_RENAME_OUT_WRITE_RD [i], write_rd [i]); |
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161 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_LOG [i], num_reg_rd_log [i]); |
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162 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old [i]); |
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163 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_NEW [i], num_reg_rd_phy_new [i]); |
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164 | PORT_WRITE(out_RENAME_OUT_WRITE_RE [i], write_re [i]); |
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165 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_LOG [i], num_reg_re_log [i]); |
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166 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old [i]); |
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167 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_NEW [i], num_reg_re_phy_new [i]); |
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168 | } |
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169 | |
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170 | log_printf(FUNC,Dependency_checking_unit,FUNCTION,"End"); |
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171 | }; |
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172 | |
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173 | }; // end namespace dependency_checking_unit |
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174 | }; // end namespace register_translation_unit |
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175 | }; // end namespace rename_unit |
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176 | }; // end namespace ooo_engine |
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177 | }; // end namespace multi_ooo_engine |
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178 | }; // end namespace core |
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179 | }; // end namespace behavioural |
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180 | }; // end namespace morpheo |
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181 | #endif |
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