1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Free_List_unit_genMealy_pop.cpp 109 2009-02-16 20:28:31Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace rename_unit { |
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17 | namespace register_translation_unit { |
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18 | namespace free_list_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Free_List_unit::genMealy_pop" |
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23 | void Free_List_unit::genMealy_pop (void) |
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24 | { |
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25 | log_begin(Free_List_unit,FUNCTION); |
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26 | log_function(Free_List_unit,FUNCTION,_name.c_str()); |
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27 | |
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28 | std::list<generic::priority::select_t> * select_gpr = _priority_gpr->select(); |
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29 | std::list<generic::priority::select_t>::iterator it_gpr=select_gpr->begin(); |
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30 | |
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31 | std::list<generic::priority::select_t> * select_spr = _priority_spr->select(); |
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32 | std::list<generic::priority::select_t>::iterator it_spr=select_spr->begin(); |
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33 | |
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34 | for (uint32_t i=0; i<_param->_nb_pop; i++) |
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35 | { |
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36 | log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); |
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37 | |
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38 | // GPR |
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39 | bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); |
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40 | |
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41 | log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); |
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42 | |
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43 | if (not gpr_ack) |
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44 | { |
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45 | // scan all bank |
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46 | for (; |
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47 | it_gpr!=select_gpr->end(); |
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48 | ++it_gpr) |
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49 | { |
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50 | uint32_t num_bank = it_gpr->grp; |
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51 | |
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52 | log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); |
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53 | |
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54 | if (not _gpr_list[num_bank].empty()) |
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55 | { |
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56 | // find |
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57 | log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[num_bank].front()); |
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58 | |
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59 | gpr_ack = true; |
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60 | internal_POP_GPR_BANK [i] = num_bank; |
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61 | PORT_WRITE(out_POP_GPR_NUM_REG [i], |
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62 | //(num_bank << _param->_shift) | // only in VHDL |
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63 | _gpr_list[num_bank].front()); |
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64 | |
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65 | ++it_gpr; |
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66 | break; |
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67 | } |
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68 | } |
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69 | } |
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70 | |
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71 | // SPR |
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72 | bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); |
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73 | |
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74 | log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); |
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75 | |
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76 | if (not spr_ack) |
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77 | { |
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78 | // scan all bank |
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79 | for (; |
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80 | it_spr!=select_spr->end(); |
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81 | ++it_spr) |
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82 | { |
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83 | uint32_t num_bank = it_spr->grp; |
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84 | |
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85 | log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); |
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86 | |
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87 | if (not _spr_list[num_bank].empty()) |
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88 | { |
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89 | // find |
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90 | log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[num_bank].front()); |
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91 | |
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92 | spr_ack = true; |
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93 | internal_POP_SPR_BANK [i] = num_bank; |
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94 | PORT_WRITE(out_POP_SPR_NUM_REG [i], |
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95 | //(num_bank << _param->_shift) | // only in VHDL |
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96 | _spr_list[num_bank].front()); |
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97 | |
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98 | ++it_spr; |
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99 | break; |
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100 | } |
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101 | } |
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102 | } |
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103 | |
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104 | |
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105 | internal_POP_ACK [i] = gpr_ack and spr_ack; |
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106 | PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); |
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107 | } |
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108 | |
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109 | // for (uint32_t i=0; i<_param->_nb_pop; i++) |
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110 | // { |
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111 | // log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); |
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112 | |
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113 | // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; |
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114 | |
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115 | // // GPR |
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116 | // bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); |
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117 | |
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118 | // log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); |
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119 | |
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120 | // if (not gpr_ack) |
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121 | // { |
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122 | // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) |
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123 | // { |
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124 | // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; |
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125 | |
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126 | // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); |
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127 | |
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128 | // if (not _gpr_list[bank].empty()) |
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129 | // { |
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130 | // // find |
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131 | // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); |
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132 | |
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133 | // gpr_ack = true; |
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134 | // internal_POP_GPR_BANK [i] = bank; |
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135 | // PORT_WRITE(out_POP_GPR_NUM_REG [i], |
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136 | // //(bank << _param->_shift) | // only in VHDL |
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137 | // _gpr_list[bank].front()); |
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138 | |
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139 | // break; |
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140 | // } |
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141 | // } |
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142 | // } |
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143 | |
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144 | // // SPR |
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145 | // bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); |
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146 | |
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147 | // log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); |
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148 | |
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149 | // if (not spr_ack) |
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150 | // { |
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151 | // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; |
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152 | |
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153 | // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) |
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154 | // { |
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155 | // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; |
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156 | |
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157 | // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); |
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158 | |
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159 | // if (not _spr_list[bank].empty()) |
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160 | // { |
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161 | // // find |
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162 | // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); |
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163 | |
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164 | // spr_ack = true; |
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165 | // internal_POP_SPR_BANK [i] = bank; |
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166 | // PORT_WRITE(out_POP_SPR_NUM_REG [i], |
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167 | // //(bank << _param->_shift) | // only in VHDL |
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168 | // _spr_list[bank].front()); |
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169 | |
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170 | // break; |
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171 | // } |
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172 | // } |
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173 | // } |
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174 | |
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175 | // internal_POP_ACK [i] = gpr_ack and spr_ack; |
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176 | |
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177 | // PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); |
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178 | // } |
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179 | |
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180 | |
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181 | log_end(Free_List_unit,FUNCTION); |
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182 | }; |
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183 | |
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184 | }; // end namespace free_list_unit |
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185 | }; // end namespace register_translation_unit |
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186 | }; // end namespace rename_unit |
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187 | }; // end namespace ooo_engine |
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188 | }; // end namespace multi_ooo_engine |
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189 | }; // end namespace core |
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190 | |
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191 | }; // end namespace behavioural |
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192 | }; // end namespace morpheo |
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193 | #endif |
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