Changeset 109 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp
- Timestamp:
- Feb 16, 2009, 9:28:31 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp
r108 r109 26 26 log_function(Free_List_unit,FUNCTION,_name.c_str()); 27 27 28 std::list<generic::priority::select_t> * select_gpr = _priority_gpr->select(); 29 std::list<generic::priority::select_t>::iterator it_gpr=select_gpr->begin(); 30 31 std::list<generic::priority::select_t> * select_spr = _priority_spr->select(); 32 std::list<generic::priority::select_t>::iterator it_spr=select_spr->begin(); 33 28 34 for (uint32_t i=0; i<_param->_nb_pop; i++) 29 35 { 30 36 log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 31 32 uint32_t offset = i*_param->_nb_bank_by_pop; 33 37 34 38 // GPR 35 39 bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 36 40 37 41 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 38 42 39 43 if (not gpr_ack) 40 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 41 { 42 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop 43 ); 44 45 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 46 47 if (not _gpr_list[bank].empty()) 48 { 49 // find 50 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 51 52 gpr_ack = true; 53 internal_POP_GPR_BANK [i] = bank; 54 PORT_WRITE(out_POP_GPR_NUM_REG [i], 55 //(bank << _param->_shift) | // only in VHDL 56 _gpr_list[bank].front()); 57 58 break; 59 } 60 } 44 { 45 // scan all bank 46 for (; 47 it_gpr!=select_gpr->end(); 48 ++it_gpr) 49 { 50 uint32_t num_bank = it_gpr->grp; 51 52 log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); 53 54 if (not _gpr_list[num_bank].empty()) 55 { 56 // find 57 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[num_bank].front()); 58 59 gpr_ack = true; 60 internal_POP_GPR_BANK [i] = num_bank; 61 PORT_WRITE(out_POP_GPR_NUM_REG [i], 62 //(num_bank << _param->_shift) | // only in VHDL 63 _gpr_list[num_bank].front()); 64 65 ++it_gpr; 66 break; 67 } 68 } 69 } 61 70 62 71 // SPR 63 72 bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 73 74 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 75 76 if (not spr_ack) 77 { 78 // scan all bank 79 for (; 80 it_spr!=select_spr->end(); 81 ++it_spr) 82 { 83 uint32_t num_bank = it_spr->grp; 84 85 log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); 86 87 if (not _spr_list[num_bank].empty()) 88 { 89 // find 90 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[num_bank].front()); 91 92 spr_ack = true; 93 internal_POP_SPR_BANK [i] = num_bank; 94 PORT_WRITE(out_POP_SPR_NUM_REG [i], 95 //(num_bank << _param->_shift) | // only in VHDL 96 _spr_list[num_bank].front()); 97 98 ++it_spr; 99 break; 100 } 101 } 102 } 64 103 65 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i]));66 67 if (not spr_ack)68 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++)69 {70 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop71 );72 73 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank);74 75 if (not _spr_list[bank].empty())76 {77 // find78 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front());79 80 spr_ack = true;81 internal_POP_SPR_BANK [i] = bank;82 PORT_WRITE(out_POP_SPR_NUM_REG [i],83 //(bank << _param->_shift) | // only in VHDL84 _spr_list[bank].front());85 86 break;87 }88 }89 104 90 105 internal_POP_ACK [i] = gpr_ack and spr_ack; 91 92 106 PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); 93 107 } 108 109 // for (uint32_t i=0; i<_param->_nb_pop; i++) 110 // { 111 // log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 112 113 // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; 114 115 // // GPR 116 // bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 117 118 // log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 119 120 // if (not gpr_ack) 121 // { 122 // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 123 // { 124 // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; 125 126 // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 127 128 // if (not _gpr_list[bank].empty()) 129 // { 130 // // find 131 // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 132 133 // gpr_ack = true; 134 // internal_POP_GPR_BANK [i] = bank; 135 // PORT_WRITE(out_POP_GPR_NUM_REG [i], 136 // //(bank << _param->_shift) | // only in VHDL 137 // _gpr_list[bank].front()); 138 139 // break; 140 // } 141 // } 142 // } 143 144 // // SPR 145 // bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 146 147 // log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 148 149 // if (not spr_ack) 150 // { 151 // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; 152 153 // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 154 // { 155 // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; 156 157 // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 158 159 // if (not _spr_list[bank].empty()) 160 // { 161 // // find 162 // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); 163 164 // spr_ack = true; 165 // internal_POP_SPR_BANK [i] = bank; 166 // PORT_WRITE(out_POP_SPR_NUM_REG [i], 167 // //(bank << _param->_shift) | // only in VHDL 168 // _spr_list[bank].front()); 169 170 // break; 171 // } 172 // } 173 // } 174 175 // internal_POP_ACK [i] = gpr_ack and spr_ack; 176 177 // PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); 178 // } 94 179 95 180
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