[139] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Register_Address_Translation_unit_function_depth_save_transition.cpp 145 2010-10-13 18:15:51Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace rename_unit { |
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| 17 | namespace register_translation_unit { |
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| 18 | namespace register_address_translation_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Register_Address_Translation_unit::function_depth_save_transition" |
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| 23 | void Register_Address_Translation_unit::function_depth_save_transition (void) |
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| 24 | { |
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| 25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
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| 26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
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| 27 | |
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| 28 | if (PORT_READ(in_NRESET) == 0) |
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| 29 | { |
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| 30 | uint32_t gpr = 1; |
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| 31 | uint32_t spr = 0; |
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| 32 | |
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| 33 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 34 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 35 | { |
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[145] | 36 | RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; |
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| 37 | RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; |
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| 38 | RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary |
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[139] | 39 | |
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| 40 | for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) |
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[145] | 41 | { |
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| 42 | RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; |
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| 43 | for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) |
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| 44 | { |
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| 45 | RAT_GPR_SPECULATIVE_VALID [i][j][l][k] = false; |
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| 46 | RAT_GPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary |
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| 47 | } |
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| 48 | } |
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[139] | 49 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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[145] | 50 | { |
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| 51 | RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; |
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| 52 | for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) |
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| 53 | { |
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| 54 | RAT_SPR_SPECULATIVE_VALID [i][j][l][k] = false; |
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| 55 | RAT_SPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary |
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| 56 | } |
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| 57 | } |
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| 58 | |
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| 59 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 60 | reg_RAT_USE [i][j][k] = false; |
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| 61 | reg_SAVE_RAT [i][j] = false; |
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[139] | 62 | } |
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| 63 | } |
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| 64 | else |
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| 65 | { |
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| 66 | // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) |
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[145] | 67 | bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated]; |
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| 68 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 69 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 70 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 71 | free_rat [i][j][k] = false; |
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[139] | 72 | |
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| 73 | // ===================================================== |
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| 74 | // ====[ RETIRE_EVENT ]================================= |
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| 75 | // ===================================================== |
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| 76 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 77 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 78 | if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) |
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| 79 | { |
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| 80 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j); |
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[145] | 81 | |
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| 82 | // Test if event have just occure |
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| 83 | // * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value) |
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[139] | 84 | |
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| 85 | if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) |
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[145] | 86 | switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) |
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| 87 | { |
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| 88 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
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[139] | 89 | { |
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[145] | 90 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * BRANCH_MISS_SPECULATION - Reset Update Table"); |
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[139] | 91 | |
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[145] | 92 | reg_SAVE_RAT [i][j] = true; |
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| 93 | |
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| 94 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0; |
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| 95 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; |
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| 96 | Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; |
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| 97 | Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); |
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| 98 | |
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| 99 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); |
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| 100 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); |
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| 101 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); |
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| 102 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); |
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[139] | 103 | |
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[145] | 104 | Tdepth_t it = depth_min; |
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| 105 | |
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| 106 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 107 | { |
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| 108 | it = (it-1)%_param->_nb_branch_speculated[i][j]; |
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[139] | 109 | |
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[145] | 110 | if (it == depth) |
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| 111 | break; |
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| 112 | |
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| 113 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",it); |
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| 114 | |
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| 115 | free_rat[i][j][it] = true; |
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| 116 | } |
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| 117 | |
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| 118 | break; |
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[139] | 119 | } |
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[145] | 120 | case EVENT_TYPE_EXCEPTION : |
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| 121 | { |
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| 122 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * EXCEPTION - Reset Update Table"); |
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| 123 | |
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| 124 | reg_SAVE_RAT [i][j] = true; |
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| 125 | |
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| 126 | // Reset validity table |
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| 127 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 128 | free_rat [i][j][k] = true; |
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| 129 | |
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| 130 | break; |
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| 131 | } |
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| 132 | default : |
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| 133 | { |
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| 134 | break; |
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| 135 | } |
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| 136 | } |
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[139] | 137 | } |
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| 138 | |
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| 139 | // ===================================================== |
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| 140 | // ====[ INSERT ]======================================= |
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| 141 | // ===================================================== |
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| 142 | // First : interface insert |
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| 143 | // this instruction is speculative !!! |
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| 144 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 145 | // Test transaction |
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| 146 | if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) |
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| 147 | { |
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| 148 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); |
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| 149 | |
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| 150 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
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| 151 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
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[145] | 152 | Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); |
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| 153 | Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); |
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| 154 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; |
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| 155 | Tcontrol_t save_rat = reg_SAVE_RAT[front_end_id][context_id]; |
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| 156 | // TODO SAVE_RAT |
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[139] | 157 | |
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| 158 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); |
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| 159 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); |
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[145] | 160 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); |
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| 161 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",save_rat); |
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[139] | 162 | |
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[145] | 163 | if (save_rat) |
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| 164 | { |
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| 165 | // #ifdef DEBUG_TEST |
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| 166 | // if (reg_RAT_USE[front_end_id][context_id][depth]) |
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| 167 | // throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth)); |
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| 168 | // #endif |
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| 169 | reg_RAT_USE[front_end_id][context_id][depth] = true; |
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| 170 | |
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| 171 | // new branch, new RAT |
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| 172 | for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) |
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| 173 | RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; |
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| 174 | for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) |
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| 175 | RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; |
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| 176 | } |
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[139] | 177 | |
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[145] | 178 | save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); |
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| 179 | reg_SAVE_RAT[front_end_id][context_id] = save_rat; |
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[139] | 180 | |
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[145] | 181 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); |
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| 182 | |
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| 183 | // Test if write and modifie RAT |
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[139] | 184 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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| 185 | if (write_rd == 1) |
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| 186 | { |
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| 187 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]); |
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| 188 | Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); |
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| 189 | |
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| 190 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log); |
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| 191 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); |
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| 192 | |
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[145] | 193 | RAT_GPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy; |
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| 194 | RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true; |
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[139] | 195 | } |
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| 196 | |
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| 197 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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| 198 | if (write_re == 1) |
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| 199 | { |
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| 200 | Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]); |
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| 201 | Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); |
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| 202 | |
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| 203 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log); |
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| 204 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); |
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| 205 | |
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[145] | 206 | RAT_SPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy; |
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| 207 | RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true; |
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[139] | 208 | } |
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| 209 | } |
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| 210 | |
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| 211 | // ===================================================== |
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| 212 | // ====[ RETIRE ]======================================= |
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| 213 | // ===================================================== |
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| 214 | // Second : interface retire |
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[145] | 215 | // if event AND event is exception, restore rat_NOT_SPECULATIVE |
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| 216 | |
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| 217 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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| 218 | if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) |
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| 219 | { |
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[139] | 220 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); |
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| 221 | |
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| 222 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; |
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| 223 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; |
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| 224 | Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); |
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| 225 | Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); |
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| 226 | Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); |
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| 227 | |
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| 228 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 229 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); |
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| 230 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore ); |
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| 231 | |
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| 232 | // Test if write and have not a previous update |
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| 233 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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| 234 | if (write_rd == 1) |
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| 235 | { |
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| 236 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); |
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| 237 | |
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| 238 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); |
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| 239 | |
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| 240 | if (not restore) |
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| 241 | { |
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| 242 | Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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[145] | 243 | |
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[139] | 244 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); |
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| 245 | |
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[145] | 246 | RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; |
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[139] | 247 | } |
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| 248 | } |
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| 249 | |
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| 250 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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| 251 | if (write_re == 1) |
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| 252 | { |
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| 253 | Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); |
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| 254 | |
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| 255 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); |
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| 256 | |
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| 257 | if (not restore) |
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| 258 | { |
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| 259 | Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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| 260 | |
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| 261 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); |
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| 262 | |
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[145] | 263 | RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; |
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[139] | 264 | } |
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| 265 | } |
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[145] | 266 | } |
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[139] | 267 | |
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[145] | 268 | // ===================================================== |
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| 269 | // ====[ DEPTH ]======================================== |
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| 270 | // ===================================================== |
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| 271 | #if 1 |
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| 272 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 273 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 274 | { |
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| 275 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * DEPTH[%d][%d]",i,j); |
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| 276 | |
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| 277 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; |
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| 278 | Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; |
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| 279 | Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); |
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| 280 | |
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| 281 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); |
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| 282 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); |
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| 283 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); |
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| 284 | |
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| 285 | if (not depth_full) |
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| 286 | { |
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| 287 | Tdepth_t depth = depth_max; |
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| 288 | |
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| 289 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 290 | { |
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| 291 | if (depth == depth_min) |
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| 292 | break; |
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| 293 | |
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| 294 | if (reg_RAT_USE[i][j][depth]) |
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| 295 | { |
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| 296 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",depth); |
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| 297 | |
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| 298 | free_rat [i][j][depth] = true; |
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| 299 | // reg_RAT_USE[i][j][depth] = false; |
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| 300 | |
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| 301 | // for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) |
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| 302 | // RAT_GPR_SPECULATIVE_VALID [i][j][depth][l] = false; |
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| 303 | // for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) |
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| 304 | // RAT_SPR_SPECULATIVE_VALID [i][j][depth][l] = false; |
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| 305 | } |
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| 306 | |
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| 307 | depth = (depth+1)%_param->_nb_branch_speculated[i][j]; |
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| 308 | } |
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| 309 | } |
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| 310 | } |
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| 311 | #endif |
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| 312 | // ===================================================== |
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| 313 | // ====[ FREE RAT ]===================================== |
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| 314 | // ===================================================== |
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| 315 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 316 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 317 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 318 | if (free_rat[i][j][k]) |
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| 319 | { |
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| 320 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Free RAT : [%d][%d][%d]",i,j,k); |
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| 321 | |
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| 322 | reg_RAT_USE[i][j][k] = false; |
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| 323 | |
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| 324 | for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) |
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| 325 | RAT_GPR_SPECULATIVE_VALID [i][j][k][l] = false; |
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| 326 | for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) |
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| 327 | RAT_SPR_SPECULATIVE_VALID [i][j][k][l] = false; |
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| 328 | } |
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| 329 | |
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[139] | 330 | } |
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| 331 | |
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| 332 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) |
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| 333 | { |
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| 334 | uint32_t limit = 4; |
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| 335 | |
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| 336 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); |
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| 337 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 338 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 339 | { |
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[145] | 340 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]); |
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| 341 | |
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| 342 | for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) |
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[139] | 343 | { |
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| 344 | std::string str = ""; |
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| 345 | for (uint32_t x=0; x<limit; x++) |
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| 346 | { |
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[145] | 347 | uint32_t index = l+x; |
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[139] | 348 | if (index >= _param->_nb_general_register_logic) |
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| 349 | break; |
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| 350 | else |
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[145] | 351 | str+=toString("GPR[%.4d] - %.5d | ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]); |
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[139] | 352 | } |
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| 353 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 354 | } |
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| 355 | |
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[145] | 356 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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[139] | 357 | { |
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[145] | 358 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); |
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| 359 | |
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| 360 | for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) |
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| 361 | { |
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| 362 | std::string str = ""; |
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| 363 | for (uint32_t x=0; x<limit; x++) |
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| 364 | { |
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| 365 | uint32_t index = l+x; |
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| 366 | if (index >= _param->_nb_general_register_logic) |
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| 367 | break; |
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| 368 | else |
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| 369 | str+=toString("GPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]); |
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| 370 | } |
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| 371 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 372 | } |
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| 373 | } |
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| 374 | |
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| 375 | for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) |
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| 376 | { |
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[139] | 377 | std::string str = ""; |
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| 378 | |
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| 379 | for (uint32_t x=0; x<limit; x++) |
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| 380 | { |
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[145] | 381 | uint32_t index = l+x; |
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[139] | 382 | if (index >= _param->_nb_special_register_logic) |
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| 383 | break; |
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| 384 | else |
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[145] | 385 | str+=toString("SPR[%.4d] - %.5d | ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]); |
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[139] | 386 | } |
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| 387 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 388 | } |
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| 389 | |
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[145] | 390 | |
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| 391 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 392 | { |
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| 393 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); |
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| 394 | |
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| 395 | for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) |
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| 396 | { |
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| 397 | std::string str = ""; |
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| 398 | |
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| 399 | for (uint32_t x=0; x<limit; x++) |
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| 400 | { |
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| 401 | uint32_t index = l+x; |
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| 402 | if (index >= _param->_nb_special_register_logic) |
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| 403 | break; |
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| 404 | else |
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| 405 | str+=toString("SPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]); |
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| 406 | } |
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| 407 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 408 | } |
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| 409 | } |
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[139] | 410 | } |
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| 411 | } |
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| 412 | #endif |
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| 413 | |
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| 414 | log_end(Register_Address_Translation_unit,FUNCTION); |
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| 415 | }; |
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| 416 | |
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| 417 | }; // end namespace register_address_translation_unit |
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| 418 | }; // end namespace register_translation_unit |
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| 419 | }; // end namespace rename_unit |
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| 420 | }; // end namespace ooo_engine |
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| 421 | }; // end namespace multi_ooo_engine |
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| 422 | }; // end namespace core |
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| 423 | |
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| 424 | }; // end namespace behavioural |
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| 425 | }; // end namespace morpheo |
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| 426 | #endif |
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