Changeset 145 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp
- Timestamp:
- Oct 13, 2010, 8:15:51 PM (14 years ago)
- File:
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- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp
r144 r145 34 34 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 35 35 { 36 rat_depth [i][j] = 0; 37 rat_gpr_speculative [i][j][0] = 0; 36 RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; 37 RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; 38 RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary 38 39 39 40 for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) 40 rat_gpr_speculative [i][j][k] = gpr++; 41 { 42 RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; 43 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 44 { 45 RAT_GPR_SPECULATIVE_VALID [i][j][l][k] = false; 46 RAT_GPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary 47 } 48 } 41 49 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 42 rat_spr_speculative [i][j][k] = spr++; // not necessary 50 { 51 RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; 52 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 53 { 54 RAT_SPR_SPECULATIVE_VALID [i][j][l][k] = false; 55 RAT_SPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary 56 } 57 } 58 59 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 60 reg_RAT_USE [i][j][k] = false; 61 reg_SAVE_RAT [i][j] = false; 43 62 } 44 63 } … … 46 65 { 47 66 // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) 67 bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated]; 68 for (uint32_t i=0; i<_param->_nb_front_end; i++) 69 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 70 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 71 free_rat [i][j][k] = false; 48 72 49 73 // ===================================================== … … 55 79 { 56 80 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j); 81 82 // Test if event have just occure 83 // * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value) 57 84 58 // Test if event have just occure59 85 if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) 60 { 61 switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) 86 switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) 87 { 88 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 62 89 { 63 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 64 case EVENT_TYPE_LOAD_MISS_SPECULATION : 65 { 66 // Miss speculation (branch or load) 67 // Restore contexte and update depth 68 69 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * MISS_SPECULATION : Restore RAT"); 70 71 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0; 72 73 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 74 75 // restore GPR 76 for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) 77 rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr]; 78 79 // restore SPR 80 for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) 81 rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr]; 82 83 // update rat_depth 84 rat_depth[i][j] = depth; 85 86 break; 87 } 88 // case EVENT_TYPE_EXCEPTION : 89 // case EVENT_TYPE_SPR_ACCESS : 90 // case EVENT_TYPE_MSYNC : 91 // case EVENT_TYPE_PSYNC : 92 // case EVENT_TYPE_CSYNC : 93 default : 94 { 95 // nothing 96 break; 97 } 90 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * BRANCH_MISS_SPECULATION - Reset Update Table"); 91 92 reg_SAVE_RAT [i][j] = true; 93 94 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0; 95 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; 96 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; 97 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); 98 99 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 100 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); 101 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); 102 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); 103 104 Tdepth_t it = depth_min; 105 106 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 107 { 108 it = (it-1)%_param->_nb_branch_speculated[i][j]; 109 110 if (it == depth) 111 break; 112 113 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",it); 114 115 free_rat[i][j][it] = true; 116 } 117 118 break; 98 119 } 99 100 } 120 case EVENT_TYPE_EXCEPTION : 121 { 122 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * EXCEPTION - Reset Update Table"); 123 124 reg_SAVE_RAT [i][j] = true; 125 126 // Reset validity table 127 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 128 free_rat [i][j][k] = true; 129 130 break; 131 } 132 default : 133 { 134 break; 135 } 136 } 101 137 } 102 138 … … 114 150 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 115 151 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 116 Tcontrol_t save = internal_RENAME_SAVE [i]; 152 Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); 153 Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); 154 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 155 Tcontrol_t save_rat = reg_SAVE_RAT[front_end_id][context_id]; 156 // TODO SAVE_RAT 117 157 118 158 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); 119 159 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); 120 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save : %d",save); 121 122 // Test if write and modifie RAT (RD and RE) 123 124 Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); 125 Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); 126 160 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 161 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",save_rat); 162 163 if (save_rat) 164 { 165 // #ifdef DEBUG_TEST 166 // if (reg_RAT_USE[front_end_id][context_id][depth]) 167 // throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth)); 168 // #endif 169 reg_RAT_USE[front_end_id][context_id][depth] = true; 170 171 // new branch, new RAT 172 for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) 173 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; 174 for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) 175 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; 176 } 177 178 save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); 179 reg_SAVE_RAT[front_end_id][context_id] = save_rat; 180 181 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); 182 183 // Test if write and modifie RAT 127 184 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); 128 185 if (write_rd == 1) … … 134 191 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); 135 192 136 rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy; 193 RAT_GPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy; 194 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true; 137 195 } 138 196 … … 146 204 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); 147 205 148 rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy; 149 } 150 151 if (save) 152 { 153 // Need save RAT 154 155 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 156 157 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth old - new : %d",depth); 158 159 // #ifdef DEBUG_TEST 160 // if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id])) 161 // throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth)); 162 // #endif 163 164 // save GPR 165 for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) 166 rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr]; 167 168 // save SPR 169 for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) 170 rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr]; 171 172 // update rat_depth with new depth 173 rat_depth[front_end_id][context_id] = depth; 206 RAT_SPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy; 207 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true; 174 208 } 175 209 } … … 179 213 // ===================================================== 180 214 // Second : interface retire 181 // (because if an event on the same thread : the instruction is already renamed) 182 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 183 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 184 { 215 // if event AND event is exception, restore rat_NOT_SPECULATIVE 216 217 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 218 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 219 { 185 220 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); 186 221 187 // if no event : no effect, because the RAT content the most recently register188 // but if they have a event (exception or miss speculation), the rat must restore the oldest value189 // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register190 // the retire interface became of the Re Order Buffer, also is in program sequence !191 192 #ifdef DEBUG193 222 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; 194 223 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; 195 #endif196 224 Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); 197 225 Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); … … 206 234 if (write_rd == 1) 207 235 { 208 #ifdef DEBUG209 236 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); 210 #endif211 237 212 238 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); … … 214 240 if (not restore) 215 241 { 216 #ifdef DEBUG217 242 Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 218 #endif 243 219 244 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); 220 245 221 // rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;246 RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; 222 247 } 223 248 } … … 226 251 if (write_re == 1) 227 252 { 228 #ifdef DEBUG229 253 Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); 254 255 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); 256 257 if (not restore) 258 { 259 Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 260 261 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 262 263 RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 264 } 265 } 266 } 267 268 // ===================================================== 269 // ====[ DEPTH ]======================================== 270 // ===================================================== 271 #if 1 272 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 273 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 274 { 275 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * DEPTH[%d][%d]",i,j); 276 277 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; 278 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; 279 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); 280 281 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); 282 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); 283 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); 284 285 if (not depth_full) 286 { 287 Tdepth_t depth = depth_max; 288 289 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 290 { 291 if (depth == depth_min) 292 break; 293 294 if (reg_RAT_USE[i][j][depth]) 295 { 296 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",depth); 297 298 free_rat [i][j][depth] = true; 299 // reg_RAT_USE[i][j][depth] = false; 300 301 // for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) 302 // RAT_GPR_SPECULATIVE_VALID [i][j][depth][l] = false; 303 // for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) 304 // RAT_SPR_SPECULATIVE_VALID [i][j][depth][l] = false; 305 } 306 307 depth = (depth+1)%_param->_nb_branch_speculated[i][j]; 308 } 309 } 310 } 230 311 #endif 231 232 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); 233 234 if (not restore) 235 { 236 #ifdef DEBUG 237 Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 238 #endif 239 240 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 241 242 // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 243 } 244 } 245 246 } 312 // ===================================================== 313 // ====[ FREE RAT ]===================================== 314 // ===================================================== 315 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 316 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 317 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 318 if (free_rat[i][j][k]) 319 { 320 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Free RAT : [%d][%d][%d]",i,j,k); 321 322 reg_RAT_USE[i][j][k] = false; 323 324 for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) 325 RAT_GPR_SPECULATIVE_VALID [i][j][k][l] = false; 326 for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) 327 RAT_SPR_SPECULATIVE_VALID [i][j][k][l] = false; 328 } 329 247 330 } 248 331 … … 255 338 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 256 339 { 257 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);258 259 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)340 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]); 341 342 for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) 260 343 { 261 344 std::string str = ""; 262 345 for (uint32_t x=0; x<limit; x++) 263 346 { 264 uint32_t index = k+x;347 uint32_t index = l+x; 265 348 if (index >= _param->_nb_general_register_logic) 266 349 break; 267 350 else 268 str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative[i][j][index]);351 str+=toString("GPR[%.4d] - %.5d | ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]); 269 352 } 270 353 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 271 354 } 272 355 273 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 274 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) 275 { 276 std::string str = ""; 277 for (uint32_t x=0; x<limit; x++) 278 { 279 uint32_t index = k+x; 280 if (index >= _param->_nb_general_register_logic) 281 break; 282 else 283 str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]); 284 } 285 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 286 } 287 288 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 356 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 357 { 358 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); 359 360 for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) 361 { 362 std::string str = ""; 363 for (uint32_t x=0; x<limit; x++) 364 { 365 uint32_t index = l+x; 366 if (index >= _param->_nb_general_register_logic) 367 break; 368 else 369 str+=toString("GPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]); 370 } 371 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 372 } 373 } 374 375 for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) 289 376 { 290 377 std::string str = ""; … … 292 379 for (uint32_t x=0; x<limit; x++) 293 380 { 294 uint32_t index = k+x;381 uint32_t index = l+x; 295 382 if (index >= _param->_nb_special_register_logic) 296 383 break; 297 384 else 298 str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative[i][j][index]);385 str+=toString("SPR[%.4d] - %.5d | ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]); 299 386 } 300 387 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 301 388 } 302 389 303 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 304 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 305 { 306 std::string str = ""; 307 for (uint32_t x=0; x<limit; x++) 308 { 309 uint32_t index = k+x; 310 if (index >= _param->_nb_special_register_logic) 311 break; 312 else 313 str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]); 314 } 315 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 316 } 317 390 391 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 392 { 393 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); 394 395 for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) 396 { 397 std::string str = ""; 398 399 for (uint32_t x=0; x<limit; x++) 400 { 401 uint32_t index = l+x; 402 if (index >= _param->_nb_special_register_logic) 403 break; 404 else 405 str+=toString("SPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]); 406 } 407 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 408 } 409 } 318 410 } 319 411 }
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