[139] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Register_Address_Translation_unit_function_depth_save_transition.cpp 144 2010-09-28 11:19:10Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace rename_unit { |
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| 17 | namespace register_translation_unit { |
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| 18 | namespace register_address_translation_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Register_Address_Translation_unit::function_depth_save_transition" |
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| 23 | void Register_Address_Translation_unit::function_depth_save_transition (void) |
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| 24 | { |
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| 25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
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| 26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
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| 27 | |
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| 28 | if (PORT_READ(in_NRESET) == 0) |
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| 29 | { |
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| 30 | uint32_t gpr = 1; |
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| 31 | uint32_t spr = 0; |
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| 32 | |
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| 33 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 34 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 35 | { |
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| 36 | rat_depth [i][j] = 0; |
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| 37 | rat_gpr_speculative [i][j][0] = 0; |
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| 38 | |
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| 39 | for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) |
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| 40 | rat_gpr_speculative [i][j][k] = gpr++; |
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| 41 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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| 42 | rat_spr_speculative [i][j][k] = spr++; // not necessary |
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| 43 | } |
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| 44 | } |
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| 45 | else |
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| 46 | { |
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| 47 | // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) |
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| 48 | |
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| 49 | // ===================================================== |
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| 50 | // ====[ RETIRE_EVENT ]================================= |
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| 51 | // ===================================================== |
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| 52 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 53 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 54 | if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) |
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| 55 | { |
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| 56 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j); |
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| 57 | |
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| 58 | // Test if event have just occure |
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| 59 | if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) |
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| 60 | { |
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| 61 | switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) |
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| 62 | { |
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| 63 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
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| 64 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
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| 65 | { |
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| 66 | // Miss speculation (branch or load) |
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| 67 | // Restore contexte and update depth |
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| 68 | |
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| 69 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * MISS_SPECULATION : Restore RAT"); |
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| 70 | |
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| 71 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0; |
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| 72 | |
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| 73 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); |
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| 74 | |
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| 75 | // restore GPR |
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| 76 | for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) |
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| 77 | rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr]; |
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| 78 | |
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| 79 | // restore SPR |
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| 80 | for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) |
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| 81 | rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr]; |
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| 82 | |
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| 83 | // update rat_depth |
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| 84 | rat_depth[i][j] = depth; |
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| 85 | |
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| 86 | break; |
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| 87 | } |
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| 88 | // case EVENT_TYPE_EXCEPTION : |
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| 89 | // case EVENT_TYPE_SPR_ACCESS : |
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| 90 | // case EVENT_TYPE_MSYNC : |
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| 91 | // case EVENT_TYPE_PSYNC : |
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| 92 | // case EVENT_TYPE_CSYNC : |
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| 93 | default : |
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| 94 | { |
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| 95 | // nothing |
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| 96 | break; |
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| 97 | } |
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| 98 | } |
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| 99 | |
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| 100 | } |
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| 101 | } |
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| 102 | |
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| 103 | // ===================================================== |
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| 104 | // ====[ INSERT ]======================================= |
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| 105 | // ===================================================== |
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| 106 | // First : interface insert |
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| 107 | // this instruction is speculative !!! |
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| 108 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 109 | // Test transaction |
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| 110 | if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) |
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| 111 | { |
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| 112 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); |
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| 113 | |
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| 114 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
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| 115 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
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| 116 | Tcontrol_t save = internal_RENAME_SAVE [i]; |
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| 117 | |
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| 118 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); |
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| 119 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); |
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| 120 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save : %d",save); |
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| 121 | |
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| 122 | // Test if write and modifie RAT (RD and RE) |
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| 123 | |
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| 124 | Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); |
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| 125 | Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); |
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| 126 | |
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| 127 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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| 128 | if (write_rd == 1) |
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| 129 | { |
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| 130 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]); |
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| 131 | Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); |
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| 132 | |
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| 133 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log); |
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| 134 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); |
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| 135 | |
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| 136 | rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy; |
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| 137 | } |
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| 138 | |
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| 139 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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| 140 | if (write_re == 1) |
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| 141 | { |
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| 142 | Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]); |
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| 143 | Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); |
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| 144 | |
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| 145 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log); |
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| 146 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); |
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| 147 | |
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| 148 | rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy; |
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| 149 | } |
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| 150 | |
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| 151 | if (save) |
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| 152 | { |
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| 153 | // Need save RAT |
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| 154 | |
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| 155 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; |
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| 156 | |
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| 157 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth old - new : %d",depth); |
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| 158 | |
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| 159 | // #ifdef DEBUG_TEST |
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| 160 | // if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id])) |
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| 161 | // throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth)); |
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| 162 | // #endif |
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| 163 | |
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| 164 | // save GPR |
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| 165 | for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) |
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| 166 | rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr]; |
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| 167 | |
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| 168 | // save SPR |
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| 169 | for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) |
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| 170 | rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr]; |
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| 171 | |
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| 172 | // update rat_depth with new depth |
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| 173 | rat_depth[front_end_id][context_id] = depth; |
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| 174 | } |
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| 175 | } |
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| 176 | |
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| 177 | // ===================================================== |
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| 178 | // ====[ RETIRE ]======================================= |
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| 179 | // ===================================================== |
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| 180 | // Second : interface retire |
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| 181 | // (because if an event on the same thread : the instruction is already renamed) |
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| 182 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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| 183 | if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) |
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| 184 | { |
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| 185 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); |
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| 186 | |
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| 187 | // if no event : no effect, because the RAT content the most recently register |
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| 188 | // but if they have a event (exception or miss speculation), the rat must restore the oldest value |
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| 189 | // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register |
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| 190 | // the retire interface became of the Re Order Buffer, also is in program sequence ! |
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| 191 | |
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[144] | 192 | #ifdef DEBUG |
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[139] | 193 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; |
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| 194 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; |
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[144] | 195 | #endif |
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[139] | 196 | Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); |
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| 197 | Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); |
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| 198 | Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); |
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| 199 | |
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| 200 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 201 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); |
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| 202 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore ); |
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| 203 | |
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| 204 | // Test if write and have not a previous update |
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| 205 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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| 206 | if (write_rd == 1) |
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| 207 | { |
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[144] | 208 | #ifdef DEBUG |
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[139] | 209 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); |
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[144] | 210 | #endif |
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[139] | 211 | |
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| 212 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); |
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| 213 | |
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| 214 | if (not restore) |
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| 215 | { |
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[144] | 216 | #ifdef DEBUG |
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[139] | 217 | Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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[144] | 218 | #endif |
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[139] | 219 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); |
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| 220 | |
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| 221 | // rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; |
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| 222 | } |
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| 223 | } |
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| 224 | |
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| 225 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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| 226 | if (write_re == 1) |
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| 227 | { |
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[144] | 228 | #ifdef DEBUG |
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[139] | 229 | Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); |
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[144] | 230 | #endif |
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[139] | 231 | |
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| 232 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); |
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| 233 | |
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| 234 | if (not restore) |
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| 235 | { |
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[144] | 236 | #ifdef DEBUG |
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[139] | 237 | Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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[144] | 238 | #endif |
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[139] | 239 | |
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| 240 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); |
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| 241 | |
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| 242 | // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; |
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| 243 | } |
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| 244 | } |
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| 245 | |
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| 246 | } |
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| 247 | } |
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| 248 | |
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| 249 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) |
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| 250 | { |
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| 251 | uint32_t limit = 4; |
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| 252 | |
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| 253 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); |
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| 254 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 255 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 256 | { |
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| 257 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]); |
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| 258 | |
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| 259 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) |
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| 260 | { |
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| 261 | std::string str = ""; |
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| 262 | for (uint32_t x=0; x<limit; x++) |
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| 263 | { |
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| 264 | uint32_t index = k+x; |
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| 265 | if (index >= _param->_nb_general_register_logic) |
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| 266 | break; |
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| 267 | else |
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| 268 | str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative [i][j][index]); |
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| 269 | } |
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| 270 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 271 | } |
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| 272 | |
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| 273 | for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) |
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| 274 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) |
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| 275 | { |
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| 276 | std::string str = ""; |
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| 277 | for (uint32_t x=0; x<limit; x++) |
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| 278 | { |
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| 279 | uint32_t index = k+x; |
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| 280 | if (index >= _param->_nb_general_register_logic) |
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| 281 | break; |
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| 282 | else |
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| 283 | str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]); |
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| 284 | } |
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| 285 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 286 | } |
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| 287 | |
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| 288 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) |
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| 289 | { |
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| 290 | std::string str = ""; |
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| 291 | |
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| 292 | for (uint32_t x=0; x<limit; x++) |
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| 293 | { |
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| 294 | uint32_t index = k+x; |
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| 295 | if (index >= _param->_nb_special_register_logic) |
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| 296 | break; |
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| 297 | else |
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| 298 | str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative [i][j][index]); |
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| 299 | } |
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| 300 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 301 | } |
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| 302 | |
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| 303 | for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) |
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| 304 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) |
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| 305 | { |
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| 306 | std::string str = ""; |
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| 307 | for (uint32_t x=0; x<limit; x++) |
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| 308 | { |
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| 309 | uint32_t index = k+x; |
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| 310 | if (index >= _param->_nb_special_register_logic) |
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| 311 | break; |
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| 312 | else |
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| 313 | str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]); |
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| 314 | } |
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| 315 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 316 | } |
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| 317 | |
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| 318 | } |
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| 319 | } |
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| 320 | #endif |
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| 321 | |
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| 322 | log_end(Register_Address_Translation_unit,FUNCTION); |
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| 323 | }; |
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| 324 | |
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| 325 | }; // end namespace register_address_translation_unit |
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| 326 | }; // end namespace register_translation_unit |
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| 327 | }; // end namespace rename_unit |
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| 328 | }; // end namespace ooo_engine |
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| 329 | }; // end namespace multi_ooo_engine |
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| 330 | }; // end namespace core |
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| 331 | |
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| 332 | }; // end namespace behavioural |
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| 333 | }; // end namespace morpheo |
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| 334 | #endif |
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