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Register_Address_Translation_unit_function_depth_save_transition.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago
1) add test with SPECINT2K 2) new config of Selftest 3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table) 4) add Function_pointer but need fix
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File size: 20.4 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Register_Address_Translation_unit_function_depth_save_transition.cpp 145 2010-10-13 18:15:51Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace register_address_translation_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Register_Address_Translation_unit::function_depth_save_transition"
23	void Register_Address_Translation_unit::function_depth_save_transition (void)
24	{
25	log_begin(Register_Address_Translation_unit,FUNCTION);
26	log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
27
28	if (PORT_READ(in_NRESET) == 0)
29	{
30	uint32_t gpr = 1;
31	uint32_t spr = 0;
32
33	for (uint32_t i=0; i<_param->_nb_front_end; i++)
34	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
35	{
36	RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0;
37	RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false;
38	RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary
39
40	for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
41	{
42	RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++;
43	for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
44	{
45	RAT_GPR_SPECULATIVE_VALID [i][j][l][k] = false;
46	RAT_GPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary
47	}
48	}
49	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
50	{
51	RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++;
52	for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
53	{
54	RAT_SPR_SPECULATIVE_VALID [i][j][l][k] = false;
55	RAT_SPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary
56	}
57	}
58
59	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
60	reg_RAT_USE [i][j][k] = false;
61	reg_SAVE_RAT [i][j] = false;
62	}
63	}
64	else
65	{
66	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
67	bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated];
68	for (uint32_t i=0; i<_param->_nb_front_end; i++)
69	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
70	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
71	free_rat [i][j][k] = false;
72
73	// =====================================================
74	// ====[ RETIRE_EVENT ]=================================
75	// =====================================================
76	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
77	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
78	if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
79	{
80	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j);
81
82	// Test if event have just occure
83	// * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value)
84
85	if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
86	switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
87	{
88	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
89	{
90	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * BRANCH_MISS_SPECULATION - Reset Update Table");
91
92	reg_SAVE_RAT [i][j] = true;
93
94	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0;
95	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0;
96	Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0;
97	Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]);
98
99	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth);
100	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min);
101	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max);
102	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full);
103
104	Tdepth_t it = depth_min;
105
106	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
107	{
108	it = (it-1)%_param->_nb_branch_speculated[i][j];
109
110	if (it == depth)
111	break;
112
113	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",it);
114
115	free_rat[i][j][it] = true;
116	}
117
118	break;
119	}
120	case EVENT_TYPE_EXCEPTION :
121	{
122	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * EXCEPTION - Reset Update Table");
123
124	reg_SAVE_RAT [i][j] = true;
125
126	// Reset validity table
127	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
128	free_rat [i][j][k] = true;
129
130	break;
131	}
132	default :
133	{
134	break;
135	}
136	}
137	}
138
139	// =====================================================
140	// ====[ INSERT ]=======================================
141	// =====================================================
142	// First : interface insert
143	// this instruction is speculative !!!
144	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
145	// Test transaction
146	if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i])
147	{
148	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i);
149
150	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
151	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0;
152	Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]);
153	Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]);
154	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0;
155	Tcontrol_t save_rat = reg_SAVE_RAT[front_end_id][context_id];
156	// TODO SAVE_RAT
157
158	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id);
159	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id);
160	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth);
161	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",save_rat);
162
163	if (save_rat)
164	{
165	// #ifdef DEBUG_TEST
166	// if (reg_RAT_USE[front_end_id][context_id][depth])
167	// throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth));
168	// #endif
169	reg_RAT_USE[front_end_id][context_id][depth] = true;
170
171	// new branch, new RAT
172	for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++)
173	RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false;
174	for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++)
175	RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false;
176	}
177
178	save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]);
179	reg_SAVE_RAT[front_end_id][context_id] = save_rat;
180
181	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat);
182
183	// Test if write and modifie RAT
184	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
185	if (write_rd == 1)
186	{
187	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
188	Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
189
190	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log);
191	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy);
192
193	RAT_GPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy;
194	RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true;
195	}
196
197	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
198	if (write_re == 1)
199	{
200	Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
201	Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
202
203	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log);
204	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy);
205
206	RAT_SPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy;
207	RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true;
208	}
209	}
210
211	// =====================================================
212	// ====[ RETIRE ]=======================================
213	// =====================================================
214	// Second : interface retire
215	// if event AND event is exception, restore rat_NOT_SPECULATIVE
216
217	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
218	if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
219	{
220	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i);
221
222	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
223	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0;
224	Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]);
225	Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]);
226	Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]);
227
228	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
229	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id );
230	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore );
231
232	// Test if write and have not a previous update
233	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
234	if (write_rd == 1)
235	{
236	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
237
238	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log );
239
240	if (not restore)
241	{
242	Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
243
244	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
245
246	RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
247	}
248	}
249
250	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
251	if (write_re == 1)
252	{
253	Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
254
255	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log );
256
257	if (not restore)
258	{
259	Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
260
261	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new);
262
263	RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
264	}
265	}
266	}
267
268	// =====================================================
269	// ====[ DEPTH ]========================================
270	// =====================================================
271	#if 1
272	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
273	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
274	{
275	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * DEPTH[%d][%d]",i,j);
276
277	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0;
278	Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0;
279	Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]);
280
281	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min);
282	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max);
283	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full);
284
285	if (not depth_full)
286	{
287	Tdepth_t depth = depth_max;
288
289	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
290	{
291	if (depth == depth_min)
292	break;
293
294	if (reg_RAT_USE[i][j][depth])
295	{
296	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",depth);
297
298	free_rat [i][j][depth] = true;
299	// reg_RAT_USE[i][j][depth] = false;
300
301	// for (uint32_t l=0; l<_param->_nb_general_register_logic; l++)
302	// RAT_GPR_SPECULATIVE_VALID [i][j][depth][l] = false;
303	// for (uint32_t l=0; l<_param->_nb_special_register_logic; l++)
304	// RAT_SPR_SPECULATIVE_VALID [i][j][depth][l] = false;
305	}
306
307	depth = (depth+1)%_param->_nb_branch_speculated[i][j];
308	}
309	}
310	}
311	#endif
312	// =====================================================
313	// ====[ FREE RAT ]=====================================
314	// =====================================================
315	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
316	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
317	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
318	if (free_rat[i][j][k])
319	{
320	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Free RAT : [%d][%d][%d]",i,j,k);
321
322	reg_RAT_USE[i][j][k] = false;
323
324	for (uint32_t l=0; l<_param->_nb_general_register_logic; l++)
325	RAT_GPR_SPECULATIVE_VALID [i][j][k][l] = false;
326	for (uint32_t l=0; l<_param->_nb_special_register_logic; l++)
327	RAT_SPR_SPECULATIVE_VALID [i][j][k][l] = false;
328	}
329
330	}
331
332	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
333	{
334	uint32_t limit = 4;
335
336	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)");
337	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
338	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
339	{
340	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]);
341
342	for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit)
343	{
344	std::string str = "";
345	for (uint32_t x=0; x<limit; x++)
346	{
347	uint32_t index = l+x;
348	if (index >= _param->_nb_general_register_logic)
349	break;
350	else
351	str+=toString("GPR[%.4d] - %.5d \| ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]);
352	}
353	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
354	}
355
356	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
357	{
358	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]);
359
360	for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit)
361	{
362	std::string str = "";
363	for (uint32_t x=0; x<limit; x++)
364	{
365	uint32_t index = l+x;
366	if (index >= _param->_nb_general_register_logic)
367	break;
368	else
369	str+=toString("GPR[%.4d][%.4d] - %.1d %.5d \| ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]);
370	}
371	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
372	}
373	}
374
375	for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit)
376	{
377	std::string str = "";
378
379	for (uint32_t x=0; x<limit; x++)
380	{
381	uint32_t index = l+x;
382	if (index >= _param->_nb_special_register_logic)
383	break;
384	else
385	str+=toString("SPR[%.4d] - %.5d \| ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]);
386	}
387	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
388	}
389
390
391	for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k)
392	{
393	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]);
394
395	for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit)
396	{
397	std::string str = "";
398
399	for (uint32_t x=0; x<limit; x++)
400	{
401	uint32_t index = l+x;
402	if (index >= _param->_nb_special_register_logic)
403	break;
404	else
405	str+=toString("SPR[%.4d][%.4d] - %.1d %.5d \| ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]);
406	}
407	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
408	}
409	}
410	}
411	}
412	#endif
413
414	log_end(Register_Address_Translation_unit,FUNCTION);
415	};
416
417	}; // end namespace register_address_translation_unit
418	}; // end namespace register_translation_unit
419	}; // end namespace rename_unit
420	}; // end namespace ooo_engine
421	}; // end namespace multi_ooo_engine
422	}; // end namespace core
423
424	}; // end namespace behavioural
425	}; // end namespace morpheo
426	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp @ 145

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